2021-06-11 09:14:13

by Cristian Ciocaltea

Subject: [PATCH v2 2/2] ARM: dts: owl-s500-roseapplepi: Add ethernet support

Add pinctrl configuration for enabling the Ethernet MAC on RoseapplePi
SBC. Additionally, provide the necessary properties for the generic S500
ethernet node in order to setup PHY and MDIO.

Signed-off-by: Cristian Ciocaltea <[email protected]>
---
arch/arm/boot/dts/owl-s500-roseapplepi.dts | 45 ++++++++++++++++++++++
1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
index b8c5db2344aa..eb555f385283 100644
--- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -225,6 +225,27 @@ bias1-pinconf {
bias-pull-down;
};
};
+
+ ethernet_pins: ethernet-pins {
+ eth_rmii-pinmux {
+ groups = "rmii_txd0_mfp", "rmii_txd1_mfp",
+ "rmii_rxd0_mfp", "rmii_rxd1_mfp",
+ "rmii_txen_mfp", "rmii_rxen_mfp",
+ "rmii_crs_dv_mfp", "rmii_ref_clk_mfp";
+ function = "eth_rmii";
+ };
+
+ phy_clk-pinmux {
+ groups = "clko_25m_mfp";
+ function = "clko_25m";
+ };
+
+ ref_clk-pinconf {
+ groups = "rmii_ref_clk_drv";
+ drive-strength = <2>;
+ };
+
+ };
};

/* uSD */
@@ -241,6 +262,30 @@ &mmc0 {
vqmmc-supply = <&sd_vcc>;
};

+&ethernet {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ethernet_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&eth_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reset-gpios = <&pinctrl 88 GPIO_ACTIVE_LOW>; /* GPIOC24 */
+ reset-delay-us = <10000>;
+ reset-post-delay-us = <150000>;
+
+ eth_phy: ethernet-phy@3 {
+ reg = <0x3>;
+ max-speed = <100>;
+ interrupt-parent = <&sirq>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
&twd_timer {
status = "okay";
};
--
2.32.0

2021-06-14 11:41:30

by Manivannan Sadhasivam

Subject: Re: [PATCH v2 2/2] ARM: dts: owl-s500-roseapplepi: Add ethernet support

On Fri, Jun 11, 2021 at 12:11:33PM +0300, Cristian Ciocaltea wrote:
> Add pinctrl configuration for enabling the Ethernet MAC on RoseapplePi
> SBC. Additionally, provide the necessary properties for the generic S500
> ethernet node in order to setup PHY and MDIO.
>
> Signed-off-by: Cristian Ciocaltea <[email protected]>

Reviewed-by: Manivannan Sadhasivam <[email protected]>

Thanks,
Mani

> ---
> arch/arm/boot/dts/owl-s500-roseapplepi.dts | 45 ++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> index b8c5db2344aa..eb555f385283 100644
> --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> @@ -225,6 +225,27 @@ bias1-pinconf {
> bias-pull-down;
> };
> };
> +
> + ethernet_pins: ethernet-pins {
> + eth_rmii-pinmux {
> + groups = "rmii_txd0_mfp", "rmii_txd1_mfp",
> + "rmii_rxd0_mfp", "rmii_rxd1_mfp",
> + "rmii_txen_mfp", "rmii_rxen_mfp",
> + "rmii_crs_dv_mfp", "rmii_ref_clk_mfp";
> + function = "eth_rmii";
> + };
> +
> + phy_clk-pinmux {
> + groups = "clko_25m_mfp";
> + function = "clko_25m";
> + };
> +
> + ref_clk-pinconf {
> + groups = "rmii_ref_clk_drv";
> + drive-strength = <2>;
> + };
> +
> + };
> };
>
> /* uSD */
> @@ -241,6 +262,30 @@ &mmc0 {
> vqmmc-supply = <&sd_vcc>;
> };
>
> +&ethernet {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ethernet_pins>;
> + phy-mode = "rmii";
> + phy-handle = <&eth_phy>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reset-gpios = <&pinctrl 88 GPIO_ACTIVE_LOW>; /* GPIOC24 */
> + reset-delay-us = <10000>;
> + reset-post-delay-us = <150000>;
> +
> + eth_phy: ethernet-phy@3 {
> + reg = <0x3>;
> + max-speed = <100>;
> + interrupt-parent = <&sirq>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + };
> + };
> +};
> +
> &twd_timer {
> status = "okay";
> };
> --
> 2.32.0
>