Hi All,
RZ/G2L has a simple pin and GPIO controller combined similar to RZ/A2.
Second patch adds the core wrapper for RZ/G2L family and third patch
defines pins/groups/functions for i2c/scif/usb supported by RZ/G2L Soc.
Cheers,
Prabhakar
Lad Prabhakar (3):
dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add DT bindings for
RZ/G2L pinctrl
pinctrl: renesas: Add RZ/G2L pin and gpio controller core wrapper
pinctrl: renesas: Add pins/groups/functions for I2C, SCIF and USB
supported by RZ/G2L SoC
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 121 ++++
drivers/pinctrl/renesas/Kconfig | 16 +
drivers/pinctrl/renesas/Makefile | 2 +
drivers/pinctrl/renesas/pfc-r9a07g044.c | 362 ++++++++++++
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 536 ++++++++++++++++++
drivers/pinctrl/renesas/pinctrl-rzg2l.h | 96 ++++
include/dt-bindings/pinctrl/pinctrl-rzg2l.h | 16 +
7 files changed, 1149 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
create mode 100644 drivers/pinctrl/renesas/pfc-r9a07g044.c
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.c
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.h
create mode 100644 include/dt-bindings/pinctrl/pinctrl-rzg2l.h
--
2.17.1
Add device tree binding documentation and header file for Renesas
RZ/G2L pinctrl.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 121 ++++++++++++++++++
include/dt-bindings/pinctrl/pinctrl-rzg2l.h | 16 +++
2 files changed, 137 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
create mode 100644 include/dt-bindings/pinctrl/pinctrl-rzg2l.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
new file mode 100644
index 000000000000..e8ab5a0a46b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L combined Pin and GPIO controller
+
+maintainers:
+ - Geert Uytterhoeven <[email protected]>
+
+description:
+ The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
+ controller.
+ Pin multiplexing and GPIO configuration is performed on a per-pin basis.
+ Each port features up to 8 pins, each of them configurable for GPIO function
+ (port mode) or in alternate function mode.
+ Up to 8 different alternate function modes exist for each single pin.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+ description:
+ The first cell contains the global GPIO port index, constructed using the
+ RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/pinctrl-rzg2l.h> and the
+ second cell represents consumer flag as mentioned in ../gpio/gpio.txt
+ E.g. "RZG2L_GPIO(39, 1)" for P39_1.
+
+ gpio-ranges:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+additionalProperties:
+ anyOf:
+ - type: object
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ description:
+ Pin controller client devices use pin configuration subnodes (children
+ and grandchildren) for desired pin configuration.
+ Client device subnodes use below standard properties.
+
+ properties:
+ phandle: true
+ function: true
+ groups: true
+ pins: true
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+ power-source:
+ enum: [ 1800, 2500, 3300 ]
+ slew-rate: true
+ gpio-hog: true
+ gpios: true
+ input-enable: true
+ output-high: true
+ output-low: true
+ line-name: true
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+ - clocks
+ - power-domains
+ - resets
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/pinctrl-rzg2l.h>
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ pinctrl: pinctrl@11030000 {
+ compatible = "renesas,r9a07g044l-pinctrl";
+ reg = <0x11030000 0x10000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 392>;
+ clocks = <&cpg CPG_MOD R9A07G044_CLK_GPIO>;
+ resets = <&cpg R9A07G044_CLK_GPIO>;
+ power-domains = <&cpg>;
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ sd1-pwr-en-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(39, 2) 0>;
+ output-high;
+ line-name = "sd1_pwr_en";
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/pinctrl-rzg2l.h b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h
new file mode 100644
index 000000000000..d285d9e8c60a
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G2{L,LC} pinctrl bindings.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RZG2L_H
+#define __DT_BINDINGS_PINCTRL_RZG2L_H
+
+#define RZG2L_PINS_PER_PORT 8
+
+#define RZG2L_GPIO(port, pos) ((port) * RZG2L_PINS_PER_PORT + (pos))
+
+#endif /* __DT_BINDINGS_PINCTRL_RZG2L_H */
--
2.17.1
Add pins/groups/functions for I2C, SCIF and USB supported by RZ/G2L SoC and
bind it with RZ/G2L PFC core.
Based on a patch in the BSP by Hien Huynh <[email protected]>.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
drivers/pinctrl/renesas/Kconfig | 5 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pfc-r9a07g044.c | 362 ++++++++++++++++++++++++
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 +
drivers/pinctrl/renesas/pinctrl-rzg2l.h | 2 +
5 files changed, 376 insertions(+)
create mode 100644 drivers/pinctrl/renesas/pfc-r9a07g044.c
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 2b4ac226ce35..dc7faa6eaeb1 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -37,6 +37,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
+ select PINCTRL_PFC_R9A07G044 if ARCH_R9A07G044
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -155,6 +156,10 @@ config PINCTRL_PFC_R8A73A4
bool "pin control support for R-Mobile APE6" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
+config PINCTRL_PFC_R9A07G044
+ bool "pin control support for RZ/G2L" if COMPILE_TEST
+ select PINCTRL_RZG2L
+
config PINCTRL_RZA1
bool "pin control support for RZ/A1"
depends on OF
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 7d9238a9ef57..2ea5fa3a7769 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
+obj-$(CONFIG_PINCTRL_PFC_R9A07G044) += pfc-r9a07g044.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/renesas/pfc-r9a07g044.c b/drivers/pinctrl/renesas/pfc-r9a07g044.c
new file mode 100644
index 000000000000..3f2ef4f52173
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r9a07g044.c
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R9A07G044 processor support - pinctrl GPIO hardware block.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "pinctrl-rzg2l.h"
+
+#define RZG2L_GPIO_PIN_CONF (0)
+
+static const struct {
+ struct pinctrl_pin_desc pin_gpio[392];
+} pinmux_pins = {
+ .pin_gpio = {
+ RZ_G2L_PINCTRL_PIN_GPIO(0, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(1, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(2, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(3, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(4, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(5, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(6, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(7, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(8, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(9, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(10, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(11, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(12, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(13, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(14, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(15, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(16, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(17, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(18, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(19, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(20, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(21, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(22, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(23, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(24, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(25, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(26, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(27, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(28, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(29, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(30, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(31, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(32, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(33, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(34, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(35, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(36, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(37, 0),
+ RZ_G2L_PINCTRL_PIN_GPIO(38, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(39, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(40, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(41, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(42, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(43, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(44, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(45, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(46, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(47, RZG2L_GPIO_PIN_CONF),
+ RZ_G2L_PINCTRL_PIN_GPIO(48, RZG2L_GPIO_PIN_CONF),
+ },
+};
+
+/* - RIIC2 ------------------------------------------------------------------ */
+static int i2c2_a_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(3, 0), RZ_G2L_PIN(3, 1),
+};
+static int i2c2_b_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(19, 0), RZ_G2L_PIN(19, 1),
+};
+static int i2c2_c_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(42, 3), RZ_G2L_PIN(42, 4),
+};
+static int i2c2_d_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(46, 0), RZ_G2L_PIN(46, 1),
+};
+static int i2c2_e_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(48, 0), RZ_G2L_PIN(48, 1),
+};
+/* - RIIC3 ------------------------------------------------------------------ */
+static int i2c3_a_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(8, 1), RZ_G2L_PIN(8, 0),
+};
+static int i2c3_b_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(18, 0), RZ_G2L_PIN(18, 1),
+};
+static int i2c3_c_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(46, 2), RZ_G2L_PIN(46, 3),
+};
+static int i2c3_d_pins[] = {
+ /* SDA, SCL */
+ RZ_G2L_PIN(48, 2), RZ_G2L_PIN(48, 3),
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static int scif0_clk_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(39, 0),
+};
+static int scif0_ctrl_pins[] = {
+ /* CTS, RTS */
+ RZ_G2L_PIN(39, 1), RZ_G2L_PIN(39, 2),
+};
+static int scif0_data_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(38, 0), RZ_G2L_PIN(38, 1),
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static int scif1_clk_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(40, 2),
+};
+static int scif1_ctrl_pins[] = {
+ /* CTS, RTS */
+ RZ_G2L_PIN(41, 0), RZ_G2L_PIN(41, 1),
+};
+static int scif1_data_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(40, 0), RZ_G2L_PIN(40, 1),
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static int scif2_clk_a_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(5, 0),
+};
+static int scif2_clk_b_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(17, 0),
+};
+static int scif2_clk_c_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(37, 0),
+};
+static int scif2_clk_d_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(42, 2),
+};
+static int scif2_clk_e_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(48, 2),
+};
+static int scif2_ctrl_a_pins[] = {
+ /* CTS, RTS */
+ RZ_G2L_PIN(5, 1), RZ_G2L_PIN(5, 2),
+};
+static int scif2_ctrl_b_pins[] = {
+ /* CTS, RTS */
+ RZ_G2L_PIN(17, 1), RZ_G2L_PIN(17, 2),
+};
+static int scif2_ctrl_c_pins[] = {
+ /* CTS, RTS */
+ RZ_G2L_PIN(37, 1), RZ_G2L_PIN(37, 2),
+};
+static int scif2_ctrl_d_pins[] = {
+ /* CTS, RTS */
+ RZ_G2L_PIN(42, 3), RZ_G2L_PIN(42, 4),
+};
+static int scif2_ctrl_e_pins[] = {
+ /* CTS, RTS */
+ RZ_G2L_PIN(48, 3), RZ_G2L_PIN(48, 4),
+};
+static int scif2_data_a_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(4, 0), RZ_G2L_PIN(4, 1),
+};
+static int scif2_data_b_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(16, 0), RZ_G2L_PIN(16, 1),
+};
+static int scif2_data_c_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(33, 0), RZ_G2L_PIN(33, 1),
+};
+static int scif2_data_d_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(42, 0), RZ_G2L_PIN(42, 1),
+};
+static int scif2_data_e_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(48, 0), RZ_G2L_PIN(48, 1),
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static int scif3_clk_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(1, 0),
+};
+static int scif3_data_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(0, 0), RZ_G2L_PIN(0, 1),
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static int scif4_clk_pins[] = {
+ /* SCK */
+ RZ_G2L_PIN(3, 0),
+};
+static int scif4_data_pins[] = {
+ /* TX, RX */
+ RZ_G2L_PIN(2, 0), RZ_G2L_PIN(2, 1),
+};
+
+/* - USB0 ------------------------------------------------------------------- */
+static int usb0_a_pins[] = {
+ /* VBUS, OVC */
+ RZ_G2L_PIN(4, 0), RZ_G2L_PIN(5, 0),
+};
+static int usb0_a_otg_exicen_pins[] = {
+ /* OTG_EXICEN */
+ RZ_G2L_PIN(5, 2),
+};
+static int usb0_a_otg_id_pins[] = {
+ /* OTG_ID */
+ RZ_G2L_PIN(5, 1),
+};
+static int usb0_b_pins[] = {
+ /* VBUS, OVC */
+ RZ_G2L_PIN(6, 0), RZ_G2L_PIN(7, 0),
+};
+static int usb0_b_otg_exicen_pins[] = {
+ /* OTG_EXICEN */
+ RZ_G2L_PIN(7, 2),
+};
+static int usb0_b_otg_id_pins[] = {
+ /* OTG_ID */
+ RZ_G2L_PIN(7, 1),
+};
+/* - USB1 ------------------------------------------------------------------- */
+static int usb1_a_pins[] = {
+ /* VBUS, OVC */
+ RZ_G2L_PIN(8, 0), RZ_G2L_PIN(8, 1),
+};
+static int usb1_b_pins[] = {
+ /* VBUS, OVC */
+ RZ_G2L_PIN(29, 0), RZ_G2L_PIN(29, 1),
+};
+static int usb1_c_pins[] = {
+ /* VBUS, OVC */
+ RZ_G2L_PIN(38, 0), RZ_G2L_PIN(38, 1),
+};
+static int usb1_d_pins[] = {
+ /* VBUS, OVC */
+ RZ_G2L_PIN(42, 0), RZ_G2L_PIN(42, 1),
+};
+
+static struct group_desc pinmux_groups[] = {
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c2_a, 2),
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c2_b, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c2_c, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c2_d, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c2_e, 3),
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c3_a, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c3_b, 3),
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c3_c, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(i2c3_d, 3),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif0_clk, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif0_ctrl, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif0_data, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif1_clk, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif1_ctrl, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif1_data, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_clk_a, 2),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_clk_b, 2),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_clk_c, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_clk_d, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_clk_e, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_ctrl_a, 2),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_ctrl_b, 2),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_ctrl_c, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_ctrl_d, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_ctrl_e, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_data_a, 2),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_data_b, 2),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_data_c, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_data_d, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif2_data_e, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif3_clk, 5),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif3_data, 5),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif4_clk, 5),
+ RZ_G2L_PINCTRL_PIN_GROUP(scif4_data, 5),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb0_a, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb0_a_otg_exicen, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb0_a_otg_id, 1),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb0_b, 3),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb0_b_otg_exicen, 3),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb0_b_otg_id, 3),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb1_a, 2),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb1_b, 4),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb1_c, 5),
+ RZ_G2L_PINCTRL_PIN_GROUP(usb1_d, 1),
+};
+
+static const char *i2c2_groups[] = {
+ "i2c2_a", "i2c2_b", "i2c2_c", "i2c2_d", "i2c2_e",
+};
+
+static const char *i2c3_groups[] = {
+ "i2c3_a", "i2c3_b", "i2c3_c", "i2c3_d",
+};
+
+static const char *scif0_groups[] = {
+ "scif0_clk", "scif0_ctrl", "scif0_data",
+};
+
+static const char *scif1_groups[] = {
+ "scif1_clk", "scif1_ctrl", "scif1_data",
+};
+
+static const char *scif2_groups[] = {
+ "scif2_clk_a", "scif2_clk_b", "scif2_clk_c", "scif2_clk_d", "scif2_clk_e",
+ "scif2_ctrl_a", "scif2_ctrl_b", "scif2_ctrl_c", "scif2_ctrl_d", "scif2_ctrl_e",
+ "scif2_data_a", "scif2_data_b", "scif2_data_c", "scif2_data_d", "scif2_data_e",
+};
+
+static const char *scif3_groups[] = {
+ "scif3_clk", "scif3_data",
+};
+
+static const char *scif4_groups[] = {
+ "scif4_clk", "scif4_data",
+};
+
+static const char *usb0_groups[] = {
+ "usb0_a", "usb0_a_otg_exicen", "usb0_a_otg_id",
+ "usb0_b", "usb0_b_otg_exicen", "usb0_b_otg_id",
+};
+
+static const char *usb1_groups[] = {
+ "usb1_a", "usb1_b", "usb1_c", "usb1_d",
+};
+
+static const struct function_desc pinmux_functions[] = {
+ RZ_G2L_FN_DESC(i2c2),
+ RZ_G2L_FN_DESC(i2c3),
+ RZ_G2L_FN_DESC(scif0),
+ RZ_G2L_FN_DESC(scif1),
+ RZ_G2L_FN_DESC(scif2),
+ RZ_G2L_FN_DESC(scif3),
+ RZ_G2L_FN_DESC(scif4),
+ RZ_G2L_FN_DESC(usb0),
+ RZ_G2L_FN_DESC(usb1),
+};
+
+const struct rzg2l_pin_soc r9a07g044_pinctrl_data = {
+ .pins = pinmux_pins.pin_gpio,
+ .npins = ARRAY_SIZE(pinmux_pins.pin_gpio),
+ .groups = pinmux_groups,
+ .ngroups = ARRAY_SIZE(pinmux_groups),
+ .funcs = pinmux_functions,
+ .nfuncs = ARRAY_SIZE(pinmux_functions),
+ .nports = ARRAY_SIZE(pinmux_pins.pin_gpio) / RZG2L_MAX_PINS_PER_PORT,
+};
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index b9730b53fd85..a1d67409c649 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -512,6 +512,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
}
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R9A07G044
+ {
+ .compatible = "renesas,r9a07g044-pinctrl",
+ .data = &r9a07g044_pinctrl_data,
+ },
+#endif
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.h b/drivers/pinctrl/renesas/pinctrl-rzg2l.h
index 39135e5bc04e..c6f178c8d916 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.h
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.h
@@ -91,4 +91,6 @@ struct rzg2l_pin_soc {
#define RZ_G2L_FN_DESC(id) { #id, id##_groups, ARRAY_SIZE(id##_groups) }
+extern const struct rzg2l_pin_soc r9a07g044_pinctrl_data;
+
#endif
--
2.17.1
On Wed, 16 Jun 2021 14:26:39 +0100, Lad Prabhakar wrote:
> Add device tree binding documentation and header file for Renesas
> RZ/G2L pinctrl.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
> ---
> .../pinctrl/renesas,rzg2l-pinctrl.yaml | 121 ++++++++++++++++++
> include/dt-bindings/pinctrl/pinctrl-rzg2l.h | 16 +++
> 2 files changed, 137 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> create mode 100644 include/dt-bindings/pinctrl/pinctrl-rzg2l.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.example.dts:20:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
20 | #include <dt-bindings/clock/r9a07g044-cpg.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1492923
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Wed, Jun 16, 2021 at 02:26:39PM +0100, Lad Prabhakar wrote:
> Add device tree binding documentation and header file for Renesas
> RZ/G2L pinctrl.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
> ---
> .../pinctrl/renesas,rzg2l-pinctrl.yaml | 121 ++++++++++++++++++
> include/dt-bindings/pinctrl/pinctrl-rzg2l.h | 16 +++
> 2 files changed, 137 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> create mode 100644 include/dt-bindings/pinctrl/pinctrl-rzg2l.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> new file mode 100644
> index 000000000000..e8ab5a0a46b3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> @@ -0,0 +1,121 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L combined Pin and GPIO controller
> +
> +maintainers:
> + - Geert Uytterhoeven <[email protected]>
> +
> +description:
> + The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
> + controller.
> + Pin multiplexing and GPIO configuration is performed on a per-pin basis.
> + Each port features up to 8 pins, each of them configurable for GPIO function
> + (port mode) or in alternate function mode.
> + Up to 8 different alternate function modes exist for each single pin.
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
> +
> + reg:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> + description:
> + The first cell contains the global GPIO port index, constructed using the
> + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/pinctrl-rzg2l.h> and the
> + second cell represents consumer flag as mentioned in ../gpio/gpio.txt
> + E.g. "RZG2L_GPIO(39, 1)" for P39_1.
> +
> + gpio-ranges:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> +additionalProperties:
> + anyOf:
> + - type: object
Define a node name pattern for child nodes to match on rather than using
'additionalProperties'. '-pins$' for example.
> + allOf:
> + - $ref: pincfg-node.yaml#
> + - $ref: pinmux-node.yaml#
> +
> + description:
> + Pin controller client devices use pin configuration subnodes (children
> + and grandchildren) for desired pin configuration.
> + Client device subnodes use below standard properties.
> +
> + properties:
> + phandle: true
> + function: true
> + groups: true
> + pins: true
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> + drive-strength:
> + enum: [ 2, 4, 8, 12 ]
> + power-source:
> + enum: [ 1800, 2500, 3300 ]
> + slew-rate: true
> + gpio-hog: true
> + gpios: true
> + input-enable: true
> + output-high: true
> + output-low: true
> + line-name: true
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> + - clocks
> + - power-domains
> + - resets
> +
> +examples:
> + - |
> + #include <dt-bindings/pinctrl/pinctrl-rzg2l.h>
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> + pinctrl: pinctrl@11030000 {
> + compatible = "renesas,r9a07g044l-pinctrl";
> + reg = <0x11030000 0x10000>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 0 392>;
> + clocks = <&cpg CPG_MOD R9A07G044_CLK_GPIO>;
> + resets = <&cpg R9A07G044_CLK_GPIO>;
> + power-domains = <&cpg>;
> +
> + scif0_pins: scif0 {
> + groups = "scif0_data";
> + function = "scif0";
> + };
> +
> + sd1-pwr-en-hog {
> + gpio-hog;
> + gpios = <RZG2L_GPIO(39, 2) 0>;
> + output-high;
> + line-name = "sd1_pwr_en";
> + };
> + };
> diff --git a/include/dt-bindings/pinctrl/pinctrl-rzg2l.h b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h
> new file mode 100644
> index 000000000000..d285d9e8c60a
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * This header provides constants for Renesas RZ/G2{L,LC} pinctrl bindings.
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_RZG2L_H
> +#define __DT_BINDINGS_PINCTRL_RZG2L_H
> +
> +#define RZG2L_PINS_PER_PORT 8
> +
> +#define RZG2L_GPIO(port, pos) ((port) * RZG2L_PINS_PER_PORT + (pos))
> +
> +#endif /* __DT_BINDINGS_PINCTRL_RZG2L_H */
> --
> 2.17.1
Hi Lad,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on renesas-drivers/renesas-pinctrl]
[also build test WARNING on robh/for-next pinctrl/devel v5.13-rc6 next-20210616]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Lad-Prabhakar/pinctrl-Add-RZ-G2L-pin-and-gpio-driver/20210616-225928
base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl
config: parisc-randconfig-s031-20210617 (attached as .config)
compiler: hppa-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/0cc4856c569c78a2855607272bccac66fd3d8e9e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Lad-Prabhakar/pinctrl-Add-RZ-G2L-pin-and-gpio-driver/20210616-225928
git checkout 0cc4856c569c78a2855607272bccac66fd3d8e9e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=parisc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_set_mux':
drivers/pinctrl/renesas/pinctrl-rzg2l.c:115:9: error: implicit declaration of function 'pinmux_generic_get_function'; did you mean 'pinmux_generic_free_functions'? [-Werror=implicit-function-declaration]
115 | func = pinmux_generic_get_function(pctldev, func_selector);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinmux_generic_free_functions
>> drivers/pinctrl/renesas/pinctrl-rzg2l.c:115:7: warning: assignment to 'struct function_desc *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
115 | func = pinmux_generic_get_function(pctldev, func_selector);
| ^
drivers/pinctrl/renesas/pinctrl-rzg2l.c:118:10: error: implicit declaration of function 'pinctrl_generic_get_group' [-Werror=implicit-function-declaration]
118 | group = pinctrl_generic_get_group(pctldev, group_selector);
| ^~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pinctrl/renesas/pinctrl-rzg2l.c:118:8: warning: assignment to 'struct group_desc *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
118 | group = pinctrl_generic_get_group(pctldev, group_selector);
| ^
drivers/pinctrl/renesas/pinctrl-rzg2l.c:122:14: error: dereferencing pointer to incomplete type 'struct group_desc'
122 | pins = group->pins;
| ^~
In file included from include/linux/printk.h:409,
from include/linux/kernel.h:17,
from include/linux/list.h:9,
from include/linux/kobject.h:19,
from include/linux/of.h:17,
from drivers/pinctrl/renesas/pinctrl-rzg2l.c:8:
drivers/pinctrl/renesas/pinctrl-rzg2l.c:126:7: error: dereferencing pointer to incomplete type 'struct function_desc'
126 | func->name, group->name);
| ^~
include/linux/dynamic_debug.h:129:15: note: in definition of macro '__dynamic_func_call'
129 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:161:2: note: in expansion of macro '_dynamic_func_call'
161 | _dynamic_func_call(fmt,__dynamic_dev_dbg, \
| ^~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:123:2: note: in expansion of macro 'dynamic_dev_dbg'
123 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~
drivers/pinctrl/renesas/pinctrl-rzg2l.c:125:2: note: in expansion of macro 'dev_dbg'
125 | dev_dbg(pctldev->dev, "enable function %s group %s\n",
| ^~~~~~~
drivers/pinctrl/renesas/pinctrl-rzg2l.c: At top level:
drivers/pinctrl/renesas/pinctrl-rzg2l.c:135:22: error: 'pinctrl_generic_get_group_count' undeclared here (not in a function)
135 | .get_groups_count = pinctrl_generic_get_group_count,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/renesas/pinctrl-rzg2l.c:136:20: error: 'pinctrl_generic_get_group_name' undeclared here (not in a function)
136 | .get_group_name = pinctrl_generic_get_group_name,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/renesas/pinctrl-rzg2l.c:137:20: error: 'pinctrl_generic_get_group_pins' undeclared here (not in a function); did you mean 'pinctrl_get_group_pins'?
137 | .get_group_pins = pinctrl_generic_get_group_pins,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinctrl_get_group_pins
drivers/pinctrl/renesas/pinctrl-rzg2l.c:143:25: error: 'pinmux_generic_get_function_count' undeclared here (not in a function); did you mean 'pinmux_generic_free_functions'?
143 | .get_functions_count = pinmux_generic_get_function_count,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinmux_generic_free_functions
drivers/pinctrl/renesas/pinctrl-rzg2l.c:144:23: error: 'pinmux_generic_get_function_name' undeclared here (not in a function); did you mean 'pinmux_generic_free_functions'?
144 | .get_function_name = pinmux_generic_get_function_name,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinmux_generic_free_functions
drivers/pinctrl/renesas/pinctrl-rzg2l.c:145:25: error: 'pinmux_generic_get_function_groups' undeclared here (not in a function); did you mean 'pinmux_generic_free_functions'?
145 | .get_function_groups = pinmux_generic_get_function_groups,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinmux_generic_free_functions
drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_add_groups':
drivers/pinctrl/renesas/pinctrl-rzg2l.c:155:56: error: invalid use of undefined type 'struct group_desc'
155 | const struct group_desc *group = pctrl->psoc->groups + i;
| ^
drivers/pinctrl/renesas/pinctrl-rzg2l.c:157:9: error: implicit declaration of function 'pinctrl_generic_add_group' [-Werror=implicit-function-declaration]
157 | ret = pinctrl_generic_add_group(pctrl->pctrl_dev, group->name,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/renesas/pinctrl-rzg2l.c:157:58: error: dereferencing pointer to incomplete type 'const struct group_desc'
157 | ret = pinctrl_generic_add_group(pctrl->pctrl_dev, group->name,
| ^~
drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_add_functions':
drivers/pinctrl/renesas/pinctrl-rzg2l.c:175:57: error: invalid use of undefined type 'struct function_desc'
175 | const struct function_desc *func = pctrl->psoc->funcs + i;
| ^
drivers/pinctrl/renesas/pinctrl-rzg2l.c:177:9: error: implicit declaration of function 'pinmux_generic_add_function'; did you mean 'pinmux_generic_free_functions'? [-Werror=implicit-function-declaration]
177 | ret = pinmux_generic_add_function(pctrl->pctrl_dev, func->name,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinmux_generic_free_functions
drivers/pinctrl/renesas/pinctrl-rzg2l.c:177:59: error: dereferencing pointer to incomplete type 'const struct function_desc'
177 | ret = pinmux_generic_add_function(pctrl->pctrl_dev, func->name,
| ^~
At top level:
drivers/pinctrl/renesas/pinctrl-rzg2l.c:514:34: warning: 'rzg2l_pinctrl_of_table' defined but not used [-Wunused-const-variable=]
514 | static const struct of_device_id rzg2l_pinctrl_of_table[] = {
| ^~~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for PINCTRL_RZG2L
Depends on PINCTRL && OF && (ARCH_R9A07G044 || COMPILE_TEST
Selected by
- PINCTRL_PFC_R9A07G044 && PINCTRL
vim +115 drivers/pinctrl/renesas/pinctrl-rzg2l.c
64165286d371f1 Lad Prabhakar 2021-06-16 103
64165286d371f1 Lad Prabhakar 2021-06-16 104 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
64165286d371f1 Lad Prabhakar 2021-06-16 105 unsigned int func_selector,
64165286d371f1 Lad Prabhakar 2021-06-16 106 unsigned int group_selector)
64165286d371f1 Lad Prabhakar 2021-06-16 107 {
64165286d371f1 Lad Prabhakar 2021-06-16 108 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
64165286d371f1 Lad Prabhakar 2021-06-16 109 struct function_desc *func;
64165286d371f1 Lad Prabhakar 2021-06-16 110 struct group_desc *group;
64165286d371f1 Lad Prabhakar 2021-06-16 111 unsigned long data;
64165286d371f1 Lad Prabhakar 2021-06-16 112 int *pins;
64165286d371f1 Lad Prabhakar 2021-06-16 113 int i;
64165286d371f1 Lad Prabhakar 2021-06-16 114
64165286d371f1 Lad Prabhakar 2021-06-16 @115 func = pinmux_generic_get_function(pctldev, func_selector);
64165286d371f1 Lad Prabhakar 2021-06-16 116 if (!func)
64165286d371f1 Lad Prabhakar 2021-06-16 117 return -EINVAL;
64165286d371f1 Lad Prabhakar 2021-06-16 @118 group = pinctrl_generic_get_group(pctldev, group_selector);
64165286d371f1 Lad Prabhakar 2021-06-16 119 if (!group)
64165286d371f1 Lad Prabhakar 2021-06-16 120 return -EINVAL;
64165286d371f1 Lad Prabhakar 2021-06-16 121
64165286d371f1 Lad Prabhakar 2021-06-16 122 pins = group->pins;
64165286d371f1 Lad Prabhakar 2021-06-16 123 data = (unsigned long)group->data;
64165286d371f1 Lad Prabhakar 2021-06-16 124
64165286d371f1 Lad Prabhakar 2021-06-16 125 dev_dbg(pctldev->dev, "enable function %s group %s\n",
64165286d371f1 Lad Prabhakar 2021-06-16 126 func->name, group->name);
64165286d371f1 Lad Prabhakar 2021-06-16 127
64165286d371f1 Lad Prabhakar 2021-06-16 128 for (i = 0; i < group->num_pins; i++)
64165286d371f1 Lad Prabhakar 2021-06-16 129 rzg2l_pinctrl_set_pfc_mode(pctrl, *(pins + i), data);
64165286d371f1 Lad Prabhakar 2021-06-16 130
64165286d371f1 Lad Prabhakar 2021-06-16 131 return 0;
64165286d371f1 Lad Prabhakar 2021-06-16 132 };
64165286d371f1 Lad Prabhakar 2021-06-16 133
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
Hi Prabhakar,
On Wed, Jun 16, 2021 at 3:27 PM Lad Prabhakar
<[email protected]> wrote:
> Add device tree binding documentation and header file for Renesas
> RZ/G2L pinctrl.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> @@ -0,0 +1,121 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L combined Pin and GPIO controller
> +
> +maintainers:
> + - Geert Uytterhoeven <[email protected]>
> +
> +description:
> + The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
> + controller.
> + Pin multiplexing and GPIO configuration is performed on a per-pin basis.
> + Each port features up to 8 pins, each of them configurable for GPIO function
> + (port mode) or in alternate function mode.
> + Up to 8 different alternate function modes exist for each single pin.
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
> +
> + reg:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> + description:
> + The first cell contains the global GPIO port index, constructed using the
> + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/pinctrl-rzg2l.h> and the
<dt-bindings/pinctrl/rzg2l-pinctrl.h>, for consistency with other Renesas
header files?
> + second cell represents consumer flag as mentioned in ../gpio/gpio.txt
> + E.g. "RZG2L_GPIO(39, 1)" for P39_1.
> +
> + gpio-ranges:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> +additionalProperties:
> + anyOf:
> + - type: object
> + allOf:
> + - $ref: pincfg-node.yaml#
> + - $ref: pinmux-node.yaml#
> +
> + description:
> + Pin controller client devices use pin configuration subnodes (children
> + and grandchildren) for desired pin configuration.
> + Client device subnodes use below standard properties.
> +
> + properties:
> + phandle: true
> + function: true
> + groups: true
RZ/G2L uses per-pin configuration, and, unlike R-Car, the configuration
registers do not have the concept of pin groups. Hence I'm wondering
why you are using "function" and "group" properties, and not per-pin
"pinmux" properties, like RZ/A2?
> + pins: true
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> + drive-strength:
> + enum: [ 2, 4, 8, 12 ]
> + power-source:
> + enum: [ 1800, 2500, 3300 ]
> + slew-rate: true
> + gpio-hog: true
> + gpios: true
> + input-enable: true
> + output-high: true
> + output-low: true
> + line-name: true
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pinctrl-rzg2l.h
include/dt-bindings/pinctrl/rzg2l-pinctrl.h, for consistency?
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * This header provides constants for Renesas RZ/G2{L,LC} pinctrl bindings.
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_RZG2L_H
> +#define __DT_BINDINGS_PINCTRL_RZG2L_H
__DT_BINDINGS_RZG2L_PINCTRL_H
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
On Wed, Jun 16, 2021 at 3:27 PM Lad Prabhakar
<[email protected]> wrote:
> Add pins/groups/functions for I2C, SCIF and USB supported by RZ/G2L SoC and
> bind it with RZ/G2L PFC core.
>
> Based on a patch in the BSP by Hien Huynh <[email protected]>.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/pinctrl/renesas/pfc-r9a07g044.c
> @@ -0,0 +1,362 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * R9A07G044 processor support - pinctrl GPIO hardware block.
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + */
> +
> +#include "pinctrl-rzg2l.h"
> +
> +#define RZG2L_GPIO_PIN_CONF (0)
> +
> +static const struct {
> + struct pinctrl_pin_desc pin_gpio[392];
> +} pinmux_pins = {
> + .pin_gpio = {
> + RZ_G2L_PINCTRL_PIN_GPIO(0, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(1, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(2, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(3, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(4, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(5, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(6, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(7, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(8, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(9, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(10, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(11, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(12, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(13, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(14, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(15, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(16, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(17, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(18, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(19, RZG2L_GPIO_PIN_CONF),
RZG2L_GPIO_PIN_CONF is 0, ike all of the below?
> + RZ_G2L_PINCTRL_PIN_GPIO(20, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(21, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(22, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(23, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(24, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(25, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(26, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(27, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(28, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(29, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(30, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(31, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(32, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(33, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(34, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(35, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(36, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(37, 0),
> + RZ_G2L_PINCTRL_PIN_GPIO(38, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(39, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(40, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(41, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(42, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(43, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(44, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(45, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(46, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(47, RZG2L_GPIO_PIN_CONF),
> + RZ_G2L_PINCTRL_PIN_GPIO(48, RZG2L_GPIO_PIN_CONF),
> + },
> +};
Doesn't the above belong in pinctrl-rzg2l.c?
> +
> +/* - RIIC2 ------------------------------------------------------------------ */
> +static int i2c2_a_pins[] = {
> + /* SDA, SCL */
> + RZ_G2L_PIN(3, 0), RZ_G2L_PIN(3, 1),
> +};
> +static int i2c2_b_pins[] = {
> + /* SDA, SCL */
> + RZ_G2L_PIN(19, 0), RZ_G2L_PIN(19, 1),
> +};
> +static int i2c2_c_pins[] = {
> + /* SDA, SCL */
> + RZ_G2L_PIN(42, 3), RZ_G2L_PIN(42, 4),
> +};
> +static int i2c2_d_pins[] = {
> + /* SDA, SCL */
> + RZ_G2L_PIN(46, 0), RZ_G2L_PIN(46, 1),
> +};
> +static int i2c2_e_pins[] = {
> + /* SDA, SCL */
> + RZ_G2L_PIN(48, 0), RZ_G2L_PIN(48, 1),
> +};
[...]
> +static struct group_desc pinmux_groups[] = {
> + RZ_G2L_PINCTRL_PIN_GROUP(i2c2_a, 2),
> + RZ_G2L_PINCTRL_PIN_GROUP(i2c2_b, 4),
> + RZ_G2L_PINCTRL_PIN_GROUP(i2c2_c, 1),
> + RZ_G2L_PINCTRL_PIN_GROUP(i2c2_d, 4),
> + RZ_G2L_PINCTRL_PIN_GROUP(i2c2_e, 3),
[...]
As RZ/G2L, unlike R-Car, does not have the concept of pin groups, I'm
wondering why you are defining these groups? The pin function list
spreadsheet also doesn't have the "a" to "e" names of the possible
alternatives.
While I agree it makes it a little bit easier to describe in DT the
use of a group with lots of pins, it does prevent other use cases.
As register configuration is per-pin, I believe the hardware supports
the use of pins from multiple groups (e.g. SDA from the first group,
and SCL from the second group), and thus the board designer may decide
to make use of that.
With pinmux_pins[] moved, and the groups removed, this file becomes
empty?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds