From: Gabriel Fernandez <[email protected]>
Platform STM32MP1 can be used in configuration where some clocks and
IP resets can relate as secure resources.
These resources are moved from a RCC clock/reset handle to a SCMI
clock/reset_domain handle.
The RCC clock driver is now dependent of the SCMI driver, then we have
to manage now the probe defering.
v2 -> v3:
- use determine_rate op instead of round_rate for ck_rtc
- remove DT patches from patchset to keek Kernel device tree as there are in basic boot.
We will applied scmi clock phandle thanks dtbo in U-boot.
v1 -> v2:
- fix yamllint warnings.
Gabriel Fernandez (11):
clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock
clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
clk: stm32mp1: remove intermediate pll clocks
clk: stm32mp1: convert to module driver
clk: stm32mp1: move RCC reset controller into RCC clock driver
reset: stm32mp1: remove stm32mp1 reset
dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on
stm32mp15
dt-bindings: clock: stm32mp1 new compatible for secure rcc
clk: stm32mp1: new compatible for secure RCC support
.../bindings/clock/st,stm32mp1-rcc.yaml | 6 +-
drivers/clk/Kconfig | 10 +
drivers/clk/clk-stm32mp1.c | 500 +++++++++++++++---
drivers/reset/Kconfig | 6 -
drivers/reset/Makefile | 1 -
drivers/reset/reset-stm32mp1.c | 115 ----
include/dt-bindings/clock/stm32mp1-clks.h | 27 +
include/dt-bindings/reset/stm32mp1-resets.h | 15 +
8 files changed, 469 insertions(+), 211 deletions(-)
delete mode 100644 drivers/reset/reset-stm32mp1.c
--
2.17.1
From: Gabriel Fernandez <[email protected]>
Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource.
Signed-off-by: Arnaud Pouliquen <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
include/dt-bindings/reset/stm32mp1-resets.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
index bc71924faa54..f3a0ed317835 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -7,6 +7,7 @@
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
#define _DT_BINDINGS_STM32MP1_RESET_H_
+#define MCU_HOLD_BOOT_R 2144
#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
@@ -117,5 +118,6 @@
#define RST_SCMI0_RNG1 8
#define RST_SCMI0_MDMA 9
#define RST_SCMI0_MCU 10
+#define RST_SCMI0_MCU_HOLD_BOOT 11
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
--
2.17.1
From: Gabriel Fernandez <[email protected]>
st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/reset/Kconfig | 6 --
drivers/reset/Makefile | 1 -
drivers/reset/reset-stm32mp1.c | 115 ---------------------------------
3 files changed, 122 deletions(-)
delete mode 100644 drivers/reset/reset-stm32mp1.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 3e7f55e44d84..29fb33c0e26d 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -199,12 +199,6 @@ config RESET_SIMPLE
- ZTE's zx2967 family
- SiFive FU740 SoCs
-config RESET_STM32MP157
- bool "STM32MP157 Reset Driver" if COMPILE_TEST
- default MACH_STM32MP157
- help
- This enables the RCC reset controller driver for STM32 MPUs.
-
config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
default ARM && ARCH_INTEL_SOCFPGA
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 65a118a91b27..ac3e612ad953 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
-obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
deleted file mode 100644
index b221a28041fa..000000000000
--- a/drivers/reset/reset-stm32mp1.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
- * Author: Gabriel Fernandez <[email protected]> for STMicroelectronics.
- */
-
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/reset-controller.h>
-
-#define CLR_OFFSET 0x4
-
-struct stm32_reset_data {
- struct reset_controller_dev rcdev;
- void __iomem *membase;
-};
-
-static inline struct stm32_reset_data *
-to_stm32_reset_data(struct reset_controller_dev *rcdev)
-{
- return container_of(rcdev, struct stm32_reset_data, rcdev);
-}
-
-static int stm32_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
-{
- struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
- int reg_width = sizeof(u32);
- int bank = id / (reg_width * BITS_PER_BYTE);
- int offset = id % (reg_width * BITS_PER_BYTE);
- void __iomem *addr;
-
- addr = data->membase + (bank * reg_width);
- if (!assert)
- addr += CLR_OFFSET;
-
- writel(BIT(offset), addr);
-
- return 0;
-}
-
-static int stm32_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- return stm32_reset_update(rcdev, id, true);
-}
-
-static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- return stm32_reset_update(rcdev, id, false);
-}
-
-static int stm32_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
- int reg_width = sizeof(u32);
- int bank = id / (reg_width * BITS_PER_BYTE);
- int offset = id % (reg_width * BITS_PER_BYTE);
- u32 reg;
-
- reg = readl(data->membase + (bank * reg_width));
-
- return !!(reg & BIT(offset));
-}
-
-static const struct reset_control_ops stm32_reset_ops = {
- .assert = stm32_reset_assert,
- .deassert = stm32_reset_deassert,
- .status = stm32_reset_status,
-};
-
-static const struct of_device_id stm32_reset_dt_ids[] = {
- { .compatible = "st,stm32mp1-rcc"},
- { /* sentinel */ },
-};
-
-static int stm32_reset_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct stm32_reset_data *data;
- void __iomem *membase;
- struct resource *res;
-
- data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- membase = devm_ioremap_resource(dev, res);
- if (IS_ERR(membase))
- return PTR_ERR(membase);
-
- data->membase = membase;
- data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
- data->rcdev.ops = &stm32_reset_ops;
- data->rcdev.of_node = dev->of_node;
-
- return devm_reset_controller_register(dev, &data->rcdev);
-}
-
-static struct platform_driver stm32_reset_driver = {
- .probe = stm32_reset_probe,
- .driver = {
- .name = "stm32mp1-reset",
- .of_match_table = stm32_reset_dt_ids,
- },
-};
-
-builtin_platform_driver(stm32_reset_driver);
--
2.17.1
From: Gabriel Fernandez <[email protected]>
This patch is to prepare STM32MP1 clocks in trusted mode.
Integrate the mux clock into pll clock will facilitate to have a more
coherent clock tree in no trusted / trusted mode.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 65 ++++++++++++++++++++++++--------------
1 file changed, 42 insertions(+), 23 deletions(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index a7c244fd0b03..24d99da07fc8 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -731,6 +731,7 @@ struct stm32_pll_obj {
spinlock_t *lock;
void __iomem *reg;
struct clk_hw hw;
+ struct clk_mux mux;
};
#define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
@@ -745,6 +746,8 @@ struct stm32_pll_obj {
#define FRAC_MASK 0x1FFF
#define FRAC_SHIFT 3
#define FRACLE BIT(16)
+#define PLL_MUX_SHIFT 0
+#define PLL_MUX_MASK 3
static int __pll_is_enabled(struct clk_hw *hw)
{
@@ -856,16 +859,29 @@ static int pll_is_enabled(struct clk_hw *hw)
return ret;
}
+static u8 pll_get_parent(struct clk_hw *hw)
+{
+ struct stm32_pll_obj *clk_elem = to_pll(hw);
+ struct clk_hw *mux_hw = &clk_elem->mux.hw;
+
+ __clk_hw_set_clk(mux_hw, hw);
+
+ return clk_mux_ops.get_parent(mux_hw);
+}
+
static const struct clk_ops pll_ops = {
.enable = pll_enable,
.disable = pll_disable,
.recalc_rate = pll_recalc_rate,
.is_enabled = pll_is_enabled,
+ .get_parent = pll_get_parent,
};
static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
- const char *parent_name,
+ const char * const *parent_names,
+ int num_parents,
void __iomem *reg,
+ void __iomem *mux_reg,
unsigned long flags,
spinlock_t *lock)
{
@@ -881,8 +897,15 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
init.name = name;
init.ops = &pll_ops;
init.flags = flags;
- init.parent_names = &parent_name;
- init.num_parents = 1;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ element->mux.lock = lock;
+ element->mux.reg = mux_reg;
+ element->mux.shift = PLL_MUX_SHIFT;
+ element->mux.mask = PLL_MUX_MASK;
+ element->mux.flags = CLK_MUX_READ_ONLY;
+ element->mux.reg = mux_reg;
element->hw.init = &init;
element->reg = reg;
@@ -1074,6 +1097,7 @@ static const struct clk_ops rtc_div_clk_ops = {
struct stm32_pll_cfg {
u32 offset;
+ u32 muxoff;
};
static struct clk_hw *_clk_register_pll(struct device *dev,
@@ -1083,8 +1107,11 @@ static struct clk_hw *_clk_register_pll(struct device *dev,
{
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
- return clk_register_pll(dev, cfg->name, cfg->parent_name,
- base + stm_pll_cfg->offset, cfg->flags, lock);
+ return clk_register_pll(dev, cfg->name, cfg->parent_names,
+ cfg->num_parents,
+ base + stm_pll_cfg->offset,
+ base + stm_pll_cfg->muxoff,
+ cfg->flags, lock);
}
struct stm32_cktim_cfg {
@@ -1194,14 +1221,16 @@ _clk_stm32_register_composite(struct device *dev,
.func = _clk_hw_register_mux,\
}
-#define PLL(_id, _name, _parent, _flags, _offset)\
+#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
{\
.id = _id,\
.name = _name,\
- .parent_name = _parent,\
- .flags = _flags,\
+ .parent_names = _parents,\
+ .num_parents = ARRAY_SIZE(_parents),\
+ .flags = CLK_IGNORE_UNUSED | (_flags),\
.cfg = &(struct stm32_pll_cfg) {\
- .offset = _offset,\
+ .offset = _offset_p,\
+ .muxoff = _offset_mux,\
},\
.func = _clk_register_pll,\
}
@@ -1717,21 +1746,11 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
- /* ref clock pll */
- MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
- 0, 2, CLK_MUX_READ_ONLY),
-
- MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
- 0, 2, CLK_MUX_READ_ONLY),
-
- MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
- 0, 2, CLK_MUX_READ_ONLY),
-
/* PLLs */
- PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
- PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
- PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
- PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
+ PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
+ PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
+ PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
+ PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
/* ODF */
COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
--
2.17.1
From: Gabriel Fernandez <[email protected]>
This patch is to prepare STM32MP1 clocks in trusted mode.
This Merge will facilitate to have a more coherent clock tree
in no trusted / trusted world.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index a875649df8b8..35d5aee8f9b0 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1657,16 +1657,16 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
};
static const struct clock_config stm32mp1_clock_cfg[] = {
- /* Oscillator divider */
- DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
- RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
-
/* External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
/* ck_csi is used by IO compensation and should be critical */
GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
RCC_OCENSETR, 4, 0),
- GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
+ COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
+ _GATE_MP1(RCC_OCENSETR, 0, 0),
+ _NO_MUX,
+ _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
+ CLK_DIVIDER_READ_ONLY, NULL)),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
--
2.17.1
From: Gabriel Fernandez <[email protected]>
stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
PLL output and few secure aware interfaces.
This change defines the SCMI clock identifiers used by SCMI agents
and servers.
Server SCMI0 exposes clocks and reset controllers for resources under
RCC[TZEN] configuration control.
Server SCMI1 exposes clocks for resources under RCC[MCKPROT] control.
Signed-off-by: Etienne Carriere <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
include/dt-bindings/clock/stm32mp1-clks.h | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
index 4cdaf135829c..e02770b98e6c 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,4 +248,31 @@
#define STM32MP1_LAST_CLK 232
+/* SCMI clock identifiers */
+#define CK_SCMI0_HSE 0
+#define CK_SCMI0_HSI 1
+#define CK_SCMI0_CSI 2
+#define CK_SCMI0_LSE 3
+#define CK_SCMI0_LSI 4
+#define CK_SCMI0_PLL2_Q 5
+#define CK_SCMI0_PLL2_R 6
+#define CK_SCMI0_MPU 7
+#define CK_SCMI0_AXI 8
+#define CK_SCMI0_BSEC 9
+#define CK_SCMI0_CRYP1 10
+#define CK_SCMI0_GPIOZ 11
+#define CK_SCMI0_HASH1 12
+#define CK_SCMI0_I2C4 13
+#define CK_SCMI0_I2C6 14
+#define CK_SCMI0_IWDG1 15
+#define CK_SCMI0_RNG1 16
+#define CK_SCMI0_RTC 17
+#define CK_SCMI0_RTCAPB 18
+#define CK_SCMI0_SPI6 19
+#define CK_SCMI0_USART1 20
+
+#define CK_SCMI1_PLL3_Q 0
+#define CK_SCMI1_PLL3_R 1
+#define CK_SCMI1_MCU 2
+
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
--
2.17.1
From: Gabriel Fernandez <[email protected]>
Introduce new compatible string "st,stm32mp1-rcc-secure" for
stm32mp1 clock driver when the device is configured with RCC
security support hardened.
Signed-off-by: Etienne Carriere <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
index 4e385508f516..8b1ecb2ecdd5 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
@@ -54,7 +54,9 @@ properties:
compatible:
items:
- - const: st,stm32mp1-rcc
+ - enum:
+ - st,stm32mp1-rcc-secure
+ - st,stm32mp1-rcc
- const: syscon
reg:
@@ -71,7 +73,7 @@ additionalProperties: false
examples:
- |
rcc: rcc@50000000 {
- compatible = "st,stm32mp1-rcc", "syscon";
+ compatible = "st,stm32mp1-rcc-secure", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.17.1
From: Gabriel Fernandez <[email protected]>
Platform STM32MP1 can be used in configuration where some clock
resources cannot be accessed by Linux kernel when executing in non-secure
state of the CPU(s).
In such configuration, the RCC clock driver must not register clocks
it cannot access.
They are expected to be registered from another clock driver such
as the SCMI clock driver.
This change uses specific compatible string "st,stm32mp1-rcc-secure"
to specify RCC clock driver configuration where RCC is secure.
Signed-off-by: Etienne Carriere <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/Kconfig | 10 ++++
drivers/clk/clk-stm32mp1.c | 101 ++++++++++++++++++++++++++++++++++++-
2 files changed, 110 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index e80918be8e9c..e367a033e121 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -335,6 +335,16 @@ config COMMON_CLK_STM32MP157
help
Support for stm32mp157 SoC family clocks
+config COMMON_CLK_STM32MP157_SCMI
+ bool "stm32mp157 Clock driver with Trusted Firmware"
+ depends on COMMON_CLK_STM32MP157
+ select COMMON_CLK_SCMI
+ select ARM_SCMI_PROTOCOL
+ default y
+ help
+ Support for stm32mp157 SoC family clocks with Trusted Firmware using
+ SCMI protocol.
+
config COMMON_CLK_STM32F
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
help
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6d3a36f81b2d..6adc625e79cb 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -2056,11 +2056,61 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
};
+static const u32 stm32mp1_clock_secured[] = {
+ CK_HSE,
+ CK_HSI,
+ CK_CSI,
+ CK_LSI,
+ CK_LSE,
+ PLL1,
+ PLL2,
+ PLL1_P,
+ PLL2_P,
+ PLL2_Q,
+ PLL2_R,
+ CK_MPU,
+ CK_AXI,
+ SPI6,
+ I2C4,
+ I2C6,
+ USART1,
+ RTCAPB,
+ TZC1,
+ TZC2,
+ TZPC,
+ IWDG1,
+ BSEC,
+ STGEN,
+ GPIOZ,
+ CRYP1,
+ HASH1,
+ RNG1,
+ BKPSRAM,
+ RNG1_K,
+ STGEN_K,
+ SPI6_K,
+ I2C4_K,
+ I2C6_K,
+ USART1_K,
+ RTC,
+};
+
+static bool stm32_check_security(const struct clock_config *cfg)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
+ if (cfg->id == stm32mp1_clock_secured[i])
+ return true;
+ return false;
+}
+
struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
u32 clear_offset;
+ bool (*check_security)(const struct clock_config *cfg);
};
static struct stm32_rcc_match_data stm32mp1_data = {
@@ -2070,11 +2120,23 @@ static struct stm32_rcc_match_data stm32mp1_data = {
.clear_offset = RCC_CLR,
};
+static struct stm32_rcc_match_data stm32mp1_data_secure = {
+ .cfg = stm32mp1_clock_cfg,
+ .num = ARRAY_SIZE(stm32mp1_clock_cfg),
+ .maxbinding = STM32MP1_LAST_CLK,
+ .clear_offset = RCC_CLR,
+ .check_security = &stm32_check_security
+};
+
static const struct of_device_id stm32mp1_match_data[] = {
{
.compatible = "st,stm32mp1-rcc",
.data = &stm32mp1_data,
},
+ {
+ .compatible = "st,stm32mp1-rcc-secure",
+ .data = &stm32mp1_data_secure,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
@@ -2234,6 +2296,9 @@ static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,
hws[n] = ERR_PTR(-ENOENT);
for (n = 0; n < data->num; n++) {
+ if (data->check_security && data->check_security(&data->cfg[n]))
+ continue;
+
err = stm32_register_hw_clk(dev, clk_data, base, &rlock,
&data->cfg[n]);
if (err) {
@@ -2301,11 +2366,45 @@ static int stm32mp1_rcc_init(struct device *dev)
return ret;
}
+static int get_clock_deps(struct device *dev)
+{
+ static const char * const clock_deps_name[] = {
+ "hsi", "hse", "csi", "lsi", "lse",
+ };
+ size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
+ struct clk **clk_deps;
+ int i;
+
+ clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
+ if (!clk_deps)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
+ struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
+ clock_deps_name[i]);
+
+ if (IS_ERR(clk)) {
+ if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
+ return PTR_ERR(clk);
+ } else {
+ /* Device gets a reference count on the clock */
+ clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
+ clk_put(clk);
+ }
+ }
+
+ return 0;
+}
+
static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ int ret = get_clock_deps(dev);
+
+ if (!ret)
+ ret = stm32mp1_rcc_init(dev);
- return stm32mp1_rcc_init(dev);
+ return ret;
}
static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
--
2.17.1
From: Gabriel Fernandez <[email protected]>
stm32mp15 TZ secure firmware provides SCMI reset domains for
secure resources. This change defines the SCMI reset domain
identifiers used by SCMI agents and servers.
Stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
PLL output and few secure aware interfaces. This change defines the
SCMI clock identifiers used by SCMI agents and servers.
Server SCMI0 exposes reset controllers for resources under RCC[TZEN]
configuration control.
Signed-off-by: Etienne Carriere <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
include/dt-bindings/reset/stm32mp1-resets.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
index f0c3aaef67a0..bc71924faa54 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -105,4 +105,17 @@
#define GPIOJ_R 19785
#define GPIOK_R 19786
+/* SCMI reset domain identifiers */
+#define RST_SCMI0_SPI6 0
+#define RST_SCMI0_I2C4 1
+#define RST_SCMI0_I2C6 2
+#define RST_SCMI0_USART1 3
+#define RST_SCMI0_STGEN 4
+#define RST_SCMI0_GPIOZ 5
+#define RST_SCMI0_CRYP1 6
+#define RST_SCMI0_HASH1 7
+#define RST_SCMI0_RNG1 8
+#define RST_SCMI0_MDMA 9
+#define RST_SCMI0_MCU 10
+
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
--
2.17.1
On 6/17/21 7:18 AM, [email protected] wrote:
> From: Gabriel Fernandez <[email protected]>
>
> Platform STM32MP1 can be used in configuration where some clock
> resources cannot be accessed by Linux kernel when executing in non-secure
> state of the CPU(s).
> In such configuration, the RCC clock driver must not register clocks
> it cannot access.
> They are expected to be registered from another clock driver such
> as the SCMI clock driver.
> This change uses specific compatible string "st,stm32mp1-rcc-secure"
> to specify RCC clock driver configuration where RCC is secure.
Should this really be a new compatible string or rather a DT property ?
I think the later, since this is the same clock IP, only operating in
different "mode" , no ?
Yes we could have considered it as a feature but we think it's better to
manage it as a layer of our driver via a compatible.
On 6/17/21 8:46 AM, Marek Vasut wrote:
> On 6/17/21 7:18 AM, [email protected] wrote:
>> From: Gabriel Fernandez <[email protected]>
>>
>> Platform STM32MP1 can be used in configuration where some clock
>> resources cannot be accessed by Linux kernel when executing in non-secure
>> state of the CPU(s).
>> In such configuration, the RCC clock driver must not register clocks
>> it cannot access.
>> They are expected to be registered from another clock driver such
>> as the SCMI clock driver.
>> This change uses specific compatible string "st,stm32mp1-rcc-secure"
>> to specify RCC clock driver configuration where RCC is secure.
>
> Should this really be a new compatible string or rather a DT property ?
> I think the later, since this is the same clock IP, only operating in
> different "mode" , no ?
Quoting [email protected] (2021-06-16 22:18:04)
> From: Gabriel Fernandez <[email protected]>
>
> This patch is to prepare STM32MP1 clocks in trusted mode.
> This Merge will facilitate to have a more coherent clock tree
> in no trusted / trusted world.
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-next
Quoting [email protected] (2021-06-16 22:18:06)
> From: Gabriel Fernandez <[email protected]>
>
> This patch is to prepare STM32MP1 clocks in trusted mode.
> Integrate the mux clock into pll clock will facilitate to have a more
> coherent clock tree in no trusted / trusted mode.
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-next
Quoting [email protected] (2021-06-16 22:18:09)
> From: Gabriel Fernandez <[email protected]>
>
> st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-next although it would be nice to get Philipp's ack
Quoting [email protected] (2021-06-16 22:18:10)
> From: Gabriel Fernandez <[email protected]>
>
> stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
> PLL output and few secure aware interfaces.
> This change defines the SCMI clock identifiers used by SCMI agents
> and servers.
> Server SCMI0 exposes clocks and reset controllers for resources under
> RCC[TZEN] configuration control.
> Server SCMI1 exposes clocks for resources under RCC[MCKPROT] control.
>
> Signed-off-by: Etienne Carriere <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
Applied to clk-next
Quoting [email protected] (2021-06-16 22:18:11)
> From: Gabriel Fernandez <[email protected]>
>
> stm32mp15 TZ secure firmware provides SCMI reset domains for
> secure resources. This change defines the SCMI reset domain
> identifiers used by SCMI agents and servers.
>
> Stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some
> PLL output and few secure aware interfaces. This change defines the
> SCMI clock identifiers used by SCMI agents and servers.
>
> Server SCMI0 exposes reset controllers for resources under RCC[TZEN]
> configuration control.
>
> Signed-off-by: Etienne Carriere <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
Applied to clk-next
Quoting [email protected] (2021-06-16 22:18:13)
> From: Gabriel Fernandez <[email protected]>
>
> Introduce new compatible string "st,stm32mp1-rcc-secure" for
> stm32mp1 clock driver when the device is configured with RCC
> security support hardened.
>
> Signed-off-by: Etienne Carriere <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
Applied to clk-next
Quoting [email protected] (2021-06-16 22:18:14)
> From: Gabriel Fernandez <[email protected]>
>
> Platform STM32MP1 can be used in configuration where some clock
> resources cannot be accessed by Linux kernel when executing in non-secure
> state of the CPU(s).
> In such configuration, the RCC clock driver must not register clocks
> it cannot access.
> They are expected to be registered from another clock driver such
> as the SCMI clock driver.
> This change uses specific compatible string "st,stm32mp1-rcc-secure"
> to specify RCC clock driver configuration where RCC is secure.
>
> Signed-off-by: Etienne Carriere <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-next
Quoting [email protected] (2021-06-16 22:18:12)
> From: Gabriel Fernandez <[email protected]>
>
> Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource.
>
> Signed-off-by: Arnaud Pouliquen <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
Applied to clk-next
On Sun, 2021-06-27 at 18:35 -0700, Stephen Boyd wrote:
> Quoting [email protected] (2021-06-16 22:18:09)
> > From: Gabriel Fernandez <[email protected]>
> >
> > st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.
> >
> > Signed-off-by: Gabriel Fernandez <[email protected]>
> > ---
>
> Applied to clk-next although it would be nice to get Philipp's ack
Acked-by: Philipp Zabel <[email protected]>
regards
Philipp
Sure, many thanks Stephen.
Best regards
Gabriel
On 6/28/21 3:35 AM, Stephen Boyd wrote:
> Quoting [email protected] (2021-06-16 22:18:09)
>> From: Gabriel Fernandez <[email protected]>
>>
>> st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.
>>
>> Signed-off-by: Gabriel Fernandez <[email protected]>
>> ---
>
> Applied to clk-next although it would be nice to get Philipp's ack
>