Changes in v5:
- Fixed contamination from patch 2/3 in patch 1/3
- Fixed missing bits in cpuidle-qcom-spm (thanks Stephan)
Changes in v4:
- Huge patch series has been split for better reviewability,
as suggested by Bjorn
Changes in v3:
- Rebased (no changes - was in previous series' v3)
Changes in v2:
- Fixed MSM8998 SAW parameters on SPM driver
Tested on the following smartphones:
- Sony Xperia XA2 (SDM630)
- Sony Xperia XA2 Ultra (SDM630)
- Sony Xperia 10 (SDM630)
- Sony Xperia XZ Premium (MSM8998)
- F(x)Tec Pro 1 (MSM8998)
This is a component that we can find on very old
chips, like MSM8974; there, it has been used to actually do the
power scaling basically "on its own" - sending the cores in a specific
sleep mode to save power.
On the newer ones, including MSM8998, SDM630, 660 and others, it is still
present! Though, this time, it's being used for the cluster caches and it
has a different firmware (and maybe it's also slightly different HW),
implementing the SAWv4.1 set and getting controlled *not by the OS* but
by other controllers in the SoC (like the OSM).
Contrary from MSM8974 and the like, this new version of the SPM just
requires us to set the initial parameters for AVS and *nothing else*, as
its states will be totally managed internally.
AngeloGioacchino Del Regno (3):
cpuidle: qcom_spm: Detach state machine from main SPM handling
soc: qcom: spm: Implement support for SAWv4.1, SDM630/660 L2 AVS
soc: qcom: spm: Add compatible for MSM8998 SAWv4.1 L2
drivers/cpuidle/Kconfig.arm | 1 +
drivers/cpuidle/cpuidle-qcom-spm.c | 295 ++++++-----------------------
drivers/soc/qcom/Kconfig | 9 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/spm.c | 240 +++++++++++++++++++++++
include/soc/qcom/spm.h | 45 +++++
6 files changed, 355 insertions(+), 236 deletions(-)
create mode 100644 drivers/soc/qcom/spm.c
create mode 100644 include/soc/qcom/spm.h
--
2.32.0
Implement the support for SAW v4.1, used in at least MSM8998,
SDM630, SDM660 and APQ variants and, while at it, also add the
configuration for the SDM630/660 Silver and Gold cluster L2
Adaptive Voltage Scaler: this is also one of the prerequisites
to allow the OSM controller to perform DCVS.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/soc/qcom/spm.c | 28 +++++++++++++++++++++++++++-
include/soc/qcom/spm.h | 4 +++-
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 0c8aa9240c41..843732d12c54 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -32,9 +32,28 @@ enum spm_reg {
SPM_REG_SEQ_ENTRY,
SPM_REG_SPM_STS,
SPM_REG_PMIC_STS,
+ SPM_REG_AVS_CTL,
+ SPM_REG_AVS_LIMIT,
SPM_REG_NR,
};
+static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = {
+ [SPM_REG_AVS_CTL] = 0x904,
+ [SPM_REG_AVS_LIMIT] = 0x908,
+};
+
+static const struct spm_reg_data spm_reg_660_gold_l2 = {
+ .reg_offset = spm_reg_offset_v4_1,
+ .avs_ctl = 0x1010031,
+ .avs_limit = 0x4580458,
+};
+
+static const struct spm_reg_data spm_reg_660_silver_l2 = {
+ .reg_offset = spm_reg_offset_v4_1,
+ .avs_ctl = 0x101c031,
+ .avs_limit = 0x4580458,
+};
+
static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
[SPM_REG_CFG] = 0x08,
[SPM_REG_SPM_CTL] = 0x30,
@@ -126,6 +145,10 @@ void spm_set_low_power_mode(struct spm_driver_data *drv,
}
static const struct of_device_id spm_match_table[] = {
+ { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
+ .data = &spm_reg_660_gold_l2 },
+ { .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
+ .data = &spm_reg_660_silver_l2 },
{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
.data = &spm_reg_8974_8084_cpu },
{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
@@ -169,6 +192,8 @@ static int spm_dev_probe(struct platform_device *pdev)
* CPU was held in reset, the reset signal could trigger the SPM state
* machine, before the sequences are completely written.
*/
+ spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl);
+ spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit);
spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
@@ -178,7 +203,8 @@ static int spm_dev_probe(struct platform_device *pdev)
drv->reg_data->pmic_data[1]);
/* Set up Standby as the default low power mode */
- spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
+ if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
+ spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
return 0;
}
diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
index 719c604a8402..5ab40488a9f4 100644
--- a/include/soc/qcom/spm.h
+++ b/include/soc/qcom/spm.h
@@ -22,11 +22,13 @@ enum pm_sleep_mode {
};
struct spm_reg_data {
- const u8 *reg_offset;
+ const u16 *reg_offset;
u32 spm_cfg;
u32 spm_dly;
u32 pmic_dly;
u32 pmic_data[MAX_PMIC_DATA];
+ u32 avs_ctl;
+ u32 avs_limit;
u8 seq[MAX_SEQ_DATA];
u8 start_index[PM_SLEEP_MODE_NR];
};
--
2.32.0
Add the SAWv4.1 parameters for MSM8998's Gold and Silver clusters.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/soc/qcom/spm.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 843732d12c54..2e6312663293 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -54,6 +54,18 @@ static const struct spm_reg_data spm_reg_660_silver_l2 = {
.avs_limit = 0x4580458,
};
+static const struct spm_reg_data spm_reg_8998_gold_l2 = {
+ .reg_offset = spm_reg_offset_v4_1,
+ .avs_ctl = 0x1010031,
+ .avs_limit = 0x4700470,
+};
+
+static const struct spm_reg_data spm_reg_8998_silver_l2 = {
+ .reg_offset = spm_reg_offset_v4_1,
+ .avs_ctl = 0x1010031,
+ .avs_limit = 0x4200420,
+};
+
static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
[SPM_REG_CFG] = 0x08,
[SPM_REG_SPM_CTL] = 0x30,
@@ -149,6 +161,10 @@ static const struct of_device_id spm_match_table[] = {
.data = &spm_reg_660_gold_l2 },
{ .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
.data = &spm_reg_660_silver_l2 },
+ { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
+ .data = &spm_reg_8998_gold_l2 },
+ { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
+ .data = &spm_reg_8998_silver_l2 },
{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
.data = &spm_reg_8974_8084_cpu },
{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
--
2.32.0
On Sat, Jun 19, 2021 at 12:56:19AM +0200, AngeloGioacchino Del Regno wrote:
> Implement the support for SAW v4.1, used in at least MSM8998,
> SDM630, SDM660 and APQ variants and, while at it, also add the
> configuration for the SDM630/660 Silver and Gold cluster L2
> Adaptive Voltage Scaler: this is also one of the prerequisites
> to allow the OSM controller to perform DCVS.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> drivers/soc/qcom/spm.c | 28 +++++++++++++++++++++++++++-
> include/soc/qcom/spm.h | 4 +++-
> 2 files changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
> [...]
> static const struct of_device_id spm_match_table[] = {
> + { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
> + .data = &spm_reg_660_gold_l2 },
> + { .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
> + .data = &spm_reg_660_silver_l2 },
I think we need some dt-bindings patches for these? :)
Also, like I mentioned on v4 I still think a short comment in commit
message or file with the reason why you don't want the change qcom did
in [1] would be appropriate here. You can just use what you
already mentioned in your reply in v4 (the random lockups).
Because otherwise it's not obvious why someone else shouldn't "make this
consistent with qcom's values" sometime later and then suddenly you get
the random lockups again.
Thanks,
Stephan