2021-06-13 21:30:48

by Nobuhiro Iwamatsu

Subject: [PATCH] dt-bindings: fpga: zynq: convert bindings to YAML

Convert FPGA for Xilinx Zynq SoC bindings documentation to YAML.

Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
---
.../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 19 -------
.../bindings/fpga/xilinx-zynq-fpga-mgr.yaml | 52 +++++++++++++++++++
2 files changed, 52 insertions(+), 19 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml

diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
deleted file mode 100644
index 7018aa89683591..00000000000000
--- a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Xilinx Zynq FPGA Manager
-
-Required properties:
-- compatible: should contain "xlnx,zynq-devcfg-1.0"
-- reg: base address and size for memory mapped io
-- interrupts: interrupt for the FPGA manager device
-- clocks: phandle for clocks required operation
-- clock-names: name for the clock, should be "ref_clk"
-- syscon: phandle for access to SLCR registers
-
-Example:
- devcfg: devcfg@f8007000 {
- compatible = "xlnx,zynq-devcfg-1.0";
- reg = <0xf8007000 0x100>;
- interrupts = <0 8 4>;
- clocks = <&clkc 12>;
- clock-names = "ref_clk";
- syscon = <&slcr>;
- };
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
new file mode 100644
index 00000000000000..29daca4be47fcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq FPGA Manager Device Tree Bindings
+
+maintainers:
+ - Michal Simek <[email protected]>
+
+properties:
+ compatible:
+ const: xlnx,zynq-devcfg-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ref_clk
+
+ syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to syscon block which provide access to SLCR registers
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ devcfg: devcfg@f8007000 {
+ compatible = "xlnx,zynq-devcfg-1.0";
+ reg = <0xf8007000 0x100>;
+ interrupts = <0 8 4>;
+ clocks = <&clkc 12>;
+ clock-names = "ref_clk";
+ syscon = <&slcr>;
+ };
--
2.32.0

2021-06-24 20:28:00

by Rob Herring (Arm)

Subject: Re: [PATCH] dt-bindings: fpga: zynq: convert bindings to YAML

On Mon, 14 Jun 2021 06:28:56 +0900, Nobuhiro Iwamatsu wrote:
> Convert FPGA for Xilinx Zynq SoC bindings documentation to YAML.
>
> Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
> ---
> .../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 19 -------
> .../bindings/fpga/xilinx-zynq-fpga-mgr.yaml | 52 +++++++++++++++++++
> 2 files changed, 52 insertions(+), 19 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
> create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
>

Applied, thanks!