The first two patches in this series are small fixes before we can
actually make the video clock tree mutable. One patch adds
CLK_SET_RATE_NO_REPARENT for better rate control and the other adds
a missing clock gate.
The third and fourth patch are targeting the HDMI PLL. Add the known
working M/N combinations. Also this PLL has some special "doubling"
setting, which is calculated like this:
OUTPUT = (IN * M / N + FRAC) * 2
Since not all register bits are known we use a copy of the 2970/2975MHz
magic register values from the vendor driver.
The fifth patch makes the clocks in the video clock tree mutable. The
final patch in this series exports the clocks needed for rate control.
For reference, this is the .dts definition for the Meson8b VPU. The
code for the VPU driver is unfortunately not ready for upstreaming yet.
However, I have tested with all resolutions my monitor supports and the
clock settings are all applied correctly.
vpu: vpu@100000 {
compatible = "amlogic,meson8b-vpu";
reg = <0x100000 0x10000>;
reg-names = "vpu";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
amlogic,canvas = <&canvas>;
amlogic,hhi-sysctrl = <&hhi>;
/*
* The VCLK{,2}_IN path always needs to derived from
* the CLKID_VID_PLL_FINAL_DIV so other clocks like
* MPLL1 are not used (MPLL1 is reserved for audio
* purposes).
*/
assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>,
<&clkc CLKID_VCLK2_IN_SEL>;
assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>,
<&clkc CLKID_VID_PLL_FINAL_DIV>;
clocks = <&clkc CLKID_VPU_INTR>,
<&clkc CLKID_HDMI_INTR_SYNC>,
<&clkc CLKID_GCLK_VENCI_INT>,
<&clkc CLKID_HDMI_PLL_HDMI_OUT>,
<&clkc CLKID_HDMI_TX_PIXEL>,
<&clkc CLKID_CTS_ENCP>,
<&clkc CLKID_CTS_ENCI>,
<&clkc CLKID_CTS_ENCT>,
<&clkc CLKID_CTS_ENCL>,
<&clkc CLKID_CTS_VDAC0>;
clock-names = "vpu_intr",
"hdmi_intr_sync",
"venci_int",
"tmds",
"hdmi_tx_pixel",
"cts_encp",
"cts_enci",
"cts_enct",
"cts_encl",
"cts_vdac0";
resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>,
<&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>,
<&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>,
<&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>;
reset-names = "vid_pll_pre",
"vid_pll_post",
"vid_pll_soft_pre",
"vid_pll_soft_post";
power-domains = <&pwrc PWRC_MESON8_VPU_ID>;
nvmem-cells = <&cvbs_trimming>;
nvmem-cell-names = "cvbs_trimming";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <0>;
sound-name-prefix = "HDMITX";
/* CVBS VDAC output port */
cvbs_vdac_port: port@0 {
reg = <0>;
};
/* HDMI-TX output port */
hdmi_tx_port: port@1 {
reg = <1>;
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_tx_in>;
};
};
};
Martin Blumenstingl (6):
clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel
clk: meson: meson8b: Add the vid_pll_lvds_en gate clock
clk: meson: meson8b: Add the HDMI PLL M/N parameters
clk: meson: meson8b: Initialize the HDMI PLL registers
clk: meson: meson8b: Make the video clock trees mutable
clk: meson: meson8b: Export the video clocks
drivers/clk/meson/meson8b.c | 163 +++++++++++++++++------
drivers/clk/meson/meson8b.h | 26 ++--
include/dt-bindings/clock/meson8b-clkc.h | 10 ++
3 files changed, 143 insertions(+), 56 deletions(-)
--
2.32.0
Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only
parent which is actually used is vid_pll_final_div. This should be set
using assigned-clock-parents in the .dts rather than removing some
"unwanted" clock parents from the clock driver.
Suggested-by: Jerome Brunet <[email protected]>
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/meson8b.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index a844d35b553a..0f8bd707217a 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1175,7 +1175,7 @@ static struct clk_regmap meson8b_vclk_in_sel = {
.ops = &clk_regmap_mux_ro_ops,
.parent_hws = meson8b_vclk_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
},
};
@@ -1358,7 +1358,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
.ops = &clk_regmap_mux_ro_ops,
.parent_hws = meson8b_vclk_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
},
};
--
2.32.0
HHI_VID_DIVIDER_CNTL[11] must be enabled for the video clock tree to
work. This bit is described as "LVDS_CLK_EN". It is not 100% clear where
this bit has to be placed in the hierarchy. But since the "LVDS_OUT" of
the HDMI PLL uses it's own set of registers it's more likely that this
"LVDS_CLK_EN" bit actually enables the input of the "hdmi_pll_lvds_out"
clock to the "vid_pll_in_sel" tree.
Add a gate definition for this bit (which will not be exported) so that
the kernel can manage all required bits to enable and disable the video
clocks.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/meson8b.c | 23 ++++++++++++++++++++++-
drivers/clk/meson/meson8b.h | 3 ++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 0f8bd707217a..9ccffbfe44e5 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1045,6 +1045,23 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = {
},
};
+/* also called LVDS_CLK_EN */
+static struct clk_regmap meson8b_vid_pll_lvds_en = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_VID_DIVIDER_CNTL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "vid_pll_lvds_en",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &meson8b_hdmi_pll_lvds_out.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
static struct clk_regmap meson8b_vid_pll_in_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VID_DIVIDER_CNTL,
@@ -1061,7 +1078,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
* Meson8m2: vid2_pll
*/
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_hdmi_pll_lvds_out.hw
+ &meson8b_vid_pll_lvds_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2905,6 +2922,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -3122,6 +3140,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -3341,6 +3360,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -3539,6 +3559,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_cts_mclk_i958_div,
&meson8b_cts_mclk_i958,
&meson8b_cts_i958,
+ &meson8b_vid_pll_lvds_en,
};
static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index b1a5074cf148..954d97cf6c5a 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -182,8 +182,9 @@
#define CLKID_CTS_MCLK_I958_DIV 211
#define CLKID_VCLK_EN 214
#define CLKID_VCLK2_EN 215
+#define CLKID_VID_PLL_LVDS_EN 216
-#define CLK_NR_CLKS 216
+#define CLK_NR_CLKS 217
/*
* include the CLKID and RESETID that have
--
2.32.0
The 3.10 vendor kernel uses only specific HDMI PLL M/N parameter
combinations. The PLL won't lock for values smaller than 50 if the
internal doubling (which is yet unknown how to use it) is disabled.
However, when this doubling is enabled then the values smaller than 50
will lock just fine. The only restriction for values greater than 50 is
that the resulting frequency must not exceed the 3.0GHz limit.
These values are taken from the endlessm 3.10 kernel which includes
additional M/N combinations for some VESA and 75Hz display modes.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/meson8b.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 9ccffbfe44e5..8f29d26ed726 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -118,6 +118,27 @@ static struct clk_regmap meson8b_fixed_pll = {
},
};
+static const struct pll_params_table hdmi_pll_params_table[] = {
+ PLL_PARAMS(40, 1),
+ PLL_PARAMS(42, 1),
+ PLL_PARAMS(44, 1),
+ PLL_PARAMS(45, 1),
+ PLL_PARAMS(49, 1),
+ PLL_PARAMS(52, 1),
+ PLL_PARAMS(54, 1),
+ PLL_PARAMS(56, 1),
+ PLL_PARAMS(59, 1),
+ PLL_PARAMS(60, 1),
+ PLL_PARAMS(61, 1),
+ PLL_PARAMS(62, 1),
+ PLL_PARAMS(64, 1),
+ PLL_PARAMS(66, 1),
+ PLL_PARAMS(68, 1),
+ PLL_PARAMS(71, 1),
+ PLL_PARAMS(82, 1),
+ { /* sentinel */ }
+};
+
static struct clk_regmap meson8b_hdmi_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
@@ -150,6 +171,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
.shift = 29,
.width = 1,
},
+ .table = hdmi_pll_params_table,
},
.hw.init = &(struct clk_init_data){
/* sometimes also called "HPLL" or "HPLL PLL" */
--
2.32.0
Switch from the "_ro" clock op variants to the mutable ones for all
video clocks. This will allow the VPU driver to change the clocks as
needed for the different video output modes.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/meson8b.c | 76 ++++++++++++++++++-------------------
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 21bc29455f0d..cd0f5bae24d4 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -207,7 +207,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
.hw.init = &(struct clk_init_data){
/* sometimes also called "HPLL" or "HPLL PLL" */
.name = "hdmi_pll_dco",
- .ops = &meson_clk_pll_ro_ops,
+ .ops = &meson_clk_pll_ops,
.parent_hws = (const struct clk_hw *[]) {
&hdmi_pll_dco_in.hw
},
@@ -224,7 +224,7 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll_lvds_out",
- .ops = &clk_regmap_divider_ro_ops,
+ .ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_pll_dco.hw
},
@@ -242,7 +242,7 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll_hdmi_out",
- .ops = &clk_regmap_divider_ro_ops,
+ .ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_pll_dco.hw
},
@@ -1104,7 +1104,7 @@ static struct clk_regmap meson8b_vid_pll_lvds_en = {
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll_lvds_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_pll_lvds_out.hw
},
@@ -1121,7 +1121,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll_in_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
/*
* TODO: depending on the SoC there is also a second parent:
* Meson8: unknown
@@ -1143,7 +1143,7 @@ static struct clk_regmap meson8b_vid_pll_in_en = {
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll_in_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll_in_sel.hw
},
@@ -1160,7 +1160,7 @@ static struct clk_regmap meson8b_vid_pll_pre_div = {
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll_pre_div",
- .ops = &clk_regmap_divider_ro_ops,
+ .ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll_in_en.hw
},
@@ -1177,7 +1177,7 @@ static struct clk_regmap meson8b_vid_pll_post_div = {
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll_post_div",
- .ops = &clk_regmap_divider_ro_ops,
+ .ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll_pre_div.hw
},
@@ -1194,7 +1194,7 @@ static struct clk_regmap meson8b_vid_pll = {
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
/* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll_pre_div.hw,
@@ -1213,7 +1213,7 @@ static struct clk_regmap meson8b_vid_pll_final_div = {
},
.hw.init = &(struct clk_init_data){
.name = "vid_pll_final_div",
- .ops = &clk_regmap_divider_ro_ops,
+ .ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vid_pll.hw
},
@@ -1240,7 +1240,7 @@ static struct clk_regmap meson8b_vclk_in_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk_in_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
.parent_hws = meson8b_vclk_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
@@ -1254,7 +1254,7 @@ static struct clk_regmap meson8b_vclk_in_en = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk_in_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_in_sel.hw
},
@@ -1270,7 +1270,7 @@ static struct clk_regmap meson8b_vclk_en = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_in_en.hw
},
@@ -1286,7 +1286,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk_div1_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_en.hw
},
@@ -1316,7 +1316,7 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk_div2_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_div2_div.hw
},
@@ -1346,7 +1346,7 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk_div4_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_div4_div.hw
},
@@ -1376,7 +1376,7 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk_div6_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_div6_div.hw
},
@@ -1406,7 +1406,7 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk_div12_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk_div12_div.hw
},
@@ -1423,7 +1423,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_in_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
.parent_hws = meson8b_vclk_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
@@ -1437,7 +1437,7 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_in_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_in_sel.hw
},
@@ -1453,7 +1453,7 @@ static struct clk_regmap meson8b_vclk2_clk_en = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_clk_in_en.hw
},
@@ -1469,7 +1469,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_div1_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_clk_en.hw
},
@@ -1499,7 +1499,7 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_div2_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_div2_div.hw
},
@@ -1529,7 +1529,7 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_div4_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_div4_div.hw
},
@@ -1559,7 +1559,7 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_div6_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_div6_div.hw
},
@@ -1589,7 +1589,7 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = {
},
.hw.init = &(struct clk_init_data){
.name = "vclk2_div12_en",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_vclk2_div12_div.hw
},
@@ -1614,7 +1614,7 @@ static struct clk_regmap meson8b_cts_enct_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_enct_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT,
@@ -1628,7 +1628,7 @@ static struct clk_regmap meson8b_cts_enct = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_enct",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_enct_sel.hw
},
@@ -1645,7 +1645,7 @@ static struct clk_regmap meson8b_cts_encp_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_encp_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT,
@@ -1659,7 +1659,7 @@ static struct clk_regmap meson8b_cts_encp = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_encp",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_encp_sel.hw
},
@@ -1676,7 +1676,7 @@ static struct clk_regmap meson8b_cts_enci_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_enci_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT,
@@ -1690,7 +1690,7 @@ static struct clk_regmap meson8b_cts_enci = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_enci",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_enci_sel.hw
},
@@ -1707,7 +1707,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_tx_pixel_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT,
@@ -1721,7 +1721,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = {
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_tx_pixel",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_hdmi_tx_pixel_sel.hw
},
@@ -1746,7 +1746,7 @@ static struct clk_regmap meson8b_cts_encl_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_encl_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT,
@@ -1760,7 +1760,7 @@ static struct clk_regmap meson8b_cts_encl = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_encl",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_encl_sel.hw
},
@@ -1777,7 +1777,7 @@ static struct clk_regmap meson8b_cts_vdac0_sel = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_vdac0_sel",
- .ops = &clk_regmap_mux_ro_ops,
+ .ops = &clk_regmap_mux_ops,
.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
.flags = CLK_SET_RATE_PARENT,
@@ -1791,7 +1791,7 @@ static struct clk_regmap meson8b_cts_vdac0 = {
},
.hw.init = &(struct clk_init_data){
.name = "cts_vdac0",
- .ops = &clk_regmap_gate_ro_ops,
+ .ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&meson8b_cts_vdac0_sel.hw
},
--
2.32.0
Setting the video clocks requires fine-tuned adjustments of various
video clocks. Export the required ones to allow changing the video clock
for the CVBS and HDMI outputs at runtime.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/meson8b.h | 12 +-----------
include/dt-bindings/clock/meson8b-clkc.h | 10 ++++++++++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index b5b591943e80..ce62ed47cbfc 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -117,14 +117,11 @@
#define CLKID_PERIPH_SEL 125
#define CLKID_AXI_SEL 127
#define CLKID_L2_DRAM_SEL 129
-#define CLKID_HDMI_PLL_LVDS_OUT 131
-#define CLKID_HDMI_PLL_HDMI_OUT 132
+#define CLKID_HDMI_PLL_LVDS_OUT 131
#define CLKID_VID_PLL_IN_SEL 133
#define CLKID_VID_PLL_IN_EN 134
#define CLKID_VID_PLL_PRE_DIV 135
#define CLKID_VID_PLL_POST_DIV 136
-#define CLKID_VID_PLL_FINAL_DIV 137
-#define CLKID_VCLK_IN_SEL 138
#define CLKID_VCLK_IN_EN 139
#define CLKID_VCLK_DIV1 140
#define CLKID_VCLK_DIV2_DIV 141
@@ -135,7 +132,6 @@
#define CLKID_VCLK_DIV6 146
#define CLKID_VCLK_DIV12_DIV 147
#define CLKID_VCLK_DIV12 148
-#define CLKID_VCLK2_IN_SEL 149
#define CLKID_VCLK2_IN_EN 150
#define CLKID_VCLK2_DIV1 151
#define CLKID_VCLK2_DIV2_DIV 152
@@ -147,17 +143,11 @@
#define CLKID_VCLK2_DIV12_DIV 158
#define CLKID_VCLK2_DIV12 159
#define CLKID_CTS_ENCT_SEL 160
-#define CLKID_CTS_ENCT 161
#define CLKID_CTS_ENCP_SEL 162
-#define CLKID_CTS_ENCP 163
#define CLKID_CTS_ENCI_SEL 164
-#define CLKID_CTS_ENCI 165
#define CLKID_HDMI_TX_PIXEL_SEL 166
-#define CLKID_HDMI_TX_PIXEL 167
#define CLKID_CTS_ENCL_SEL 168
-#define CLKID_CTS_ENCL 169
#define CLKID_CTS_VDAC0_SEL 170
-#define CLKID_CTS_VDAC0 171
#define CLKID_HDMI_SYS_SEL 172
#define CLKID_HDMI_SYS_DIV 173
#define CLKID_MALI_0_SEL 175
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index f33781338eda..78aa07fd7cc0 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -105,6 +105,16 @@
#define CLKID_PERIPH 126
#define CLKID_AXI 128
#define CLKID_L2_DRAM 130
+#define CLKID_HDMI_PLL_HDMI_OUT 132
+#define CLKID_VID_PLL_FINAL_DIV 137
+#define CLKID_VCLK_IN_SEL 138
+#define CLKID_VCLK2_IN_SEL 149
+#define CLKID_CTS_ENCT 161
+#define CLKID_CTS_ENCP 163
+#define CLKID_CTS_ENCI 165
+#define CLKID_HDMI_TX_PIXEL 167
+#define CLKID_CTS_ENCL 169
+#define CLKID_CTS_VDAC0 171
#define CLKID_HDMI_SYS 174
#define CLKID_VPU 190
#define CLKID_VDEC_1 196
--
2.32.0
Add the reg_sequence to initialize the HDMI PLL with the settings for
a video mode that doesn't require PLL internal clock doubling. These
settings are taken from the 3.10 vendor kernel's driver for the 2970MHz
PLL setting used for the 1080P video mode. This puts the PLL into a
defined state and the Linux kernel can take over.
While not all bits for this PLL are implemented using these "defaults"
and then applying M, N and FRAC seems to work fine.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/meson8b.c | 40 +++++++++++++++++++++++++++++++++----
drivers/clk/meson/meson8b.h | 13 +++++++++++-
2 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 8f29d26ed726..21bc29455f0d 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -118,6 +118,35 @@ static struct clk_regmap meson8b_fixed_pll = {
},
};
+static struct clk_fixed_factor hdmi_pll_dco_in = {
+ .mult = 2,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll_dco_in",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ .index = -1,
+ },
+ .num_parents = 1,
+ },
+};
+
+/*
+ * Taken from the vendor driver for the 2970/2975MHz (both only differ in the
+ * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8,
+ * Meson8b and Meson8m2. This doubles the input (or output - it's not clear
+ * which one but the result is the same) clock. The vendor driver additionally
+ * has the following comment about: "optimise HPLL VCO 2.97GHz performance".
+ */
+static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = {
+ { .reg = HHI_VID_PLL_CNTL2, .def = 0x69c84000 },
+ { .reg = HHI_VID_PLL_CNTL3, .def = 0x8a46c023 },
+ { .reg = HHI_VID_PLL_CNTL4, .def = 0x4123b100 },
+ { .reg = HHI_VID_PLL_CNTL5, .def = 0x00012385 },
+ { .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 },
+};
+
static const struct pll_params_table hdmi_pll_params_table[] = {
PLL_PARAMS(40, 1),
PLL_PARAMS(42, 1),
@@ -172,15 +201,15 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
.width = 1,
},
.table = hdmi_pll_params_table,
+ .init_regs = meson8b_hdmi_pll_init_regs,
+ .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs),
},
.hw.init = &(struct clk_init_data){
/* sometimes also called "HPLL" or "HPLL PLL" */
.name = "hdmi_pll_dco",
.ops = &meson_clk_pll_ro_ops,
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xtal",
- .name = "xtal",
- .index = -1,
+ .parent_hws = (const struct clk_hw *[]) {
+ &hdmi_pll_dco_in.hw
},
.num_parents = 1,
},
@@ -2945,6 +2974,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
[CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -3163,6 +3193,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
[CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
@@ -3383,6 +3414,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
[CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
[CLK_NR_CLKS] = NULL,
},
.num = CLK_NR_CLKS,
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 954d97cf6c5a..b5b591943e80 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -51,6 +51,16 @@
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
+#define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
+#define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */
+#define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
+#define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
+#define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */
+#define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */
+#define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */
+#define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */
+#define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */
+#define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */
/*
* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
@@ -183,8 +193,9 @@
#define CLKID_VCLK_EN 214
#define CLKID_VCLK2_EN 215
#define CLKID_VID_PLL_LVDS_EN 216
+#define CLKID_HDMI_PLL_DCO_IN 217
-#define CLK_NR_CLKS 217
+#define CLK_NR_CLKS 218
/*
* include the CLKID and RESETID that have
--
2.32.0
On Wed 14 Jul 2021 at 01:25, Martin Blumenstingl <[email protected]> wrote:
> The 3.10 vendor kernel uses only specific HDMI PLL M/N parameter
> combinations. The PLL won't lock for values smaller than 50 if the
> internal doubling (which is yet unknown how to use it) is disabled.
> However, when this doubling is enabled then the values smaller than 50
> will lock just fine. The only restriction for values greater than 50 is
> that the resulting frequency must not exceed the 3.0GHz limit.
Hum, it's not the first time we have that type of issue.
I'm thinking that, instead of using mult_range, we should probably have
min and max output frequencies . The datasheet usually documents these
values for PLL DCO. Something to think about ...
>
> These values are taken from the endlessm 3.10 kernel which includes
> additional M/N combinations for some VESA and 75Hz display modes.
>
> Signed-off-by: Martin Blumenstingl <[email protected]>
> ---
> drivers/clk/meson/meson8b.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index 9ccffbfe44e5..8f29d26ed726 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -118,6 +118,27 @@ static struct clk_regmap meson8b_fixed_pll = {
> },
> };
>
> +static const struct pll_params_table hdmi_pll_params_table[] = {
> + PLL_PARAMS(40, 1),
> + PLL_PARAMS(42, 1),
> + PLL_PARAMS(44, 1),
> + PLL_PARAMS(45, 1),
> + PLL_PARAMS(49, 1),
> + PLL_PARAMS(52, 1),
> + PLL_PARAMS(54, 1),
> + PLL_PARAMS(56, 1),
> + PLL_PARAMS(59, 1),
> + PLL_PARAMS(60, 1),
> + PLL_PARAMS(61, 1),
> + PLL_PARAMS(62, 1),
> + PLL_PARAMS(64, 1),
> + PLL_PARAMS(66, 1),
> + PLL_PARAMS(68, 1),
> + PLL_PARAMS(71, 1),
> + PLL_PARAMS(82, 1),
> + { /* sentinel */ }
> +};
> +
> static struct clk_regmap meson8b_hdmi_pll_dco = {
> .data = &(struct meson_clk_pll_data){
> .en = {
> @@ -150,6 +171,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
> .shift = 29,
> .width = 1,
> },
> + .table = hdmi_pll_params_table,
> },
> .hw.init = &(struct clk_init_data){
> /* sometimes also called "HPLL" or "HPLL PLL" */
On Wed 14 Jul 2021 at 01:25, Martin Blumenstingl <[email protected]> wrote:
> The first two patches in this series are small fixes before we can
> actually make the video clock tree mutable. One patch adds
> CLK_SET_RATE_NO_REPARENT for better rate control and the other adds
> a missing clock gate.
>
> The third and fourth patch are targeting the HDMI PLL. Add the known
> working M/N combinations. Also this PLL has some special "doubling"
> setting, which is calculated like this:
> OUTPUT = (IN * M / N + FRAC) * 2
> Since not all register bits are known we use a copy of the 2970/2975MHz
> magic register values from the vendor driver.
>
> The fifth patch makes the clocks in the video clock tree mutable. The
> final patch in this series exports the clocks needed for rate control.
>
> For reference, this is the .dts definition for the Meson8b VPU. The
> code for the VPU driver is unfortunately not ready for upstreaming yet.
> However, I have tested with all resolutions my monitor supports and the
> clock settings are all applied correctly.
> vpu: vpu@100000 {
> compatible = "amlogic,meson8b-vpu";
>
> reg = <0x100000 0x10000>;
> reg-names = "vpu";
>
> interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
>
> amlogic,canvas = <&canvas>;
> amlogic,hhi-sysctrl = <&hhi>;
>
> /*
> * The VCLK{,2}_IN path always needs to derived from
> * the CLKID_VID_PLL_FINAL_DIV so other clocks like
> * MPLL1 are not used (MPLL1 is reserved for audio
> * purposes).
> */
> assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>,
> <&clkc CLKID_VCLK2_IN_SEL>;
> assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>,
> <&clkc CLKID_VID_PLL_FINAL_DIV>;
>
> clocks = <&clkc CLKID_VPU_INTR>,
> <&clkc CLKID_HDMI_INTR_SYNC>,
> <&clkc CLKID_GCLK_VENCI_INT>,
> <&clkc CLKID_HDMI_PLL_HDMI_OUT>,
> <&clkc CLKID_HDMI_TX_PIXEL>,
> <&clkc CLKID_CTS_ENCP>,
> <&clkc CLKID_CTS_ENCI>,
> <&clkc CLKID_CTS_ENCT>,
> <&clkc CLKID_CTS_ENCL>,
> <&clkc CLKID_CTS_VDAC0>;
> clock-names = "vpu_intr",
> "hdmi_intr_sync",
> "venci_int",
> "tmds",
> "hdmi_tx_pixel",
> "cts_encp",
> "cts_enci",
> "cts_enct",
> "cts_encl",
> "cts_vdac0";
>
> resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>,
> <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>,
> <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>,
> <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>;
> reset-names = "vid_pll_pre",
> "vid_pll_post",
> "vid_pll_soft_pre",
> "vid_pll_soft_post";
>
> power-domains = <&pwrc PWRC_MESON8_VPU_ID>;
>
> nvmem-cells = <&cvbs_trimming>;
> nvmem-cell-names = "cvbs_trimming";
>
> #address-cells = <1>;
> #size-cells = <0>;
>
> #sound-dai-cells = <0>;
> sound-name-prefix = "HDMITX";
>
> /* CVBS VDAC output port */
> cvbs_vdac_port: port@0 {
> reg = <0>;
> };
>
> /* HDMI-TX output port */
> hdmi_tx_port: port@1 {
> reg = <1>;
>
> hdmi_tx_out: endpoint {
> remote-endpoint = <&hdmi_tx_in>;
> };
> };
> };
>
>
> Martin Blumenstingl (6):
> clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel
> clk: meson: meson8b: Add the vid_pll_lvds_en gate clock
> clk: meson: meson8b: Add the HDMI PLL M/N parameters
> clk: meson: meson8b: Initialize the HDMI PLL registers
> clk: meson: meson8b: Make the video clock trees mutable
> clk: meson: meson8b: Export the video clocks
>
> drivers/clk/meson/meson8b.c | 163 +++++++++++++++++------
> drivers/clk/meson/meson8b.h | 26 ++--
> include/dt-bindings/clock/meson8b-clkc.h | 10 ++
> 3 files changed, 143 insertions(+), 56 deletions(-)
Applied, Thx