Currently, the designware schema is defined on a text file:
designware-pcie.txt
Convert the pci-bus part into a schema.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 102 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 103 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
new file mode 100644
index 000000000000..d4441d822b91
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare PCIe interface
+
+maintainers:
+ - Jingoo Han <[email protected]>
+ - Gustavo Pimentel <[email protected]>
+
+description: |
+ Synopsys DesignWare PCIe host controller
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ anyOf:
+ - {}
+ - const: snps,dw-pcie
+
+ reg:
+ description: |
+ It should contain Data Bus Interface (dbi) and config registers for all
+ versions.
+ For designware core version >= 4.80, it may contain ATU address space.
+ minItems: 2
+ maxItems: 5
+
+ reg-names:
+ minItems: 2
+ maxItems: 5
+ items:
+ enum: [dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link]
+
+ num-lanes:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: |
+ number of lanes to use (this property should be specified unless
+ the link is brought already up in BIOS)
+ maximum: 16
+
+ reset-gpio:
+ description: GPIO pin number of PERST# signal
+ maxItems: 1
+ deprecated: true
+
+ reset-gpios:
+ description: GPIO controlled connection to PERST# signal
+ maxItems: 1
+
+ interrupts: true
+
+ interrupt-names: true
+
+ clocks: true
+
+ snps,enable-cdm-check:
+ type: boolean
+ description: |
+ This is a boolean property and if present enables
+ automatic checking of CDM (Configuration Dependent Module) registers
+ for data corruption. CDM registers include standard PCIe configuration
+ space registers, Port Logic registers, DMA and iATU (internal Address
+ Translation Unit) registers.
+
+ num-viewport:
+ description: |
+ number of view ports configured in hardware. If a platform
+ does not specify it, the driver autodetects it.
+ deprecated: true
+
+unevaluatedProperties: false
+
+required:
+ - reg
+ - reg-names
+ - compatible
+
+examples:
+ - |
+ bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pcie@dfc00000 {
+ device_type = "pci";
+ compatible = "snps,dw-pcie";
+ reg = <0xdfc00000 0x0001000>, /* IP registers */
+ <0xd0000000 0x0002000>; /* Configuration space */
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
+ <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+ interrupts = <25>, <24>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index fb6971bc28c5..c88f6cb37e47 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14306,6 +14306,7 @@ M: Gustavo Pimentel <[email protected]>
L: [email protected]
S: Maintained
F: Documentation/devicetree/bindings/pci/designware-pcie.txt
+F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
F: drivers/pci/controller/dwc/*designware*
PCI DRIVER FOR TI DRA7XX/J721E
--
2.31.1
On Sun, 18 Jul 2021 13:40:48 +0200, Mauro Carvalho Chehab wrote:
> Currently, the designware schema is defined on a text file:
> designware-pcie.txt
>
> Convert the pci-bus part into a schema.
>
> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> ---
> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 102 ++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 103 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
>
Applied, thanks!