2021-07-26 02:13:43

by Jitao Shi

Subject: [PATCH v3 1/2] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift

The bridge chip ANX7625 requires the packets on lanes aligned at the end,
or ANX7625 will shift the screen.

Signed-off-by: Jitao Shi <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ae403c67cbd9..4735e0092ffe 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;

u32 data_rate;
+ /* force dsi line end without dsi_null data */
+ bool force_dsi_end_without_null;

unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}

+ if (dsi->force_dsi_end_without_null) {
+ horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+ horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+ horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
+ horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
+ }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;

+ if (dsi->next_bridge)
+ dsi->force_dsi_end_without_null = of_property_read_bool(dsi->next_bridge->of_node,
+ "force_dsi_end_without_null");
+
drm_bridge_add(&dsi->bridge);

ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
--
2.25.1

2021-07-26 02:15:11

by Jitao Shi

Subject: [PATCH v3 2/2] dt-bindings: mediatek: add force_dsi_end_without_null for dsi

Some bridge chip will shift screen when the dsi data does't ent at
the same time in line.

Signed-off-by: Jitao Shi <[email protected]>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index 8238a86686be..1c2f53f3ac3d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -19,6 +19,10 @@ Required properties:
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.

+Optional properties:
+- force_dsi_end_without_null: Some bridge chip(ex. ANX7625) requires the
+ packets on lanes aligned at the end.
+
MIPI TX Configuration Module
============================

--
2.25.1

2021-07-26 04:05:05

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 2/2] dt-bindings: mediatek: add force_dsi_end_without_null for dsi

Hi, Jitao:

On Mon, 2021-07-26 at 10:11 +0800, Jitao Shi wrote:
> Some bridge chip will shift screen when the dsi data does't ent at
> the same time in line.
>
> Signed-off-by: Jitao Shi <[email protected]>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> index 8238a86686be..1c2f53f3ac3d 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> @@ -19,6 +19,10 @@ Required properties:
> Documentation/devicetree/bindings/graph.txt. This port should be connected
> to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
>
> +Optional properties:
> +- force_dsi_end_without_null: Some bridge chip(ex. ANX7625) requires the
> + packets on lanes aligned at the end.
> +

I think you should add this property in [1] because this limitation is
ANX7625's limitation.

[1]
Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml

Regards,
CK

> MIPI TX Configuration Module
> ============================
>