From: Mark Kettenis <[email protected]>
This small series adds bindings for the PCIe controller found on the
Apple M1 SoC.
At this point, the primary consumer for these bindings is U-Boot.
With these bindings U-Boot can bring up the links for the root ports
of the PCIe root complex. A simple OS driver can then provide
standard ECAM access and manage MSI interrupts to provide access
to the built-in Ethernet and XHCI controllers of the Mac mini.
The Apple controller incorporates Synopsys Designware PCIe logic
to implement its root port. But unlike other hardware currently
supported by U-Boot and the Linux kernel the Apple hardware
integrates multiple root ports. As such the existing bindings
for the DWC PCIe interface can't be used. There is a single ECAM
space for all root space, but separate GPIOs to take the PCI devices
on those ports out of reset. Therefore the standard "reset-gpio" and
"max-link-speed" properties appear on the child nodes representing
the PCI devices that correspond to the individual root ports.
MSIs are handled by the PCIe controller and translated into "regular
interrupts". A range of 32 MSIs is provided. These 32 MSIs can be
distributed over the root ports as the OS sees fit by programming the
PCIe controller port registers.
I still hope to hear from Marc Zyngier on the way MSIs are represented
in this binding.
Patch 2/2 of this series depends on the pinctrl series I sent earlier
and will probably go through Hector Martin's Apple M1 SoC tree.
Changelog:
v3: - Remove unneeded include in example
v2: - Adjust name for ECAM in "reg-names"
- Drop "phy" registers
- Expand description
- Add description for "interrupts"
- Fix incorrect minItems for "interrupts"
- Fix incorrect MaxItems for "reg-names"
- Document the use of "msi-controller", "msi-parent", "iommu-map" and
"iommu-map-mask"
- Fix "bus-range" and "iommu-map" properties in the example
Mark Kettenis (2):
dt-bindings: pci: Add DT bindings for apple,pcie
arm64: apple: Add PCIe node
.../devicetree/bindings/pci/apple,pcie.yaml | 166 ++++++++++++++++++
MAINTAINERS | 1 +
arch/arm64/boot/dts/apple/t8103.dtsi | 63 +++++++
3 files changed, 230 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/apple,pcie.yaml
--
2.32.0
From: Mark Kettenis <[email protected]>
Add node corresponding to the apcie,t8103 node in the
Apple device tree for the Mac mini (M1, 2020).
Clock references and DART (IOMMU) references are left out at the
moment and will be added once the appropriate bindings have been
settled upon.
Signed-off-by: Mark Kettenis <[email protected]>
---
arch/arm64/boot/dts/apple/t8103.dtsi | 63 ++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi
index 503a76fc30e6..cd3ebb940e86 100644
--- a/arch/arm64/boot/dts/apple/t8103.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103.dtsi
@@ -214,5 +214,68 @@ pinctrl_smc: pinctrl@23e820000 {
<AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ pcie0: pcie@690000000 {
+ compatible = "apple,t8103-pcie", "apple,pcie";
+ device_type = "pci";
+
+ reg = <0x6 0x90000000 0x0 0x1000000>,
+ <0x6 0x80000000 0x0 0x4000>,
+ <0x6 0x81000000 0x0 0x8000>,
+ <0x6 0x82000000 0x0 0x8000>,
+ <0x6 0x83000000 0x0 0x8000>;
+ reg-names = "config", "rc", "port0", "port1", "port2";
+
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
+
+ msi-controller;
+ msi-parent = <&pcie0>;
+ msi-ranges = <704 32>;
+
+ bus-range = <0 3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
+ <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
+
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+
+ pci@0,0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 152 0>;
+ max-link-speed = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pci@1,0 {
+ device_type = "pci";
+ reg = <0x800 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 153 0>;
+ max-link-speed = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ reg = <0x1000 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 33 0>;
+ max-link-speed = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
};
};
--
2.32.0
On Mon, 26 Jul 2021 09:31:59 +0100,
Mark Kettenis <[email protected]> wrote:
>
> From: Mark Kettenis <[email protected]>
>
> This small series adds bindings for the PCIe controller found on the
> Apple M1 SoC.
>
> At this point, the primary consumer for these bindings is U-Boot.
> With these bindings U-Boot can bring up the links for the root ports
> of the PCIe root complex. A simple OS driver can then provide
> standard ECAM access and manage MSI interrupts to provide access
> to the built-in Ethernet and XHCI controllers of the Mac mini.
>
> The Apple controller incorporates Synopsys Designware PCIe logic
> to implement its root port. But unlike other hardware currently
> supported by U-Boot and the Linux kernel the Apple hardware
> integrates multiple root ports. As such the existing bindings
> for the DWC PCIe interface can't be used. There is a single ECAM
> space for all root space, but separate GPIOs to take the PCI devices
> on those ports out of reset. Therefore the standard "reset-gpio" and
> "max-link-speed" properties appear on the child nodes representing
> the PCI devices that correspond to the individual root ports.
>
> MSIs are handled by the PCIe controller and translated into "regular
> interrupts". A range of 32 MSIs is provided. These 32 MSIs can be
> distributed over the root ports as the OS sees fit by programming the
> PCIe controller port registers.
>
> I still hope to hear from Marc Zyngier on the way MSIs are represented
> in this binding.
>
> Patch 2/2 of this series depends on the pinctrl series I sent earlier
> and will probably go through Hector Martin's Apple M1 SoC tree.
>
>
> Changelog:
>
> v3: - Remove unneeded include in example
>
> v2: - Adjust name for ECAM in "reg-names"
> - Drop "phy" registers
> - Expand description
> - Add description for "interrupts"
> - Fix incorrect minItems for "interrupts"
> - Fix incorrect MaxItems for "reg-names"
> - Document the use of "msi-controller", "msi-parent", "iommu-map" and
> "iommu-map-mask"
> - Fix "bus-range" and "iommu-map" properties in the example
>
> Mark Kettenis (2):
> dt-bindings: pci: Add DT bindings for apple,pcie
> arm64: apple: Add PCIe node
>
> .../devicetree/bindings/pci/apple,pcie.yaml | 166 ++++++++++++++++++
> MAINTAINERS | 1 +
> arch/arm64/boot/dts/apple/t8103.dtsi | 63 +++++++
> 3 files changed, 230 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/apple,pcie.yaml
Thanks a log for doing this! For the whole series:
Reviewed-by: Marc Zyngier <[email protected]>
M.
--
Without deviation from the norm, progress is not possible.