Changes in v8:
- Rebased on next-20210728
- Fixed all YAML issues from dt_binding_check
- Fixed forgotten signoffs (truly, truly sorry about that)
Changes in v7:
- Fixed functionality breakage on ARM for cpuidle-qcom-spm... now it works :))
- Reworded description of patch 1/5
Changes in v6:
- Moved cpuidle_driver to be private to cpuidle-qcom-spm (unused in spm.c),
now we are assigning the cpuidle_driver structure fields inside of the
spm_cpuidle_register function; this also fixes the cpumask assignment
issue from v5
- Fixed another contamination from 2/3 in 1/3 (argh!! :])
- Added dt-bindings documentation for the SPM driver
Changes in v5:
- Fixed contamination from patch 2/3 in patch 1/3
- Fixed missing bits in cpuidle-qcom-spm (thanks Stephan)
Changes in v4:
- Huge patch series has been split for better reviewability,
as suggested by Bjorn
Changes in v3:
- Rebased (no changes - was in previous series' v3)
Changes in v2:
- Fixed MSM8998 SAW parameters on SPM driver
Tested on the following smartphones:
- Sony Xperia XA2 (SDM630)
- Sony Xperia XA2 Ultra (SDM630)
- Sony Xperia 10 (SDM630)
- Sony Xperia XZ Premium (MSM8998)
- F(x)Tec Pro 1 (MSM8998)
This is a component that we can find on very old
chips, like MSM8974; there, it has been used to actually do the
power scaling basically "on its own" - sending the cores in a specific
sleep mode to save power.
On the newer ones, including MSM8998, SDM630, 660 and others, it is still
present! Though, this time, it's being used for the cluster caches and it
has a different firmware (and maybe it's also slightly different HW),
implementing the SAWv4.1 set and getting controlled *not by the OS* but
by other controllers in the SoC (like the OSM).
Contrary from MSM8974 and the like, this new version of the SPM just
requires us to set the initial parameters for AVS and *nothing else*, as
its states will be totally managed internally.
AngeloGioacchino Del Regno (5):
cpuidle: qcom_spm: Detach state machine from main SPM handling
dt-bindings: soc: qcom: Add devicetree binding for QCOM SPM
soc: qcom: spm: Implement support for SAWv4.1, SDM630/660 L2 AVS
soc: qcom: spm: Add compatible for MSM8998 SAWv4.1 L2
dt-bindings: soc: qcom: spm: Document SDM660 and MSM8998 compatibles
.../bindings/soc/qcom/qcom,spm.yaml | 80 +++++
drivers/cpuidle/Kconfig.arm | 1 +
drivers/cpuidle/cpuidle-qcom-spm.c | 318 ++++--------------
drivers/soc/qcom/Kconfig | 9 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/spm.c | 254 ++++++++++++++
include/soc/qcom/spm.h | 43 +++
7 files changed, 456 insertions(+), 250 deletions(-)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
create mode 100644 drivers/soc/qcom/spm.c
create mode 100644 include/soc/qcom/spm.h
--
2.32.0
Implement the support for SAW v4.1, used in at least MSM8998,
SDM630, SDM660 and APQ variants and, while at it, also add the
configuration for the SDM630/660 Silver and Gold cluster L2
Adaptive Voltage Scaler: this is also one of the prerequisites
to allow the OSM controller to perform DCVS.
Please note that despite there are various "versions" of these
values downstream, these are the only ones that are perfectly
stable on the entire set of tested devices.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Stephan Gerhold <[email protected]>
---
drivers/soc/qcom/spm.c | 32 +++++++++++++++++++++++++++++---
include/soc/qcom/spm.h | 4 +++-
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index d5ba0b5488fc..28ffaa2a3509 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -32,10 +32,29 @@ enum spm_reg {
SPM_REG_SEQ_ENTRY,
SPM_REG_SPM_STS,
SPM_REG_PMIC_STS,
+ SPM_REG_AVS_CTL,
+ SPM_REG_AVS_LIMIT,
SPM_REG_NR,
};
-static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
+static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = {
+ [SPM_REG_AVS_CTL] = 0x904,
+ [SPM_REG_AVS_LIMIT] = 0x908,
+};
+
+static const struct spm_reg_data spm_reg_660_gold_l2 = {
+ .reg_offset = spm_reg_offset_v4_1,
+ .avs_ctl = 0x1010031,
+ .avs_limit = 0x4580458,
+};
+
+static const struct spm_reg_data spm_reg_660_silver_l2 = {
+ .reg_offset = spm_reg_offset_v4_1,
+ .avs_ctl = 0x101c031,
+ .avs_limit = 0x4580458,
+};
+
+static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
[SPM_REG_CFG] = 0x08,
[SPM_REG_SPM_CTL] = 0x30,
[SPM_REG_DLY] = 0x34,
@@ -66,7 +85,7 @@ static const struct spm_reg_data spm_reg_8226_cpu = {
.start_index[PM_SLEEP_MODE_SPC] = 5,
};
-static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
+static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
[SPM_REG_CFG] = 0x08,
[SPM_REG_SPM_CTL] = 0x20,
[SPM_REG_PMIC_DLY] = 0x24,
@@ -138,6 +157,10 @@ void spm_set_low_power_mode(struct spm_driver_data *drv,
}
static const struct of_device_id spm_match_table[] = {
+ { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
+ .data = &spm_reg_660_gold_l2 },
+ { .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
+ .data = &spm_reg_660_silver_l2 },
{ .compatible = "qcom,msm8226-saw2-v2.1-cpu",
.data = &spm_reg_8226_cpu },
{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
@@ -183,6 +206,8 @@ static int spm_dev_probe(struct platform_device *pdev)
* CPU was held in reset, the reset signal could trigger the SPM state
* machine, before the sequences are completely written.
*/
+ spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl);
+ spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit);
spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
@@ -192,7 +217,8 @@ static int spm_dev_probe(struct platform_device *pdev)
drv->reg_data->pmic_data[1]);
/* Set up Standby as the default low power mode */
- spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
+ if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
+ spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
return 0;
}
diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
index 4c7e5ac2583d..4951f9d8b0bd 100644
--- a/include/soc/qcom/spm.h
+++ b/include/soc/qcom/spm.h
@@ -21,11 +21,13 @@ enum pm_sleep_mode {
};
struct spm_reg_data {
- const u8 *reg_offset;
+ const u16 *reg_offset;
u32 spm_cfg;
u32 spm_dly;
u32 pmic_dly;
u32 pmic_data[MAX_PMIC_DATA];
+ u32 avs_ctl;
+ u32 avs_limit;
u8 seq[MAX_SEQ_DATA];
u8 start_index[PM_SLEEP_MODE_NR];
};
--
2.32.0
Add the SAWv4.1 parameters for MSM8998's Gold and Silver clusters.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Stephan Gerhold <[email protected]>
---
drivers/soc/qcom/spm.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 28ffaa2a3509..6974f911ba80 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -54,6 +54,18 @@ static const struct spm_reg_data spm_reg_660_silver_l2 = {
.avs_limit = 0x4580458,
};
+static const struct spm_reg_data spm_reg_8998_gold_l2 = {
+ .reg_offset = spm_reg_offset_v4_1,
+ .avs_ctl = 0x1010031,
+ .avs_limit = 0x4700470,
+};
+
+static const struct spm_reg_data spm_reg_8998_silver_l2 = {
+ .reg_offset = spm_reg_offset_v4_1,
+ .avs_ctl = 0x1010031,
+ .avs_limit = 0x4200420,
+};
+
static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
[SPM_REG_CFG] = 0x08,
[SPM_REG_SPM_CTL] = 0x30,
@@ -165,6 +177,10 @@ static const struct of_device_id spm_match_table[] = {
.data = &spm_reg_8226_cpu },
{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
.data = &spm_reg_8974_8084_cpu },
+ { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
+ .data = &spm_reg_8998_gold_l2 },
+ { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
+ .data = &spm_reg_8998_silver_l2 },
{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
.data = &spm_reg_8974_8084_cpu },
{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
--
2.32.0
The driver was updated to add SAW2 v4.1 support for new SoCs: document
the new compatibles.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../bindings/soc/qcom/qcom,spm.yaml | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
index 507216100e3f..d68c002527fa 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
@@ -18,6 +18,10 @@ properties:
compatible:
items:
- enum:
+ - qcom,sdm660-gold-saw2-v4.1-l2
+ - qcom,sdm660-silver-saw2-v4.1-l2
+ - qcom,msm8998-gold-saw2-v4.1-l2
+ - qcom,msm8998-silver-saw2-v4.1-l2
- qcom,msm8226-saw2-v2.1-cpu
- qcom,msm8974-saw2-v2.1-cpu
- qcom,apq8084-saw2-v2.1-cpu
@@ -36,6 +40,8 @@ additionalProperties: false
examples:
- |
+
+ /* Example 1: SoC using SAW2 and kpss-acc-v2 CPUIdle */
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -55,4 +61,20 @@ examples:
reg = <0xf9089000 0x1000>;
};
+ - |
+
+ /*
+ * Example 2: New-gen multi cluster SoC using SAW only for L2;
+ * This does not require any cpuidle driver, nor any cpu phandle.
+ */
+ power-manager@17812000 {
+ compatible = "qcom,msm8998-gold-saw2-v4.1-l2", "qcom,saw2";
+ reg = <0x17812000 0x1000>;
+ };
+
+ power-manager@17912000 {
+ compatible = "qcom,msm8998-silver-saw2-v4.1-l2", "qcom,saw2";
+ reg = <0x17912000 0x1000>;
+ };
+
...
--
2.32.0
On Thu, 29 Jul 2021 17:56:09 +0200, AngeloGioacchino Del Regno wrote:
> The driver was updated to add SAW2 v4.1 support for new SoCs: document
> the new compatibles.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> .../bindings/soc/qcom/qcom,spm.yaml | 22 +++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>