From: Like Xu <[email protected]>
If we use "perf record" in an AMD Milan guest, dmesg reports a #GP
warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx:
[] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write
0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20)
[] Call Trace:
[] amd_pmu_disable_event+0x22/0x90
[] x86_pmu_stop+0x4c/0xa0
[] x86_pmu_del+0x3a/0x140
The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host,
while the guest perf driver should avoid such use.
Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
Signed-off-by: Like Xu <[email protected]>
Tested-by: Kim Phillips <[email protected]>
---
v2: Add Fixes tag and Tested-by from Kim.
v1: https://lore.kernel.org/lkml/[email protected]/
arch/x86/events/perf_event.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index d6003e08b055..1c3ae954a230 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1116,8 +1116,9 @@ void x86_pmu_stop(struct perf_event *event, int flags);
static inline void x86_pmu_disable_event(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
+ u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
- wrmsrl(hwc->config_base, hwc->config);
+ wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
if (is_counter_pair(hwc))
wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
--
2.32.0
On (08/02/21 15:08), Like Xu wrote:
> Date: Mon, 2 Aug 2021 15:08:50 +0800
> From: Like Xu <[email protected]>
> To: Peter Zijlstra <[email protected]>, Joerg Roedel
> <[email protected]>
> Cc: Ingo Molnar <[email protected]>, Arnaldo Carvalho de Melo
> <[email protected]>, Mark Rutland <[email protected]>, Alexander Shishkin
> <[email protected]>, Jiri Olsa <[email protected]>,
> Namhyung Kim <[email protected]>, Thomas Gleixner <[email protected]>,
> Borislav Petkov <[email protected]>, [email protected], "H . Peter Anvin"
> <[email protected]>, [email protected],
> [email protected]
> Subject: [PATCH v2] perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY
> bit inside the guest
> X-Mailer: git-send-email 2.32.0
>
> From: Like Xu <[email protected]>
>
> If we use "perf record" in an AMD Milan guest, dmesg reports a #GP
> warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx:
>
> [] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write
> 0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20)
> [] Call Trace:
> [] amd_pmu_disable_event+0x22/0x90
> [] x86_pmu_stop+0x4c/0xa0
> [] x86_pmu_del+0x3a/0x140
>
> The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host,
> while the guest perf driver should avoid such use.
>
> Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
> Signed-off-by: Like Xu <[email protected]>
> Tested-by: Kim Phillips <[email protected]>
Reviewed-by: Liam Merwick <[email protected]>
Tested-by: Liam Merwick <[email protected]>
[ Patch applied to a 5.4 branch ]
Should it also include
Cc: [email protected]
Regards,
Liam
> ---
> v2: Add Fixes tag and Tested-by from Kim.
> v1: https://lore.kernel.org/lkml/[email protected]/
>
> arch/x86/events/perf_event.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index d6003e08b055..1c3ae954a230 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -1116,8 +1116,9 @@ void x86_pmu_stop(struct perf_event *event, int flags);
> static inline void x86_pmu_disable_event(struct perf_event *event)
> {
> struct hw_perf_event *hwc = &event->hw;
> + u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
>
> - wrmsrl(hwc->config_base, hwc->config);
> + wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
>
> if (is_counter_pair(hwc))
> wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
> --
> 2.32.0
>
On Wed, Aug 04, 2021 at 12:28:54PM +0100, Liam Merwick wrote:
> On (08/02/21 15:08), Like Xu wrote:
> > From: Like Xu <[email protected]>
> >
> > If we use "perf record" in an AMD Milan guest, dmesg reports a #GP
> > warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx:
> >
> > [] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write
> > 0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20)
> > [] Call Trace:
> > [] amd_pmu_disable_event+0x22/0x90
> > [] x86_pmu_stop+0x4c/0xa0
> > [] x86_pmu_del+0x3a/0x140
> >
> > The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host,
> > while the guest perf driver should avoid such use.
> >
> > Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
> > Signed-off-by: Like Xu <[email protected]>
> > Tested-by: Kim Phillips <[email protected]>
>
> Reviewed-by: Liam Merwick <[email protected]>
> Tested-by: Liam Merwick <[email protected]>
> [ Patch applied to a 5.4 branch ]
>
> Should it also include
>
> Cc: [email protected]
An accurate Fixes tag is usually sufficient to trigger the stable
robots. Anyway, thanks!
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27
Gitweb: https://git.kernel.org/tip/df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27
Author: Like Xu <[email protected]>
AuthorDate: Mon, 02 Aug 2021 15:08:50 +08:00
Committer: Peter Zijlstra <[email protected]>
CommitterDate: Wed, 04 Aug 2021 15:16:34 +02:00
perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest
If we use "perf record" in an AMD Milan guest, dmesg reports a #GP
warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx:
[] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20)
[] Call Trace:
[] amd_pmu_disable_event+0x22/0x90
[] x86_pmu_stop+0x4c/0xa0
[] x86_pmu_del+0x3a/0x140
The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host,
while the guest perf driver should avoid such use.
Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
Signed-off-by: Like Xu <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Reviewed-by: Liam Merwick <[email protected]>
Tested-by: Kim Phillips <[email protected]>
Tested-by: Liam Merwick <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
---
arch/x86/events/perf_event.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 2bf1c7e..2938c90 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1115,9 +1115,10 @@ void x86_pmu_stop(struct perf_event *event, int flags);
static inline void x86_pmu_disable_event(struct perf_event *event)
{
+ u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
struct hw_perf_event *hwc = &event->hw;
- wrmsrl(hwc->config_base, hwc->config);
+ wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
if (is_counter_pair(hwc))
wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);