This adds thermal support for mt8195.
Depends on https://patchwork.kernel.org/project/linux-mediatek/list/?series=502403
The changes required to support the mt8195 look very similar to those for
the mt6873 but the differences make code factorisation difficult.
Alexandre Bailon (1):
dt-bindings: thermal: Add binding document for mt8195 thermal
controller
Michael Kao (1):
thermal: mediatek: Add thermal zone settings for mt8195
Tinghan Shen (1):
arm64: dts: mt8195: Add thermal zone and thermal policy
.../thermal/mediatek-thermal-lvts.yaml | 6 +-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 164 ++++++++++++++
drivers/thermal/mediatek/soc_temp_lvts.c | 209 ++++++++++++++++--
3 files changed, 361 insertions(+), 18 deletions(-)
--
2.31.1
This patch adds binding document for mt8195 thermal controller.
Signed-off-by: Alexandre Bailon <[email protected]>
---
.../devicetree/bindings/thermal/mediatek-thermal-lvts.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml b/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml
index 69ffe7b14c212..2e1ae00d4fd18 100644
--- a/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml
+++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml
@@ -12,7 +12,11 @@ maintainers:
properties:
compatible:
- const: mediatek,mt6873-lvts
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt6873-lvts
+ - mediatek,mt8195-lvts
reg:
maxItems: 1
--
2.31.1
From: Tinghan Shen <[email protected]>
1. Add SoC and board thermal zones.
2. Add thermal throttle policy
Signed-off-by: Tinghan Shen <[email protected]>
Signed-off-by: Ben Tseng <[email protected]>
Signed-off-by: Alexandre Bailon <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 164 +++++++++++++++++++++++
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d05492ff8f190..62d0944dea4db 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "mediatek,mt8195";
@@ -475,6 +476,21 @@ spi0: spi@1100a000 {
status = "disabled";
};
+ lvts: lvts@1100b000 {
+ compatible = "mediatek,mt8195-lvts";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x1100b000 0 0x1000>,
+ <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ clock-names = "lvts_clk";
+ resets = <&infracfg_rst 1>,
+ <&infracfg_rst 2>;
+ nvmem-cells = <&lvts_e_data1 &lvts_e_data2>;
+ nvmem-cell-names = "e_data1","e_data2";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi";
reg = <0 0x11010000 0 0x100>;
@@ -830,4 +846,152 @@ vdosys1: syscon@1c100000 {
#clock-cells = <1>;
};
};
+
+ thermal_zones: thermal-zones {
+ soc_max {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <1000>; /* milliseconds */
+ thermal-sensors = <&lvts 0>;
+ sustainable-power = <1500>;
+
+ trips {
+ threshold: trip-point@0 {
+ temperature = <68000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: target@1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ soc_max_crit: soc_max_crit@0 {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu1
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu2
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu3
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ contribution = <3072>;
+ };
+ map1 {
+ trip = <&target>;
+ cooling-device = <&cpu4
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu5
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu6
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu7
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ contribution = <1024>;
+ };
+ };
+ };
+ cpu_big1 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 1>;
+ };
+ cpu_big2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 2>;
+ };
+ cpu_big3 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 3>;
+ };
+ cpu_big4 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 4>;
+ };
+ cpu_little1{
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 5>;
+ };
+ cpu_little2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 6>;
+ };
+ cpu_little3 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 7>;
+ };
+ cpu_little4 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 8>;
+ };
+ vpu1 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 9>;
+ };
+ vpu2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 10>;
+ };
+ gpu1 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 11>;
+ };
+ gpu2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 12>;
+ };
+ vdec {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 13>;
+ };
+ img {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 14>;
+ };
+ infra {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 15>;
+ };
+ cam1 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 16>;
+ };
+ cam2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 17>;
+ };
+ };
};
--
2.31.1
From: Michael Kao <[email protected]>
Add thermal zone settings for mt8195
Signed-off-by: Michael Kao <[email protected]>
Signed-off-by: Ben Tseng <[email protected]>
Signed-off-by: Alexandre Bailon <[email protected]>
---
drivers/thermal/mediatek/soc_temp_lvts.c | 206 +++++++++++++++++++++--
1 file changed, 192 insertions(+), 14 deletions(-)
diff --git a/drivers/thermal/mediatek/soc_temp_lvts.c b/drivers/thermal/mediatek/soc_temp_lvts.c
index 8153edaaf8150..ddcedcedbbc16 100644
--- a/drivers/thermal/mediatek/soc_temp_lvts.c
+++ b/drivers/thermal/mediatek/soc_temp_lvts.c
@@ -53,6 +53,7 @@
#define CLOCK_26MHZ_CYCLE_NS (38)
#define BUS_ACCESS_US (2)
+#define GOLDEN_TEMP_MAX (62)
#define FEATURE_DEVICE_AUTO_RCK (BIT(0))
#define FEATURE_CK26M_ACTIVE (BIT(1))
@@ -577,21 +578,10 @@ static int prepare_calibration_data(struct lvts_data *lvts_data)
if (!cal_data->count_rc)
return -ENOMEM;
- if (ops->efuse_to_cal_data)
+ if (ops->efuse_to_cal_data && !cal_data->use_fake_efuse)
ops->efuse_to_cal_data(lvts_data);
-
- cal_data->use_fake_efuse = 1;
- if (cal_data->golden_temp != 0) {
- cal_data->use_fake_efuse = 0;
- } else {
- for (i = 0; i < lvts_data->num_sensor; i++) {
- if (cal_data->count_r[i] != 0 ||
- cal_data->count_rc[i] != 0) {
- cal_data->use_fake_efuse = 0;
- break;
- }
- }
- }
+ if (cal_data->golden_temp == 0 || cal_data->golden_temp > GOLDEN_TEMP_MAX)
+ cal_data->use_fake_efuse = 1;
if (cal_data->use_fake_efuse) {
/* It means all efuse data are equal to 0 */
@@ -1254,6 +1244,190 @@ static struct lvts_data mt6873_lvts_data = {
},
};
+/*==================================================
+ * LVTS MT8195
+ *==================================================
+ */
+
+#define MT8195_NUM_LVTS (ARRAY_SIZE(mt8195_tc_settings))
+
+enum mt8195_lvts_domain {
+ MT8195_AP_DOMAIN,
+ MT8195_MCU_DOMAIN,
+ MT8195_NUM_DOMAIN
+};
+
+enum mt8195_lvts_sensor_enum {
+ MT8195_TS1_0,
+ MT8195_TS1_1,
+ MT8195_TS2_0,
+ MT8195_TS2_1,
+ MT8195_TS3_0,
+ MT8195_TS3_1,
+ MT8195_TS3_2,
+ MT8195_TS3_3,
+ MT8195_TS4_0,
+ MT8195_TS4_1,
+ MT8195_TS5_0,
+ MT8195_TS5_1,
+ MT8195_TS6_0,
+ MT8195_TS6_1,
+ MT8195_TS6_2,
+ MT8195_TS7_0,
+ MT8195_TS7_1,
+ MT8195_NUM_TS
+};
+
+static void mt8195_efuse_to_cal_data(struct lvts_data *lvts_data)
+{
+ struct sensor_cal_data *cal_data = &lvts_data->cal_data;
+
+ cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, 31, 24);
+ cal_data->count_r[MT8195_TS1_0] = GET_CAL_DATA_BITMASK(1, 23, 0);
+ cal_data->count_r[MT8195_TS1_1] = (GET_CAL_DATA_BITMASK(2, 15, 0) << 8) +
+ GET_CAL_DATA_BITMASK(1, 31, 24);
+ cal_data->count_r[MT8195_TS2_0] = GET_CAL_DATA_BITMASK(3, 31, 8);
+ cal_data->count_r[MT8195_TS2_1] = GET_CAL_DATA_BITMASK(4, 23, 0);
+ cal_data->count_r[MT8195_TS3_0] = (GET_CAL_DATA_BITMASK(6, 7, 0) << 16) +
+ GET_CAL_DATA_BITMASK(5, 31, 16);
+ cal_data->count_r[MT8195_TS3_1] = GET_CAL_DATA_BITMASK(6, 31, 8);
+ cal_data->count_r[MT8195_TS3_2] = GET_CAL_DATA_BITMASK(7, 23, 0);
+ cal_data->count_r[MT8195_TS3_3] = (GET_CAL_DATA_BITMASK(8, 15, 0) << 8) +
+ GET_CAL_DATA_BITMASK(7, 31, 24);
+ cal_data->count_r[MT8195_TS4_0] = GET_CAL_DATA_BITMASK(9, 31, 8);
+ cal_data->count_r[MT8195_TS4_1] = GET_CAL_DATA_BITMASK(10, 23, 0);
+ cal_data->count_r[MT8195_TS5_0] = (GET_CAL_DATA_BITMASK(12, 7, 0) << 16) +
+ GET_CAL_DATA_BITMASK(11, 31, 16);
+ cal_data->count_r[MT8195_TS5_1] = GET_CAL_DATA_BITMASK(12, 31, 8);
+ cal_data->count_r[MT8195_TS6_0] = (GET_CAL_DATA_BITMASK(14, 15, 0) << 8) +
+ GET_CAL_DATA_BITMASK(13, 31, 24);
+ cal_data->count_r[MT8195_TS6_1] = (GET_CAL_DATA_BITMASK(15, 7, 0) << 16) +
+ GET_CAL_DATA_BITMASK(14, 31, 16);
+ cal_data->count_r[MT8195_TS6_2] = GET_CAL_DATA_BITMASK(15, 31, 8);
+ cal_data->count_r[MT8195_TS7_0] = (GET_CAL_DATA_BITMASK(17, 15, 0) << 8) +
+ GET_CAL_DATA_BITMASK(16, 31, 24);
+ cal_data->count_r[MT8195_TS7_1] = (GET_CAL_DATA_BITMASK(18, 7, 0) << 16) +
+ GET_CAL_DATA_BITMASK(17, 31, 16);
+ cal_data->count_rc[MT8195_TS1_0] = (GET_CAL_DATA_BITMASK(3, 7, 0) << 16) +
+ GET_CAL_DATA_BITMASK(2, 31, 16);
+ cal_data->count_rc[MT8195_TS2_0] = (GET_CAL_DATA_BITMASK(5, 15, 0) << 8) +
+ GET_CAL_DATA_BITMASK(4, 31, 24);
+ cal_data->count_rc[MT8195_TS3_0] = (GET_CAL_DATA_BITMASK(9, 7, 0) << 16) +
+ GET_CAL_DATA_BITMASK(8, 31, 16);
+ cal_data->count_rc[MT8195_TS4_0] = (GET_CAL_DATA_BITMASK(11, 15, 0) << 8) +
+ GET_CAL_DATA_BITMASK(10, 31, 24);
+ cal_data->count_rc[MT8195_TS5_0] = GET_CAL_DATA_BITMASK(13, 23, 0);
+ cal_data->count_rc[MT8195_TS6_0] = GET_CAL_DATA_BITMASK(16, 23, 0);
+ cal_data->count_rc[MT8195_TS7_0] = GET_CAL_DATA_BITMASK(18, 31, 8);
+}
+
+static struct tc_settings mt8195_tc_settings[] = {
+ [0] = {
+ .domain_index = MT8195_MCU_DOMAIN,
+ .addr_offset = 0x0,
+ .num_sensor = 2,
+ .sensor_map = {MT8195_TS1_0, MT8195_TS1_1},
+ .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118),
+ .hw_filter = LVTS_FILTER_2_OF_4,
+ .dominator_sensing_point = SENSING_POINT1,
+ .hw_reboot_trip_point = 117000,
+ .irq_bit = BIT(3),
+ },
+ [1] = {
+ .domain_index = MT8195_MCU_DOMAIN,
+ .addr_offset = 0x100,
+ .num_sensor = 2,
+ .sensor_map = {MT8195_TS2_0, MT8195_TS2_1},
+ .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118),
+ .hw_filter = LVTS_FILTER_2_OF_4,
+ .dominator_sensing_point = SENSING_POINT0,
+ .hw_reboot_trip_point = 117000,
+ .irq_bit = BIT(4),
+ },
+ [2] = {
+ .domain_index = MT8195_MCU_DOMAIN,
+ .addr_offset = 0x200,
+ .num_sensor = 4,
+ .sensor_map = {MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, MT8195_TS3_3},
+ .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118),
+ .hw_filter = LVTS_FILTER_2_OF_4,
+ .dominator_sensing_point = SENSING_POINT0,
+ .hw_reboot_trip_point = 117000,
+ .irq_bit = BIT(5),
+ },
+ [3] = {
+ .domain_index = MT8195_AP_DOMAIN,
+ .addr_offset = 0x0,
+ .num_sensor = 2,
+ .sensor_map = {MT8195_TS4_0, MT8195_TS4_1},
+ .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118),
+ .hw_filter = LVTS_FILTER_2_OF_4,
+ .dominator_sensing_point = SENSING_POINT0,
+ .hw_reboot_trip_point = 117000,
+ .irq_bit = BIT(3),
+ },
+ [4] = {
+ .domain_index = MT8195_AP_DOMAIN,
+ .addr_offset = 0x100,
+ .num_sensor = 2,
+ .sensor_map = {MT8195_TS5_0, MT8195_TS5_1},
+ .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118),
+ .hw_filter = LVTS_FILTER_2_OF_4,
+ .dominator_sensing_point = SENSING_POINT1,
+ .hw_reboot_trip_point = 117000,
+ .irq_bit = BIT(4),
+ },
+ [5] = {
+ .domain_index = MT8195_AP_DOMAIN,
+ .addr_offset = 0x200,
+ .num_sensor = 3,
+ .sensor_map = {MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2},
+ .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118),
+ .hw_filter = LVTS_FILTER_2_OF_4,
+ .dominator_sensing_point = SENSING_POINT1,
+ .hw_reboot_trip_point = 117000,
+ .irq_bit = BIT(5),
+ },
+ [6] = {
+ .domain_index = MT8195_AP_DOMAIN,
+ .addr_offset = 0x300,
+ .num_sensor = 2,
+ .sensor_map = {MT8195_TS7_0, MT8195_TS7_1},
+ .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118),
+ .hw_filter = LVTS_FILTER_2_OF_4,
+ .dominator_sensing_point = SENSING_POINT0,
+ .hw_reboot_trip_point = 117000,
+ .irq_bit = BIT(6),
+ }
+};
+
+static struct lvts_data mt8195_lvts_data = {
+ .num_domain = MT8195_NUM_DOMAIN,
+ .num_tc = MT8195_NUM_LVTS,
+ .tc = mt8195_tc_settings,
+ .num_sensor = MT8195_NUM_TS,
+ .ops = {
+ .efuse_to_cal_data = mt8195_efuse_to_cal_data,
+ .device_enable_and_init = device_enable_and_init_v4,
+ .device_enable_auto_rck = device_enable_auto_rck_v4,
+ .device_read_count_rc_n = device_read_count_rc_n_v4,
+ .set_cal_data = set_calibration_data_v4,
+ .init_controller = init_controller_v4,
+ },
+ .feature_bitmap = FEATURE_DEVICE_AUTO_RCK,
+ .num_efuse_addr = 22,
+ .num_efuse_block = 2,
+ .cal_data = {
+ .default_golden_temp = 50,
+ .default_count_r = 35000,
+ .default_count_rc = 2750,
+ },
+ .coeff = {
+ .a = -250460,
+ .b = 250460,
+ },
+};
+
/*==================================================
*==================================================
* Support chips
@@ -1264,6 +1438,10 @@ static const struct of_device_id lvts_of_match[] = {
.compatible = "mediatek,mt6873-lvts",
.data = (void *)&mt6873_lvts_data,
},
+ {
+ .compatible = "mediatek,mt8195-lvts",
+ .data = (void *)&mt8195_lvts_data,
+ },
{
},
};
--
2.31.1
On Mon, Aug 16, 2021 at 06:43:05PM +0200, Alexandre Bailon wrote:
> This patch adds binding document for mt8195 thermal controller.
>
> Signed-off-by: Alexandre Bailon <[email protected]>
> ---
> .../devicetree/bindings/thermal/mediatek-thermal-lvts.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml b/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml
> index 69ffe7b14c212..2e1ae00d4fd18 100644
> --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml
> +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml
> @@ -12,7 +12,11 @@ maintainers:
>
> properties:
> compatible:
> - const: mediatek,mt6873-lvts
> + oneOf:
> + - items:
> + - enum:
> + - mediatek,mt6873-lvts
> + - mediatek,mt8195-lvts
You don't need 'oneOf' when only one clause. Just changing the const to
enum is enough.
Rob