In an attempt to unify u-boot's and linux' device tree for the LS1028A SoC
we first need to clean up some network related stuff. Vladimir suggested to
move the Ethernet PHYs into the MDIO controller node, which is already the
case for u-boot's device tree. Further we unify the use of phy-mode and
phy-connection-type. Both have the same meaning, but phy-mode is used more
often in the kernel and for the ls1028a both were used. Replace
phy-connection-type with phy-mode.
Further move all the nodes which belongs to the CCSR into the /soc node.
These are the Mali display conntroller and its associated pixel clock PLL.
Finally, add the GPU node for the etnaviv driver under /soc.
Michael Walle (7):
arm64: dts: ls1028a: move pixel clock pll into /soc
arm64: dts: ls1028a: move Mali DP500 node into /soc
arm64: dts: ls1028a: add Vivante GPU node
arm64: dts: freescale: fix arm,sp805 compatible string
arm64: dts: ls1028a: disable usb controller by default
arm64: dts: ls1028a: move PHY nodes to MDIO controller
arm64: dts: ls1028a: use phy-mode instead of phy-connection-type
.../fsl-ls1028a-kontron-sl28-var1.dts | 60 ++++++++--------
.../fsl-ls1028a-kontron-sl28-var2.dts | 17 ++---
.../fsl-ls1028a-kontron-sl28-var4.dts | 49 +++++++------
.../freescale/fsl-ls1028a-kontron-sl28.dts | 31 +++++----
.../boot/dts/freescale/fsl-ls1028a-qds.dts | 10 ++-
.../boot/dts/freescale/fsl-ls1028a-rdb.dts | 19 +++---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 68 +++++++++++--------
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++---
9 files changed, 149 insertions(+), 137 deletions(-)
--
2.30.2
Recently, support for this particular Vivante GC7000 GPU was added to the
linux kernel. Add the corresponding device tree node.
Signed-off-by: Michael Walle <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 92e4f004c1c2..876dea668a90 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -814,6 +814,17 @@ dpi0_out: endpoint {
};
};
+ gpu: gpu@f0c0000 {
+ compatible = "vivante,gc";
+ reg = <0x0 0xf0c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>;
+ clock-names = "core", "shader", "bus";
+ #cooling-cells = <2>;
+ };
+
sai1: audio-controller@f100000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
--
2.30.2
Move the PHY nodes from the network controller to the dedicated MDIO
controller. According to Vladimir Oltean direct MDIO access via the PF,
that is when the PHY is put under the "mdio" subnode, is defeatured and
in fact the latest reference manual isn't mentioning it anymore.
Suggested-by: Vladimir Oltean <[email protected]>
Signed-off-by: Michael Walle <[email protected]>
---
.../fsl-ls1028a-kontron-sl28-var1.dts | 58 +++++++++----------
.../fsl-ls1028a-kontron-sl28-var2.dts | 17 ++----
.../fsl-ls1028a-kontron-sl28-var4.dts | 49 ++++++++--------
.../freescale/fsl-ls1028a-kontron-sl28.dts | 21 +++----
.../boot/dts/freescale/fsl-ls1028a-rdb.dts | 12 ++--
5 files changed, 67 insertions(+), 90 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
index e8d31279b7a3..836a9b7d8263 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
@@ -8,7 +8,7 @@
* None of the four SerDes lanes are used by the module, instead they are
* all led out to the carrier for customer use.
*
- * Copyright (C) 2020 Michael Walle <[email protected]>
+ * Copyright (C) 2021 Michael Walle <[email protected]>
*
*/
@@ -21,43 +21,39 @@ / {
compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
};
+&enetc_mdio_pf3 {
+ /* Delete unused phy node */
+ /delete-node/ ethernet-phy@5;
+
+ phy0: ethernet-phy@4 {
+ reg = <0x4>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ qca,clk-out-frequency = <125000000>;
+ qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+ qca,keep-pll-enabled;
+ vddio-supply = <&vddio>;
+
+ vddio: vddio-regulator {
+ regulator-name = "VDDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddh: vddh-regulator {
+ regulator-name = "VDDH";
+ };
+ };
+};
+
&enetc_port0 {
status = "disabled";
- /*
- * Delete both the phy-handle to the old phy0 label as well as
- * the mdio node with the old phy node with the old phy0 label.
- */
+ /* Delete the phy-handle to the old phy0 label */
/delete-property/ phy-handle;
- /delete-node/ mdio;
};
&enetc_port1 {
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy0: ethernet-phy@4 {
- reg = <0x4>;
- eee-broken-1000t;
- eee-broken-100tx;
- qca,clk-out-frequency = <125000000>;
- qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
- qca,keep-pll-enabled;
- vddio-supply = <&vddio>;
-
- vddio: vddio-regulator {
- regulator-name = "VDDIO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddh: vddh-regulator {
- regulator-name = "VDDH";
- };
- };
- };
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
index f6a79c8080d1..330e34f933a3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
@@ -5,7 +5,7 @@
* This is for the network variant 2 which has two ethernet ports. These
* ports are connected to the internal switch.
*
- * Copyright (C) 2020 Michael Walle <[email protected]>
+ * Copyright (C) 2021 Michael Walle <[email protected]>
*
*/
@@ -18,12 +18,6 @@ / {
};
&enetc_mdio_pf3 {
- phy0: ethernet-phy@5 {
- reg = <0x5>;
- eee-broken-1000t;
- eee-broken-100tx;
- };
-
phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
@@ -34,14 +28,11 @@ phy1: ethernet-phy@4 {
&enetc_port0 {
status = "disabled";
/*
- * In the base device tree the PHY was registered in the mdio
- * subnode as it is PHY for this port. On this module this PHY
- * is connected to a switch port instead and registered above.
- * Therefore, delete the mdio subnode as well as the phy-handle
- * property here.
+ * In the base device tree the PHY at address 5 was assigned for
+ * this port. On this module this PHY is connected to a switch
+ * port instead. Therefore, delete the phy-handle property here.
*/
/delete-property/ phy-handle;
- /delete-node/ mdio;
};
&enetc_port2 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
index e65d1c477e2c..77ed0ebd2c75 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
@@ -5,7 +5,7 @@
* This is for the network variant 4 which has two ethernet ports. It
* extends the base and provides one more port connected via RGMII.
*
- * Copyright (C) 2019 Michael Walle <[email protected]>
+ * Copyright (C) 2021 Michael Walle <[email protected]>
*
*/
@@ -18,33 +18,30 @@ / {
compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
};
-&enetc_port1 {
- phy-handle = <&phy1>;
- phy-connection-type = "rgmii-id";
- status = "okay";
+&enetc_mdio_pf3 {
+ phy1: ethernet-phy@4 {
+ reg = <0x4>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ qca,clk-out-frequency = <125000000>;
+ qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+ qca,keep-pll-enabled;
+ vddio-supply = <&vddio>;
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy1: ethernet-phy@4 {
- reg = <0x4>;
- eee-broken-1000t;
- eee-broken-100tx;
- qca,clk-out-frequency = <125000000>;
- qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
- qca,keep-pll-enabled;
- vddio-supply = <&vddio>;
-
- vddio: vddio-regulator {
- regulator-name = "VDDIO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
+ vddio: vddio-regulator {
+ regulator-name = "VDDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
- vddh: vddh-regulator {
- regulator-name = "VDDH";
- };
+ vddh: vddh-regulator {
+ regulator-name = "VDDH";
};
};
};
+
+&enetc_port1 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
index 2c6266991c38..b3e9c499e8b0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
- * Copyright (C) 2019 Michael Walle <[email protected]>
+ * Copyright (C) 2021 Michael Walle <[email protected]>
*
*/
@@ -80,22 +80,19 @@ &duart1 {
status = "okay";
};
+&enetc_mdio_pf3 {
+ phy0: ethernet-phy@5 {
+ reg = <0x5>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ };
+};
+
&enetc_port0 {
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
managed = "in-band-status";
status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy0: ethernet-phy@5 {
- reg = <0x5>;
- eee-broken-1000t;
- eee-broken-100tx;
- };
- };
};
&esdhc {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index b0967b987f8a..ea11b1eb01f8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -197,6 +197,10 @@ &duart1 {
};
&enetc_mdio_pf3 {
+ sgmii_phy0: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
/* VSC8514 QSGMII quad PHY */
qsgmii_phy0: ethernet-phy@10 {
reg = <0x10>;
@@ -220,14 +224,6 @@ &enetc_port0 {
phy-connection-type = "sgmii";
managed = "in-band-status";
status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- sgmii_phy0: ethernet-phy@2 {
- reg = <0x2>;
- };
- };
};
&enetc_port2 {
--
2.30.2
On Tue, Aug 31, 2021 at 03:40:12PM +0200, Michael Walle wrote:
> Move the PHY nodes from the network controller to the dedicated MDIO
> controller. According to Vladimir Oltean direct MDIO access via the PF,
> that is when the PHY is put under the "mdio" subnode, is defeatured and
> in fact the latest reference manual isn't mentioning it anymore.
>
> Suggested-by: Vladimir Oltean <[email protected]>
> Signed-off-by: Michael Walle <[email protected]>
> ---
Reviewed-by: Vladimir Oltean <[email protected]>
On Tue, Aug 31, 2021 at 03:40:06PM +0200, Michael Walle wrote:
> In an attempt to unify u-boot's and linux' device tree for the LS1028A SoC
> we first need to clean up some network related stuff. Vladimir suggested to
> move the Ethernet PHYs into the MDIO controller node, which is already the
> case for u-boot's device tree. Further we unify the use of phy-mode and
> phy-connection-type. Both have the same meaning, but phy-mode is used more
> often in the kernel and for the ls1028a both were used. Replace
> phy-connection-type with phy-mode.
>
> Further move all the nodes which belongs to the CCSR into the /soc node.
> These are the Mali display conntroller and its associated pixel clock PLL.
> Finally, add the GPU node for the etnaviv driver under /soc.
>
> Michael Walle (7):
> arm64: dts: ls1028a: move pixel clock pll into /soc
> arm64: dts: ls1028a: move Mali DP500 node into /soc
> arm64: dts: ls1028a: add Vivante GPU node
> arm64: dts: freescale: fix arm,sp805 compatible string
> arm64: dts: ls1028a: disable usb controller by default
> arm64: dts: ls1028a: move PHY nodes to MDIO controller
> arm64: dts: ls1028a: use phy-mode instead of phy-connection-type
Applied all, except #4 which had been picked up separately.
Shawn