2021-09-02 10:03:56

by Kavyasree Kotagiri

Subject: [PATCH 3/3] dt-bindings: clock: lan966x: Add LAN966X Clock Controller

From: Kavyasree Kotagiri <[email protected]>

This adds the DT bindings documentation for lan966x SoC
generic clock controller.

Signed-off-by: Kavya Sree Kotagiri <[email protected]>
---
.../bindings/clock/microchip,lan966x-gck.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml

diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
new file mode 100644
index 000000000000..0df765f628c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN966X Generic Clock Controller
+
+maintainers:
+ - Kavya Sree Kotagiri <[email protected]>
+
+description: |
+ The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
+ ddr_clk and sys_clk. This clock controller generates and supplies
+ clock to various peripherals within the SoC.
+
+properties:
+ compatible:
+ const: microchip,lan966x-gck
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clks: clock-controller@e00c00a8 {
+ compatible = "microchip,lan966x-gck";
+ #clock-cells = <1>;
+ clocks = <&cpu_clk>;
+ reg = <0xe00c00a8 0x38>;
+ };
+...
--
2.17.1

2021-09-07 20:49:23

by Rob Herring (Arm)

Subject: Re: [PATCH 3/3] dt-bindings: clock: lan966x: Add LAN966X Clock Controller

On Thu, Sep 02, 2021 at 02:59:54PM +0530, [email protected] wrote:
> From: Kavyasree Kotagiri <[email protected]>

Ah, here's the rest. The threading of your series is broken.

>
> This adds the DT bindings documentation for lan966x SoC
> generic clock controller.
>
> Signed-off-by: Kavya Sree Kotagiri <[email protected]>

Please make your author and Sob name and email match.

> ---
> .../bindings/clock/microchip,lan966x-gck.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> new file mode 100644
> index 000000000000..0df765f628c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip LAN966X Generic Clock Controller
> +
> +maintainers:
> + - Kavya Sree Kotagiri <[email protected]>
> +
> +description: |
> + The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
> + ddr_clk and sys_clk. This clock controller generates and supplies
> + clock to various peripherals within the SoC.
> +
> +properties:
> + compatible:
> + const: microchip,lan966x-gck
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clks: clock-controller@e00c00a8 {
> + compatible = "microchip,lan966x-gck";
> + #clock-cells = <1>;
> + clocks = <&cpu_clk>;
> + reg = <0xe00c00a8 0x38>;

Looks like this is part of some other block?

> + };
> +...
> --
> 2.17.1
>
>