Hi All,
This patch series enables ADC and CAN interfaces on RZ/G2L SMARC EVK.
Note: Patches apply on top of [1] + [2]
[1] https://git.kernel.org/pub/scm/linux/kernel/
git/geert/renesas-devel.git/log/?h=renesas-arm-dt-for-v5.16
[2] https://patchwork.kernel.org/project/linux-renesas-soc/
cover/[email protected]/
Cheers,
Prabhakar
Lad Prabhakar (3):
arm64: dts: renesas: rzg2l-smarc-som: Move extal and memory nodes to
SOM DTSI
arm64: dts: renesas: rzg2l-smarc-som: Enable ADC on SMARC platform
arm64: dts: renesas: rzg2l-smarc: Enable CANFD
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 7 +--
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 35 +++++++++++++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 44 +++++++++++++++++--
3 files changed, 76 insertions(+), 10 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
--
2.17.1
Move extal and memory nodes to SOM DTSI.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 7 +------
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 18 ++++++++++++++++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 4 ----
3 files changed, 19 insertions(+), 10 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
index d3f72ec62f03..247b0b3f1b58 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -7,15 +7,10 @@
/dts-v1/;
#include "r9a07g044l2.dtsi"
+#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc.dtsi"
/ {
model = "Renesas SMARC EVK based on r9a07g044l2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
new file mode 100644
index 000000000000..0748f2e7396a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC SOM common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/ {
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 39e05169aaaa..e895f6e7fa28 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -89,10 +89,6 @@
status = "okay";
};
-&extal_clk {
- clock-frequency = <24000000>;
-};
-
&hsusb {
dr_mode = "otg";
status = "okay";
--
2.17.1
Enable CANFD on RZ/G2L SMARC platform.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 40 ++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index e895f6e7fa28..5dc4fff33076 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -80,6 +80,20 @@
clock-frequency = <12288000>;
};
+&canfd {
+ pinctrl-0 = <&can0_pins &can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
&ehci0 {
dr_mode = "otg";
status = "okay";
@@ -139,6 +153,32 @@
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
+ can0_pins: can0 {
+ pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
+ <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
+ };
+
+ /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
+ can0-stb {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "can0_stb";
+ };
+
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
+ <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
+ };
+
+ /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
+ can1-stb {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "can1_stb";
+ };
+
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
--
2.17.1
On Wed, Sep 22, 2021 at 11:21 PM Lad Prabhakar
<[email protected]> wrote:
> Move extal and memory nodes to SOM DTSI.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.16.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
On Wed, Sep 22, 2021 at 11:21 PM Lad Prabhakar
<[email protected]> wrote:
> Enable CANFD on RZ/G2L SMARC platform.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> @@ -139,6 +153,32 @@
> pinctrl-0 = <&sound_clk_pins>;
> pinctrl-names = "default";
>
> + can0_pins: can0 {
> + pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
> + <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
> + };
> +
> + /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
> + can0-stb {
> + gpio-hog;
> + gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
> + output-high;
While this drives the STB signal correctly, I find it confusing.
According to the datasheet, the STB signal is active-high, so it has to
be pulled low to disable standby.
So to reflect the meaning of the STB line, I would write:
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
output-low;
> + line-name = "can0_stb";
> + };
> +
> + can1_pins: can1 {
> + pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
> + <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
> + };
> +
> + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
> + can1-stb {
> + gpio-hog;
> + gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_LOW>;
> + output-high;
Likewise.
> + line-name = "can1_stb";
> + };
> +
The rest looks good to me, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Fri, Sep 24, 2021 at 10:07 AM Geert Uytterhoeven
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Wed, Sep 22, 2021 at 11:21 PM Lad Prabhakar
> <[email protected]> wrote:
> > Enable CANFD on RZ/G2L SMARC platform.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Biju Das <[email protected]>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> > @@ -139,6 +153,32 @@
> > pinctrl-0 = <&sound_clk_pins>;
> > pinctrl-names = "default";
> >
> > + can0_pins: can0 {
> > + pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
> > + <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
> > + };
> > +
> > + /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
> > + can0-stb {
> > + gpio-hog;
> > + gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
> > + output-high;
>
> While this drives the STB signal correctly, I find it confusing.
> According to the datasheet, the STB signal is active-high, so it has to
> be pulled low to disable standby.
agreed.
> So to reflect the meaning of the STB line, I would write:
>
> gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
> output-low;
>
will re-spin the patch 3/3 as above.
Cheers,
Prabhakar
> > + line-name = "can0_stb";
> > + };
> > +
> > + can1_pins: can1 {
> > + pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
> > + <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
> > + };
> > +
> > + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
> > + can1-stb {
> > + gpio-hog;
> > + gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_LOW>;
> > + output-high;
>
> Likewise.
>
> > + line-name = "can1_stb";
> > + };
> > +
>
> The rest looks good to me, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <[email protected]>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds