This patch enables general support for Intel defined PCIe VSEC and DVSEC
capabilities in the Intel Platform Monitoring Technology (PMT) driver.
Though the driver was written exclusively for PMT capabilities, newer DVSEC
and VSEC IDs for other capabilities can exist on the same device requiring
that the driver handle them.
V3 is mostly a resend of V2. It drops a platform/x86 patch that was picked
up separately by Hans in the last cycle. It also adds a new patch to
support an upcoming capability.
David E. Box (5):
PCI: Add #defines for accessing PCIE DVSEC fields
MFD: intel_pmt: Support non-PMT capabilities
MFD: intel_pmt: Add support for PCIe VSEC structures
MFD: intel_pmt: Add DG2 support
MFD: intel_extended_cap: Add support for Intel SDSi
drivers/mfd/intel_pmt.c | 258 +++++++++++++++------
drivers/platform/x86/intel/pmt/class.c | 2 +
drivers/platform/x86/intel/pmt/crashlog.c | 2 +-
drivers/platform/x86/intel/pmt/telemetry.c | 2 +-
include/uapi/linux/pci_regs.h | 4 +
5 files changed, 191 insertions(+), 77 deletions(-)
--
2.25.1
Add Platform Monitoring Technology support for DG2 platforms.
Signed-off-by: David E. Box <[email protected]>
---
V3: No change
V2: New patch
drivers/mfd/intel_pmt.c | 9 +++++++++
drivers/platform/x86/intel/pmt/class.c | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/mfd/intel_pmt.c b/drivers/mfd/intel_pmt.c
index 08e07b31aeec..a6fe50f65479 100644
--- a/drivers/mfd/intel_pmt.c
+++ b/drivers/mfd/intel_pmt.c
@@ -94,6 +94,11 @@ static const struct pmt_platform_info dg1_info = {
.capabilities = dg1_capabilities,
};
+/* DG2 Platform */
+static const struct pmt_platform_info dg2_info = {
+ .quirks = PMT_QUIRK_TABLE_SHIFT
+};
+
static bool intel_ext_cap_allowed(u16 id)
{
int i;
@@ -334,11 +339,15 @@ static void pmt_pci_remove(struct pci_dev *pdev)
#define PCI_DEVICE_ID_INTEL_PMT_ADL 0x467d
#define PCI_DEVICE_ID_INTEL_PMT_DG1 0x490e
+#define PCI_DEVICE_ID_INTEL_PMT_DG2_G10 0x4f93
+#define PCI_DEVICE_ID_INTEL_PMT_DG2_G11 0x4f95
#define PCI_DEVICE_ID_INTEL_PMT_OOBMSM 0x09a7
#define PCI_DEVICE_ID_INTEL_PMT_TGL 0x9a0d
static const struct pci_device_id pmt_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, PMT_ADL, &tgl_info) },
{ PCI_DEVICE_DATA(INTEL, PMT_DG1, &dg1_info) },
+ { PCI_DEVICE_DATA(INTEL, PMT_DG2_G10, &dg2_info) },
+ { PCI_DEVICE_DATA(INTEL, PMT_DG2_G11, &dg2_info) },
{ PCI_DEVICE_DATA(INTEL, PMT_OOBMSM, NULL) },
{ PCI_DEVICE_DATA(INTEL, PMT_TGL, &tgl_info) },
{ }
diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c
index 659b1073033c..f2a8e19a02e7 100644
--- a/drivers/platform/x86/intel/pmt/class.c
+++ b/drivers/platform/x86/intel/pmt/class.c
@@ -29,6 +29,8 @@
static const struct pci_device_id pmt_telem_early_client_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x467d) }, /* ADL */
{ PCI_VDEVICE(INTEL, 0x490e) }, /* DG1 */
+ { PCI_VDEVICE(INTEL, 0x4f93) }, /* DG2_G10 */
+ { PCI_VDEVICE(INTEL, 0x4f95) }, /* DG2_G11 */
{ PCI_VDEVICE(INTEL, 0x9a0d) }, /* TGL */
{ }
};
--
2.25.1
Add #defines for accessing Vendor ID, Revision, Length, and ID offsets
in the Designated Vendor Specific Extended Capability (DVSEC). Defined
in PCIe r5.0, sec 7.9.6.
Signed-off-by: David E. Box <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
---
v3: No change
include/uapi/linux/pci_regs.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e709ae8235e7..57ee51f19283 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1080,7 +1080,11 @@
/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
#define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
+#define PCI_DVSEC_HEADER1_VID(x) ((x) & 0xffff)
+#define PCI_DVSEC_HEADER1_REV(x) (((x) >> 16) & 0xf)
+#define PCI_DVSEC_HEADER1_LEN(x) (((x) >> 20) & 0xfff)
#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
+#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff)
/* Data Link Feature */
#define PCI_DLF_CAP 0x04 /* Capabilities Register */
--
2.25.1
Hi,
On 9/22/21 11:30 PM, David E. Box wrote:
> This patch enables general support for Intel defined PCIe VSEC and DVSEC
> capabilities in the Intel Platform Monitoring Technology (PMT) driver.
> Though the driver was written exclusively for PMT capabilities, newer DVSEC
> and VSEC IDs for other capabilities can exist on the same device requiring
> that the driver handle them.
>
> V3 is mostly a resend of V2. It drops a platform/x86 patch that was picked
> up separately by Hans in the last cycle. It also adds a new patch to
> support an upcoming capability.
>
> David E. Box (5):
> PCI: Add #defines for accessing PCIE DVSEC fields
> MFD: intel_pmt: Support non-PMT capabilities
> MFD: intel_pmt: Add support for PCIe VSEC structures
> MFD: intel_pmt: Add DG2 support
> MFD: intel_extended_cap: Add support for Intel SDSi
Since this mostly touches drivers/mfd/intel_pmt.c, I assume this is
going to get merged through the MFD trees.
For the few small drivers/platform/x86 changes:
Acked-by: Hans de Goede <[email protected]>
Regards,
Hans
>
> drivers/mfd/intel_pmt.c | 258 +++++++++++++++------
> drivers/platform/x86/intel/pmt/class.c | 2 +
> drivers/platform/x86/intel/pmt/crashlog.c | 2 +-
> drivers/platform/x86/intel/pmt/telemetry.c | 2 +-
> include/uapi/linux/pci_regs.h | 4 +
> 5 files changed, 191 insertions(+), 77 deletions(-)
>
On Thu, 2021-09-23 at 11:04 +0200, Hans de Goede wrote:
> Hi,
>
> On 9/22/21 11:30 PM, David E. Box wrote:
> > This patch enables general support for Intel defined PCIe VSEC and DVSEC
> > capabilities in the Intel Platform Monitoring Technology (PMT) driver.
> > Though the driver was written exclusively for PMT capabilities, newer DVSEC
> > and VSEC IDs for other capabilities can exist on the same device requiring
> > that the driver handle them.
> >
> > V3 is mostly a resend of V2. It drops a platform/x86 patch that was picked
> > up separately by Hans in the last cycle. It also adds a new patch to
> > support an upcoming capability.
> >
> > David E. Box (5):
> > PCI: Add #defines for accessing PCIE DVSEC fields
> > MFD: intel_pmt: Support non-PMT capabilities
> > MFD: intel_pmt: Add support for PCIe VSEC structures
> > MFD: intel_pmt: Add DG2 support
> > MFD: intel_extended_cap: Add support for Intel SDSi
>
> Since this mostly touches drivers/mfd/intel_pmt.c, I assume this is
> going to get merged through the MFD trees.
Yes. Thanks.
>
> For the few small drivers/platform/x86 changes:
>
> Acked-by: Hans de Goede <[email protected]>
>
> Regards,
>
> Hans
>
>
>
>
>
> >
> > drivers/mfd/intel_pmt.c | 258 +++++++++++++++------
> > drivers/platform/x86/intel/pmt/class.c | 2 +
> > drivers/platform/x86/intel/pmt/crashlog.c | 2 +-
> > drivers/platform/x86/intel/pmt/telemetry.c | 2 +-
> > include/uapi/linux/pci_regs.h | 4 +
> > 5 files changed, 191 insertions(+), 77 deletions(-)
> >
>
If you repost this for any reason, update the subject to:
s/PCIE/PCIe/
So it matches the commit log and other usage in drivers/pci/
On Wed, Sep 22, 2021 at 02:30:03PM -0700, David E. Box wrote:
> Add #defines for accessing Vendor ID, Revision, Length, and ID offsets
> in the Designated Vendor Specific Extended Capability (DVSEC). Defined
> in PCIe r5.0, sec 7.9.6.
>
> Signed-off-by: David E. Box <[email protected]>
> Acked-by: Bjorn Helgaas <[email protected]>
> ---
>
> v3: No change
>
> include/uapi/linux/pci_regs.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index e709ae8235e7..57ee51f19283 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1080,7 +1080,11 @@
>
> /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
> #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
> +#define PCI_DVSEC_HEADER1_VID(x) ((x) & 0xffff)
> +#define PCI_DVSEC_HEADER1_REV(x) (((x) >> 16) & 0xf)
> +#define PCI_DVSEC_HEADER1_LEN(x) (((x) >> 20) & 0xfff)
> #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
> +#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff)
>
> /* Data Link Feature */
> #define PCI_DLF_CAP 0x04 /* Capabilities Register */
> --
> 2.25.1
>