Hi All,
This patch series adds a couple of fixes for rpc-if driver and
adds support for RZ/G2L SoC, where the SPI Multi I/O Bus Controller
is identical to the RPC-IF block found on R-Car Gen3 SoC's.
Note: patch applies on top of [1].
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
[email protected]/
Cheers,
Prabhakar
Lad Prabhakar (6):
dt-bindings: memory: renesas,rpc-if: Add support for the R9A07G044
dt-bindings: memory: renesas,rpc-if: Add optional interrupts property
spi: spi-rpc-if: Check return value of rpcif_sw_init()
mtd: hyperbus: rpc-if: Check return value of rpcif_sw_init()
memory: renesas-rpc-if: Drop usage of RPCIF_DIRMAP_SIZE macro
memory: renesas-rpc-if: Add support for RZ/G2L
.../memory-controllers/renesas,rpc-if.yaml | 52 +++++++++----
drivers/memory/renesas-rpc-if.c | 73 +++++++++++++++----
drivers/mtd/hyperbus/rpc-if.c | 8 +-
drivers/spi/spi-rpc-if.c | 8 +-
include/memory/renesas-rpc-if.h | 8 +-
5 files changed, 116 insertions(+), 33 deletions(-)
--
2.17.1
RPCIF_DIRMAP_SIZE may differ on various SoC's. Instead of using
RPCIF_DIRMAP_SIZE macro use resource size to get dirmap size
which is already part of struct rpcif.
Also make sure we return error in case devm_ioremap_resource()
fails for dirmap.
Fixes: ca7d8b980b67 ("memory: add Renesas RPC-IF driver")
Fixes: 59e27d7c94aa ("memory: renesas-rpc-if: fix possible NULL pointer dereference of resource")
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
drivers/memory/renesas-rpc-if.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 77a011d5ff8c..140cb4e2b789 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -147,8 +147,6 @@
#define RPCIF_PHYINT 0x0088 /* R/W */
#define RPCIF_PHYINT_WPVAL BIT(1)
-#define RPCIF_DIRMAP_SIZE 0x4000000
-
static const struct regmap_range rpcif_volatile_ranges[] = {
regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
@@ -244,7 +242,7 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(rpc->dirmap))
- rpc->dirmap = NULL;
+ return PTR_ERR(rpc->dirmap);
rpc->size = resource_size(res);
rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
@@ -547,8 +545,8 @@ EXPORT_SYMBOL(rpcif_manual_xfer);
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
{
- loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
- size_t size = RPCIF_DIRMAP_SIZE - from;
+ loff_t from = offs & (rpc->size - 1);
+ size_t size = rpc->size - from;
if (len > size)
len = size;
--
2.17.1
For completeness add optional interrupts property.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
.../devicetree/bindings/memory-controllers/renesas,rpc-if.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
index 105b5157989b..fd1ecbb6c94d 100644
--- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
@@ -55,6 +55,9 @@ properties:
clocks: true
+ interrupts:
+ maxItems: 1
+
power-domains:
maxItems: 1
--
2.17.1
rpcif_sw_init() can fail so make sure we check the return value
of it and on error exit rpcif_hb_probe() callback with error code.
Fixes: 5de15b610f78 ("mtd: hyperbus: add Renesas RPC-IF driver")
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
drivers/mtd/hyperbus/rpc-if.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/hyperbus/rpc-if.c b/drivers/mtd/hyperbus/rpc-if.c
index ecb050ba95cd..367b0d72bf62 100644
--- a/drivers/mtd/hyperbus/rpc-if.c
+++ b/drivers/mtd/hyperbus/rpc-if.c
@@ -124,7 +124,9 @@ static int rpcif_hb_probe(struct platform_device *pdev)
if (!hyperbus)
return -ENOMEM;
- rpcif_sw_init(&hyperbus->rpc, pdev->dev.parent);
+ error = rpcif_sw_init(&hyperbus->rpc, pdev->dev.parent);
+ if (error)
+ return error;
platform_set_drvdata(pdev, hyperbus);
--
2.17.1
SPI Multi I/O Bus Controller on RZ/G2L SoC is almost identical to
the RPC-IF interface found on R-Car Gen3 SoC's.
This patch adds a new compatible string to identify the RZ/G2L family
so that the timing values on RZ/G2L can be adjusted.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
.../memory-controllers/renesas,rpc-if.yaml | 51 ++++++++++++++-----
1 file changed, 37 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
index d25072c414e4..105b5157989b 100644
--- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
@@ -24,16 +24,22 @@ allOf:
properties:
compatible:
- items:
- - enum:
- - renesas,r8a774a1-rpc-if # RZ/G2M
- - renesas,r8a774b1-rpc-if # RZ/G2N
- - renesas,r8a774c0-rpc-if # RZ/G2E
- - renesas,r8a774e1-rpc-if # RZ/G2H
- - renesas,r8a77970-rpc-if # R-Car V3M
- - renesas,r8a77980-rpc-if # R-Car V3H
- - renesas,r8a77995-rpc-if # R-Car D3
- - const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2 device
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r8a774a1-rpc-if # RZ/G2M
+ - renesas,r8a774b1-rpc-if # RZ/G2N
+ - renesas,r8a774c0-rpc-if # RZ/G2E
+ - renesas,r8a774e1-rpc-if # RZ/G2H
+ - renesas,r8a77970-rpc-if # R-Car V3M
+ - renesas,r8a77980-rpc-if # R-Car V3H
+ - renesas,r8a77995-rpc-if # R-Car D3
+ - const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2{E,H,M,N} device
+
+ - items:
+ - enum:
+ - renesas,r9a07g044-rpc-if # RZ/G2{L,LC}
+ - const: renesas,rzg2l-rpc-if # RZ/G2L family
reg:
items:
@@ -47,8 +53,7 @@ properties:
- const: dirmap
- const: wbuf
- clocks:
- maxItems: 1
+ clocks: true
power-domains:
maxItems: 1
@@ -66,8 +71,6 @@ patternProperties:
- cfi-flash
- jedec,spi-nor
-unevaluatedProperties: false
-
required:
- compatible
- reg
@@ -78,6 +81,26 @@ required:
- '#address-cells'
- '#size-cells'
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rzg2l-rpc-if
+then:
+ properties:
+ clocks:
+ items:
+ - description: SPI Multi IO Register access clock (SPI_CLK2)
+ - description: SPI Multi IO Main clock (SPI_CLK).
+
+else:
+ properties:
+ clocks:
+ maxItems: 1
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/clock/renesas-cpg-mssr.h>
--
2.17.1
SPI Multi I/O Bus Controller on RZ/G2L SoC is almost identical to
the RPC-IF interface found on R-Car Gen3 SoC's.
This patch adds a new compatible string for the RZ/G2L family so
that the timing values on RZ/G2L can be adjusted.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
drivers/memory/renesas-rpc-if.c | 65 ++++++++++++++++++++++++++++-----
drivers/mtd/hyperbus/rpc-if.c | 4 +-
drivers/spi/spi-rpc-if.c | 4 +-
include/memory/renesas-rpc-if.h | 8 +++-
4 files changed, 68 insertions(+), 13 deletions(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 140cb4e2b789..47dce166b328 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -12,6 +12,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
@@ -24,14 +25,14 @@
#define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
#define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
#define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
-#define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \
- RPCIF_CMNCR_MOIIO1(3) | \
- RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
+#define RPCIF_CMNCR_MOIIO_HIZ(val) (RPCIF_CMNCR_MOIIO0(val) | \
+ RPCIF_CMNCR_MOIIO1(val) | \
+ RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
#define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
-#define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
- RPCIF_CMNCR_IO3FV(3))
+#define RPCIF_CMNCR_IOFV_HIZ(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
+ RPCIF_CMNCR_IO3FV(val))
#define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
#define RPCIF_SSLDR 0x0004 /* R/W */
@@ -126,6 +127,9 @@
#define RPCIF_SMDRENR_OPDRE BIT(4)
#define RPCIF_SMDRENR_SPIDRE BIT(0)
+#define RPCIF_PHYADJ1 0x0070 /* R/W */
+#define RPCIF_PHYADJ2 0x0074 /* R/W */
+
#define RPCIF_PHYCNT 0x007C /* R/W */
#define RPCIF_PHYCNT_CAL BIT(31)
#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
@@ -133,10 +137,12 @@
#define RPCIF_PHYCNT_OCT BIT(20)
#define RPCIF_PHYCNT_DDRCAL BIT(19)
#define RPCIF_PHYCNT_HS BIT(18)
+#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16)
#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
#define RPCIF_PHYCNT_WBUF2 BIT(4)
#define RPCIF_PHYCNT_WBUF BIT(2)
#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
+#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
@@ -245,18 +251,46 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
return PTR_ERR(rpc->dirmap);
rpc->size = resource_size(res);
+ rpc->type = (enum rpcif_type)of_device_get_match_data(dev);
rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
return PTR_ERR_OR_ZERO(rpc->rstc);
}
EXPORT_SYMBOL(rpcif_sw_init);
-void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
+static void rpcif_timing_adjust_sdr(struct rpcif *rpc)
+{
+ u32 data;
+
+ regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0xA5390000);
+ regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000000);
+ regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00008080);
+ regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000022);
+ regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00008080);
+ regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000024);
+
+ regmap_read(rpc->regmap, RPCIF_PHYCNT, &data);
+ regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3));
+ regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00000030);
+ regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000032);
+}
+
+int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
{
u32 dummy;
pm_runtime_get_sync(rpc->dev);
+ if (rpc->type == RPCIF_RZ_G2L) {
+ int ret;
+
+ ret = reset_control_reset(rpc->rstc);
+ if (ret)
+ return ret;
+ usleep_range(200, 300);
+ rpcif_timing_adjust_sdr(rpc);
+ }
+
/*
* NOTE: The 0x260 are undocumented bits, but they must be set.
* RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
@@ -265,8 +299,15 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
* On H3 ES1.x, the value should be 0, while on others,
* the value should be 7.
*/
- regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
- RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
+ if (rpc->type == RPCIF_RCAR_GEN3) {
+ regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
+ RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
+ } else {
+ regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy);
+ dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK;
+ dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260;
+ regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy);
+ }
/*
* NOTE: The 0x1511144 are undocumented bits, but they must be set
@@ -284,7 +325,8 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
RPCIF_PHYINT_WPVAL, 0);
regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
- RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
+ RPCIF_CMNCR_MOIIO_HIZ(rpc->type == RPCIF_RZ_G2L ? 1 : 3) |
+ RPCIF_CMNCR_IOFV_HIZ(rpc->type == RPCIF_RZ_G2L ? 2 : 3) |
RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
/* Set RCF after BSZ update */
regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
@@ -296,6 +338,8 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
pm_runtime_put(rpc->dev);
rpc->bus_size = hyperflash ? 2 : 1;
+
+ return 0;
}
EXPORT_SYMBOL(rpcif_hw_init);
@@ -613,7 +657,8 @@ static int rpcif_remove(struct platform_device *pdev)
}
static const struct of_device_id rpcif_of_match[] = {
- { .compatible = "renesas,rcar-gen3-rpc-if", },
+ { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 },
+ { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L },
{},
};
MODULE_DEVICE_TABLE(of, rpcif_of_match);
diff --git a/drivers/mtd/hyperbus/rpc-if.c b/drivers/mtd/hyperbus/rpc-if.c
index 367b0d72bf62..40bca89268c3 100644
--- a/drivers/mtd/hyperbus/rpc-if.c
+++ b/drivers/mtd/hyperbus/rpc-if.c
@@ -132,7 +132,9 @@ static int rpcif_hb_probe(struct platform_device *pdev)
rpcif_enable_rpm(&hyperbus->rpc);
- rpcif_hw_init(&hyperbus->rpc, true);
+ error = rpcif_hw_init(&hyperbus->rpc, true);
+ if (error)
+ return error;
hyperbus->hbdev.map.size = hyperbus->rpc.size;
hyperbus->hbdev.map.virt = hyperbus->rpc.dirmap;
diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c
index 83796a4ead34..fe82f3575df4 100644
--- a/drivers/spi/spi-rpc-if.c
+++ b/drivers/spi/spi-rpc-if.c
@@ -156,7 +156,9 @@ static int rpcif_spi_probe(struct platform_device *pdev)
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_QUAD | SPI_RX_QUAD;
ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
- rpcif_hw_init(rpc, false);
+ error = rpcif_hw_init(rpc, false);
+ if (error)
+ return error;
error = spi_register_controller(ctlr);
if (error) {
diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h
index 77c694a19149..7c93f5177532 100644
--- a/include/memory/renesas-rpc-if.h
+++ b/include/memory/renesas-rpc-if.h
@@ -57,6 +57,11 @@ struct rpcif_op {
} data;
};
+enum rpcif_type {
+ RPCIF_RCAR_GEN3,
+ RPCIF_RZ_G2L,
+};
+
struct rpcif {
struct device *dev;
void __iomem *base;
@@ -64,6 +69,7 @@ struct rpcif {
struct regmap *regmap;
struct reset_control *rstc;
size_t size;
+ enum rpcif_type type;
enum rpcif_data_dir dir;
u8 bus_size;
void *buffer;
@@ -78,7 +84,7 @@ struct rpcif {
};
int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
-void rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
+int rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
size_t *len);
int rpcif_manual_xfer(struct rpcif *rpc);
--
2.17.1
rpcif_sw_init() can fail so make sure we check the return value
of it and on error exit rpcif_spi_probe() callback with error code.
Fixes: eb8d6d464a27 ("spi: add Renesas RPC-IF driver")
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
drivers/spi/spi-rpc-if.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c
index c53138ce0030..83796a4ead34 100644
--- a/drivers/spi/spi-rpc-if.c
+++ b/drivers/spi/spi-rpc-if.c
@@ -139,7 +139,9 @@ static int rpcif_spi_probe(struct platform_device *pdev)
return -ENOMEM;
rpc = spi_controller_get_devdata(ctlr);
- rpcif_sw_init(rpc, parent);
+ error = rpcif_sw_init(rpc, parent);
+ if (error)
+ return error;
platform_set_drvdata(pdev, ctlr);
--
2.17.1
On Tue, Sep 28, 2021 at 03:07:18PM +0100, Lad Prabhakar wrote:
> rpcif_sw_init() can fail so make sure we check the return value
> of it and on error exit rpcif_spi_probe() callback with error code.
>
> Fixes: eb8d6d464a27 ("spi: add Renesas RPC-IF driver")
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
If it fails, we should really bail out.
Reviewed-by: Wolfram Sang <[email protected]>
On Tue, Sep 28, 2021 at 03:07:17PM +0100, Lad Prabhakar wrote:
> For completeness add optional interrupts property.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
On Tue, Sep 28, 2021 at 03:07:20PM +0100, Lad Prabhakar wrote:
> RPCIF_DIRMAP_SIZE may differ on various SoC's. Instead of using
> RPCIF_DIRMAP_SIZE macro use resource size to get dirmap size
> which is already part of struct rpcif.
>
> Also make sure we return error in case devm_ioremap_resource()
> fails for dirmap.
>
> Fixes: ca7d8b980b67 ("memory: add Renesas RPC-IF driver")
> Fixes: 59e27d7c94aa ("memory: renesas-rpc-if: fix possible NULL pointer dereference of resource")
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
In general, all fine. I just think this should be split into two
patches:
> @@ -147,8 +147,6 @@
> #define RPCIF_PHYINT 0x0088 /* R/W */
> #define RPCIF_PHYINT_WPVAL BIT(1)
>
> -#define RPCIF_DIRMAP_SIZE 0x4000000
> -
> static const struct regmap_range rpcif_volatile_ranges[] = {
> regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
> regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
> @@ -547,8 +545,8 @@ EXPORT_SYMBOL(rpcif_manual_xfer);
>
> ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
> {
> - loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
> - size_t size = RPCIF_DIRMAP_SIZE - from;
> + loff_t from = offs & (rpc->size - 1);
> + size_t size = rpc->size - from;
>
> if (len > size)
> len = size;
This is the second patch to split which fixes ca7d8b980b67.
> @@ -244,7 +242,7 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
> rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(rpc->dirmap))
> - rpc->dirmap = NULL;
> + return PTR_ERR(rpc->dirmap);
> rpc->size = resource_size(res);
>
> rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
This is the first patch to split which fixes 59e27d7c94aa.
Makes sense?
If you agree, you can add my tag already to the new patches:
Reviewed-by: Wolfram Sang <[email protected]>
On Tue, Sep 28, 2021 at 03:07:19PM +0100, Lad Prabhakar wrote:
> rpcif_sw_init() can fail so make sure we check the return value
> of it and on error exit rpcif_hb_probe() callback with error code.
>
> Fixes: 5de15b610f78 ("mtd: hyperbus: add Renesas RPC-IF driver")
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Hi Wolfram,
Thank you for the review.
On Thu, Sep 30, 2021 at 2:55 PM Wolfram Sang
<[email protected]> wrote:
>
> On Tue, Sep 28, 2021 at 03:07:20PM +0100, Lad Prabhakar wrote:
> > RPCIF_DIRMAP_SIZE may differ on various SoC's. Instead of using
> > RPCIF_DIRMAP_SIZE macro use resource size to get dirmap size
> > which is already part of struct rpcif.
> >
> > Also make sure we return error in case devm_ioremap_resource()
> > fails for dirmap.
> >
> > Fixes: ca7d8b980b67 ("memory: add Renesas RPC-IF driver")
> > Fixes: 59e27d7c94aa ("memory: renesas-rpc-if: fix possible NULL pointer dereference of resource")
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Biju Das <[email protected]>
>
> In general, all fine. I just think this should be split into two
> patches:
>
Sure will split this into two.
> > @@ -147,8 +147,6 @@
> > #define RPCIF_PHYINT 0x0088 /* R/W */
> > #define RPCIF_PHYINT_WPVAL BIT(1)
> >
> > -#define RPCIF_DIRMAP_SIZE 0x4000000
> > -
> > static const struct regmap_range rpcif_volatile_ranges[] = {
> > regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
> > regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
> > @@ -547,8 +545,8 @@ EXPORT_SYMBOL(rpcif_manual_xfer);
> >
> > ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
> > {
> > - loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
> > - size_t size = RPCIF_DIRMAP_SIZE - from;
> > + loff_t from = offs & (rpc->size - 1);
> > + size_t size = rpc->size - from;
> >
> > if (len > size)
> > len = size;
>
> This is the second patch to split which fixes ca7d8b980b67.
>
Will split this change into a second patch but wont add a fixes tag see below..
>
> > @@ -244,7 +242,7 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
> > res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
> > rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
> > if (IS_ERR(rpc->dirmap))
> > - rpc->dirmap = NULL;
> > + return PTR_ERR(rpc->dirmap);
> > rpc->size = resource_size(res);
> >
> > rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
>
> This is the first patch to split which fixes 59e27d7c94aa.
>
> Makes sense?
>
Both the fixes would apply to the first patch itself i.e. when
resource_size was added in ca7d8b980b67 and later in 59e27d7c94aa
resource_size was moved online below (this would cause kernel panic
res is NULL). Do you agree?
> If you agree, you can add my tag already to the new patches:
>
> Reviewed-by: Wolfram Sang <[email protected]>
>
Sure will add your RB tag.
Cheers,
Prabhakar
Hi,
> #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
> #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
> #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
> -#define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
> - RPCIF_CMNCR_IO3FV(3))
> +#define RPCIF_CMNCR_IOFV_HIZ(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
> + RPCIF_CMNCR_IO3FV(val))
Is RPCIF_CMNCR_IO3FV and RPCIF_CMNCR_IO2FV actually documented in your
datasheets? I am asking because I have a patch pending to remove writing
to undocumented locations. So, I was aboout to remove the IO3FV and
IO2FV macros.
> +#define RPCIF_PHYADJ1 0x0070 /* R/W */
> +#define RPCIF_PHYADJ2 0x0074 /* R/W */
Those are named 'PHYADD' and 'PHYWR' in the Gen3 documentation. They are
only available on a few of the Gen3 SoCs. I think the Gen3 namings make
more sense because then it becomes easily understandable that the
registers are used to write something to the PHY.
> +#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16)
We should add a comment here that these bits are only valid for G2L...
> #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
and these only for Gen3.
> +static void rpcif_timing_adjust_sdr(struct rpcif *rpc)
> +{
> + u32 data;
> +
> + regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0xA5390000);
> + regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000000);
> + regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00008080);
> + regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000022);
> + regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00008080);
> + regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000024);
Can't we have defines for these magic values? At least in my latest Gen3
documentation, these values are explained.
> +
> + regmap_read(rpc->regmap, RPCIF_PHYCNT, &data);
> + regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3));
regmap_update_bits?
> + if (rpc->type == RPCIF_RCAR_GEN3) {
> + regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
> + RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
> + } else {
> + regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy);
> + dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK;
> + dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260;
> + regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy);
regmap_update_bits?
Rest looks good.
Thanks and happy hacking!
Wolfram
> Both the fixes would apply to the first patch itself i.e. when
> resource_size was added in ca7d8b980b67 and later in 59e27d7c94aa
> resource_size was moved online below (this would cause kernel panic
> res is NULL). Do you agree?
Yes. I do wonder a little if we need the Fixes tag for ca7d8b980b67
because we fix 59e27d7c94aa which already fixes ca7d8b980b67, so there
is a chain. But maybe redundancy doesn't hurt here. I don't mind.
> This patch series adds a couple of fixes for rpc-if driver and
> adds support for RZ/G2L SoC, where the SPI Multi I/O Bus Controller
> is identical to the RPC-IF block found on R-Car Gen3 SoC's.
I did some basic testing on the Falcon board with a Renesas R-Car V3U
SoC and did not find a regression, so:
Tested-by: Wolfram Sang <[email protected]>
Hi Wolfram,
Thank you for the review.
On Thu, Sep 30, 2021 at 3:40 PM Wolfram Sang
<[email protected]> wrote:
>
> Hi,
>
> > #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
> > #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
> > #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
> > -#define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
> > - RPCIF_CMNCR_IO3FV(3))
> > +#define RPCIF_CMNCR_IOFV_HIZ(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
> > + RPCIF_CMNCR_IO3FV(val))
>
> Is RPCIF_CMNCR_IO3FV and RPCIF_CMNCR_IO2FV actually documented in your
> datasheets? I am asking because I have a patch pending to remove writing
> to undocumented locations. So, I was aboout to remove the IO3FV and
> IO2FV macros.
>
Yes they are documented, you should be able to download the HW manual from [1]
> > +#define RPCIF_PHYADJ1 0x0070 /* R/W */
> > +#define RPCIF_PHYADJ2 0x0074 /* R/W */
>
> Those are named 'PHYADD' and 'PHYWR' in the Gen3 documentation. They are
> only available on a few of the Gen3 SoCs. I think the Gen3 namings make
> more sense because then it becomes easily understandable that the
> registers are used to write something to the PHY.
>
Agreed, will re-name it as per Gen3.
> > +#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16)
>
> We should add a comment here that these bits are only valid for G2L...
>
Will do.
> > #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
>
> and these only for Gen3.
>
ditto.
>
> > +static void rpcif_timing_adjust_sdr(struct rpcif *rpc)
> > +{
> > + u32 data;
> > +
> > + regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0xA5390000);
> > + regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000000);
> > + regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00008080);
> > + regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000022);
> > + regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00008080);
> > + regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000024);
>
> Can't we have defines for these magic values? At least in my latest Gen3
> documentation, these values are explained.
>
RZ/G2L manual doesn't explain these bits. Let me refer to R-Car Gen3
and define them as macros.
> > +
> > + regmap_read(rpc->regmap, RPCIF_PHYCNT, &data);
> > + regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3));
>
> regmap_update_bits?
>
will do.
> > + if (rpc->type == RPCIF_RCAR_GEN3) {
> > + regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
> > + RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
> > + } else {
> > + regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy);
> > + dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK;
> > + dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260;
> > + regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy);
>
> regmap_update_bits?
>
Im a bit hesitant to use regmap_update_bits() here as some of the bits
are not documented.
[1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-arm-based-high-end-32-64-bit-mpus/rzg2l-general-purpose-microprocessors-dual-core-arm-cortex-a55-12-ghz-cpus-3d-graphics-and-video-codec
Cheers,
Prabhakar
> Rest looks good.
>
> Thanks and happy hacking!
>
> Wolfram
>
Hi Prabhakar,
> > Is RPCIF_CMNCR_IO3FV and RPCIF_CMNCR_IO2FV actually documented in your
> > datasheets? I am asking because I have a patch pending to remove writing
> > to undocumented locations. So, I was aboout to remove the IO3FV and
> > IO2FV macros.
> >
> Yes they are documented, you should be able to download the HW manual from [1]
Great, then I will keep them!
> > > + regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00008080);
> > > + regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000024);
> >
> > Can't we have defines for these magic values? At least in my latest Gen3
> > documentation, these values are explained.
> >
> RZ/G2L manual doesn't explain these bits. Let me refer to R-Car Gen3
> and define them as macros.
Seems like we have the best of both worlds then with the documentation
;)
> > > + if (rpc->type == RPCIF_RCAR_GEN3) {
> > > + regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
> > > + RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
> > > + } else {
> > > + regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy);
> > > + dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK;
> > > + dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260;
> > > + regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy);
> >
> > regmap_update_bits?
> >
> Im a bit hesitant to use regmap_update_bits() here as some of the bits
> are not documented.
Hmm, maybe I should then update the patch avoiding undocumented register
access beforehand? I will download your docs and see what remains and
send that out for you to check. Somewhen later today.
Sounds good?
Happy hacking,
Wolfram
Hi Wolfram,
On Fri, Oct 1, 2021 at 9:55 AM Wolfram Sang
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> > > Is RPCIF_CMNCR_IO3FV and RPCIF_CMNCR_IO2FV actually documented in your
> > > datasheets? I am asking because I have a patch pending to remove writing
> > > to undocumented locations. So, I was aboout to remove the IO3FV and
> > > IO2FV macros.
> > >
> > Yes they are documented, you should be able to download the HW manual from [1]
>
> Great, then I will keep them!
>
> > > > + regmap_write(rpc->regmap, RPCIF_PHYADJ2, 0x00008080);
> > > > + regmap_write(rpc->regmap, RPCIF_PHYADJ1, 0x80000024);
> > >
> > > Can't we have defines for these magic values? At least in my latest Gen3
> > > documentation, these values are explained.
> > >
> > RZ/G2L manual doesn't explain these bits. Let me refer to R-Car Gen3
> > and define them as macros.
>
> Seems like we have the best of both worlds then with the documentation
> ;)
>
Indeed :)
> > > > + if (rpc->type == RPCIF_RCAR_GEN3) {
> > > > + regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
> > > > + RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
> > > > + } else {
> > > > + regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy);
> > > > + dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK;
> > > > + dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260;
> > > > + regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy);
> > >
> > > regmap_update_bits?
> > >
> > Im a bit hesitant to use regmap_update_bits() here as some of the bits
> > are not documented.
>
> Hmm, maybe I should then update the patch avoiding undocumented register
> access beforehand? I will download your docs and see what remains and
> send that out for you to check. Somewhen later today.
>
> Sounds good?
>
Fine with me.
Cheers,
Prabhakar
> Happy hacking,
>
> Wolfram
>
Hi Wolfram,
On Thu, Sep 30, 2021 at 4:01 PM Wolfram Sang
<[email protected]> wrote:
>
>
> > This patch series adds a couple of fixes for rpc-if driver and
> > adds support for RZ/G2L SoC, where the SPI Multi I/O Bus Controller
> > is identical to the RPC-IF block found on R-Car Gen3 SoC's.
>
> I did some basic testing on the Falcon board with a Renesas R-Car V3U
> SoC and did not find a regression, so:
>
> Tested-by: Wolfram Sang <[email protected]>
>
Thank you for testing this, I will include the Tested-by tag along
with the RB tags.
Cheers,
Prabhakar
Hi Prabhakar,
I checked the G2L datasheet and reconsidered. It is better if your patch
goes in first. That means...
> > > > Is RPCIF_CMNCR_IO3FV and RPCIF_CMNCR_IO2FV actually documented in your
> > > > datasheets? I am asking because I have a patch pending to remove writing
> > > > to undocumented locations. So, I was aboout to remove the IO3FV and
> > > > IO2FV macros.
> > > >
> > > Yes they are documented, you should be able to download the HW manual from [1]
> >
> > Great, then I will keep them!
... that you could change the comments here from "undocumented" to
"documened for G2L" or similar.
> > > > > + regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy);
> > > > > + dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK;
> > > > > + dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260;
> > > > > + regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy);
> > > >
> > > > regmap_update_bits?
> > > >
> > > Im a bit hesitant to use regmap_update_bits() here as some of the bits
> > > are not documented.
Here you can keep your code as is. I will change it afterwards if needed
once I clarified all undocumented locations.
Thanks and have a nice weekend,
Wolfram
Hi Wolfram,
On Fri, Oct 1, 2021 at 1:04 PM Wolfram Sang
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> I checked the G2L datasheet and reconsidered. It is better if your patch
> goes in first. That means...
>
> > > > > Is RPCIF_CMNCR_IO3FV and RPCIF_CMNCR_IO2FV actually documented in your
> > > > > datasheets? I am asking because I have a patch pending to remove writing
> > > > > to undocumented locations. So, I was aboout to remove the IO3FV and
> > > > > IO2FV macros.
> > > > >
> > > > Yes they are documented, you should be able to download the HW manual from [1]
> > >
> > > Great, then I will keep them!
>
> ... that you could change the comments here from "undocumented" to
> "documened for G2L" or similar.
>
> > > > > > + regmap_read(rpc->regmap, RPCIF_PHYCNT, &dummy);
> > > > > > + dummy &= ~RPCIF_PHYCNT_PHYMEM_MASK;
> > > > > > + dummy |= RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260;
> > > > > > + regmap_write(rpc->regmap, RPCIF_PHYCNT, dummy);
> > > > >
> > > > > regmap_update_bits?
> > > > >
> > > > Im a bit hesitant to use regmap_update_bits() here as some of the bits
> > > > are not documented.
>
> Here you can keep your code as is. I will change it afterwards if needed
> once I clarified all undocumented locations.
>
Thanks, will re-spin the patches with comments fixed.
> Thanks and have a nice weekend,
>
You too.
Cheers,
Prabhakar
> Wolfram
>
On Tue, 28 Sep 2021 15:07:17 +0100, Lad Prabhakar wrote:
> For completeness add optional interrupts property.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
> ---
> .../devicetree/bindings/memory-controllers/renesas,rpc-if.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, 28 Sep 2021 15:07:16 +0100, Lad Prabhakar wrote:
> SPI Multi I/O Bus Controller on RZ/G2L SoC is almost identical to
> the RPC-IF interface found on R-Car Gen3 SoC's.
>
> This patch adds a new compatible string to identify the RZ/G2L family
> so that the timing values on RZ/G2L can be adjusted.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
> ---
> .../memory-controllers/renesas,rpc-if.yaml | 51 ++++++++++++++-----
> 1 file changed, 37 insertions(+), 14 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
Hi Prabhakar,
some updates after internal discussions I had.
> +#define RPCIF_CMNCR_MOIIO_HIZ(val) (RPCIF_CMNCR_MOIIO0(val) | \
> + RPCIF_CMNCR_MOIIO1(val) | \
> + RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
Shimoda-san rightfully said that '_HIZ' should be removed from the macro
name because HIZ implies the value 3.
> #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
> #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
As discussed before, mention here that they are documented for G2L.
Sadly, we can't use them with Gen3...
> -#define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
> - RPCIF_CMNCR_IO3FV(3))
> +#define RPCIF_CMNCR_IOFV_HIZ(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
> + RPCIF_CMNCR_IO3FV(val))
... which means we should remove this macro entirely because it is
forbidden for Gen3. I think it is best to use the RPCIF_CMNCR_IO<n>FV
macros directly where we need them.
Do you agree?
Kind regards,
Wolfram
On Tue, Sep 28, 2021 at 4:07 PM Lad Prabhakar
<[email protected]> wrote:
> SPI Multi I/O Bus Controller on RZ/G2L SoC is almost identical to
> the RPC-IF interface found on R-Car Gen3 SoC's.
>
> This patch adds a new compatible string to identify the RZ/G2L family
> so that the timing values on RZ/G2L can be adjusted.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, Sep 28, 2021 at 4:07 PM Lad Prabhakar
<[email protected]> wrote:
> For completeness add optional interrupts property.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
Thanks for your patch!
On Tue, Sep 28, 2021 at 4:07 PM Lad Prabhakar
<[email protected]> wrote:
> rpcif_sw_init() can fail so make sure we check the return value
> of it and on error exit rpcif_spi_probe() callback with error code.
Indeed, it will now fail earlier if CONFIG_RESET_CONTROLLER=n
Patch sent
https://lore.kernel.org/all/d4383bd1a97c0490c0bdc9dae5695f4230d4a420.1633447185.git.geert+renesas@glider.be
> Fixes: eb8d6d464a27 ("spi: add Renesas RPC-IF driver")
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, Sep 28, 2021 at 4:07 PM Lad Prabhakar
<[email protected]> wrote:
> rpcif_sw_init() can fail so make sure we check the return value
> of it and on error exit rpcif_hb_probe() callback with error code.
>
> Fixes: 5de15b610f78 ("mtd: hyperbus: add Renesas RPC-IF driver")
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds