This patch series adds a device driver for Generic Clock Controller
of lan966x SoC.
v6 -> v7:
- Added Kconfig and Makefile entires for lan966x clock driver.
v5 -> v6:
- Added Acked-by to dt-bindings file.
- Removed "_clk" in clock-names.
- Added Reviewed-by to Documentation file.
v4 -> v5:
- In v4 dt-bindings, missed adding "clock-names" in required
properties and example. So, added them.
- Returning proper error - PTR_ERR.
- Removed unused variable "ret" in probe function.
v3 -> v4:
- Updated "clocks" and added "clock-names" in dt-bindings.
- Used clk_parent_data instead of of_clk_get_parent_name().
v2 -> v3:
- Fixed dt_binding_check errors.
v1 -> v2:
- Updated license in dt-bindings.
- Updated example provided for clock controller node.
Kavyasree Kotagiri (3):
dt-bindings: clock: lan966x: Add binding includes for lan966x SoC
clock IDs
dt-bindings: clock: lan966x: Add LAN966X Clock Controller
clk: lan966x: Add lan966x SoC clock driver
.../bindings/clock/microchip,lan966x-gck.yaml | 57 +++++
drivers/clk/Kconfig | 7 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-lan966x.c | 236 ++++++++++++++++++
include/dt-bindings/clock/microchip,lan966x.h | 28 +++
5 files changed, 329 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
create mode 100644 drivers/clk/clk-lan966x.c
create mode 100644 include/dt-bindings/clock/microchip,lan966x.h
--
2.17.1
This adds the DT bindings documentation for lan966x SoC
generic clock controller.
Signed-off-by: Kavyasree Kotagiri <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
v6 -> v7:
- No changes.
v5 -> v6:
- Removed "_clk" in clock-names.
- Added Reviewed-by.
v4 -> v5:
- In v4 dt-bindings, missed adding "clock-names" in required
properties and example. So, added them.
v3 -> v4:
- Updated "clocks" description.
- Added "clock-names".
v2 -> v3:
- Fixed dt_binding_check errors.
v1 -> v2:
- Updated example provided for clk controller DT node.
.../bindings/clock/microchip,lan966x-gck.yaml | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
new file mode 100644
index 000000000000..fca83bd68e26
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN966X Generic Clock Controller
+
+maintainers:
+ - Kavyasree Kotagiri <[email protected]>
+
+description: |
+ The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
+ ddr_clk and sys_clk. This clock controller generates and supplies
+ clock to various peripherals within the SoC.
+
+properties:
+ compatible:
+ const: microchip,lan966x-gck
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: CPU clock source
+ - description: DDR clock source
+ - description: System clock source
+
+ clock-names:
+ items:
+ - const: cpu
+ - const: ddr
+ - const: sys
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clks: clock-controller@e00c00a8 {
+ compatible = "microchip,lan966x-gck";
+ #clock-cells = <1>;
+ clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
+ clock-names = "cpu", "ddr", "sys";
+ reg = <0xe00c00a8 0x38>;
+ };
+...
--
2.17.1