There are some syntactical mistakes in the json files for the Cortex A76
N1 (Neoverse N1). This was obstructing parsing from an external tool.
This patch fixes the erroneous placement of commas causing the problems.
Signed-off-by: Andrew Kilroy <[email protected]>
---
.../arch/arm64/arm/cortex-a76-n1/branch.json | 4 +--
.../arch/arm64/arm/cortex-a76-n1/bus.json | 12 +++----
.../arch/arm64/arm/cortex-a76-n1/cache.json | 34 +++++++++----------
.../arm64/arm/cortex-a76-n1/exception.json | 4 +--
.../arm64/arm/cortex-a76-n1/instruction.json | 18 +++++-----
.../arch/arm64/arm/cortex-a76-n1/memory.json | 2 +-
.../arch/arm64/arm/cortex-a76-n1/other.json | 2 +-
.../arm64/arm/cortex-a76-n1/pipeline.json | 4 +--
8 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
index ec0dc92288ab..db68de188390 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
@@ -1,10 +1,10 @@
[
{
"PublicDescription": "This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken",
- "ArchStdEvent": "BR_MIS_PRED",
+ "ArchStdEvent": "BR_MIS_PRED"
},
{
"PublicDescription": "This event counts all predictable branches.",
- "ArchStdEvent": "BR_PRED",
+ "ArchStdEvent": "BR_PRED"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json
index 6263929efce2..e0875d3a685d 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json
@@ -1,21 +1,21 @@
[
{
- "PublicDescription": "The number of core clock cycles"
+ "PublicDescription": "The number of core clock cycles",
"ArchStdEvent": "CPU_CYCLES",
"BriefDescription": "The number of core clock cycles."
},
{
"PublicDescription": "This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.",
- "ArchStdEvent": "BUS_ACCESS",
+ "ArchStdEvent": "BUS_ACCESS"
},
{
- "PublicDescription": "This event duplicates CPU_CYCLES."
- "ArchStdEvent": "BUS_CYCLES",
+ "PublicDescription": "This event duplicates CPU_CYCLES.",
+ "ArchStdEvent": "BUS_CYCLES"
},
{
- "ArchStdEvent": "BUS_ACCESS_RD",
+ "ArchStdEvent": "BUS_ACCESS_RD"
},
{
- "ArchStdEvent": "BUS_ACCESS_WR",
+ "ArchStdEvent": "BUS_ACCESS_WR"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json
index cd67bb9df139..fc448c2d5ea4 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json
@@ -1,47 +1,47 @@
[
{
"PublicDescription": "This event counts any instruction fetch which misses in the cache.",
- "ArchStdEvent": "L1I_CACHE_REFILL",
+ "ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault.",
- "ArchStdEvent": "L1I_TLB_REFILL",
+ "ArchStdEvent": "L1I_TLB_REFILL"
},
{
"PublicDescription": "This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1.",
- "ArchStdEvent": "L1D_CACHE_REFILL",
+ "ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"PublicDescription": "This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count.",
- "ArchStdEvent": "L1D_CACHE",
+ "ArchStdEvent": "L1D_CACHE"
},
{
"PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault.",
- "ArchStdEvent": "L1D_TLB_REFILL",
+ "ArchStdEvent": "L1D_TLB_REFILL"
},
- {,
+ {
"PublicDescription": "Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache.",
- "ArchStdEvent": "L1I_CACHE",
+ "ArchStdEvent": "L1I_CACHE"
},
{
"PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations.",
- "ArchStdEvent": "L1D_CACHE_WB",
+ "ArchStdEvent": "L1D_CACHE_WB"
},
{
"PublicDescription": "This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.",
- "ArchStdEvent": "L2D_CACHE",
+ "ArchStdEvent": "L2D_CACHE"
},
{
"PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted",
- "ArchStdEvent": "L2D_CACHE_REFILL",
+ "ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"PublicDescription": "This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted",
- "ArchStdEvent": "L2D_CACHE_WB",
+ "ArchStdEvent": "L2D_CACHE_WB"
},
{
"PublicDescription": "This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1.",
- "ArchStdEvent": "L2D_CACHE_ALLOCATE",
+ "ArchStdEvent": "L2D_CACHE_ALLOCATE"
},
{
"PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled.",
@@ -75,21 +75,21 @@
},
{
"PublicDescription": "This event counts on any access to the L2 TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled.",
- "ArchStdEvent": "L2D_TLB",
+ "ArchStdEvent": "L2D_TLB"
},
{
"PublicDescription": "This event counts on any data access which causes L2D_TLB_REFILL to count.",
- "ArchStdEvent": "DTLB_WALK",
+ "ArchStdEvent": "DTLB_WALK"
},
{
"PublicDescription": "This event counts on any instruction access which causes L2D_TLB_REFILL to count.",
- "ArchStdEvent": "ITLB_WALK",
+ "ArchStdEvent": "ITLB_WALK"
},
{
- "ArchStdEvent": "LL_CACHE_RD",
+ "ArchStdEvent": "LL_CACHE_RD"
},
{
- "ArchStdEvent": "LL_CACHE_MISS_RD",
+ "ArchStdEvent": "LL_CACHE_MISS_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json
index ea4631db41b5..ce942324ee60 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json
@@ -1,10 +1,10 @@
[
{
- "ArchStdEvent": "EXC_TAKEN",
+ "ArchStdEvent": "EXC_TAKEN"
},
{
"PublicDescription": "This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
- "ArchStdEvent": "MEMORY_ERROR",
+ "ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "EXC_DABORT"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json
index 8e59566cba8b..b0b439a36ae9 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json
@@ -1,32 +1,32 @@
[
{
- "ArchStdEvent": "SW_INCR",
+ "ArchStdEvent": "SW_INCR"
},
{
"PublicDescription": "This event counts all retired instructions, including those that fail their condition check.",
- "ArchStdEvent": "INST_RETIRED",
+ "ArchStdEvent": "INST_RETIRED"
},
{
- "ArchStdEvent": "EXC_RETURN",
+ "ArchStdEvent": "EXC_RETURN"
},
{
"PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.",
- "ArchStdEvent": "CID_WRITE_RETIRED",
+ "ArchStdEvent": "CID_WRITE_RETIRED"
},
{
- "ArchStdEvent": "INST_SPEC",
+ "ArchStdEvent": "INST_SPEC"
},
{
"PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.",
- "ArchStdEvent": "TTBR_WRITE_RETIRED",
+ "ArchStdEvent": "TTBR_WRITE_RETIRED"
},
- {,
+ {
"PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.",
- "ArchStdEvent": "BR_RETIRED",
+ "ArchStdEvent": "BR_RETIRED"
},
{
"PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.",
- "ArchStdEvent": "BR_MIS_PRED_RETIRED",
+ "ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "ASE_SPEC"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json
index f06f399051c1..20a929e7728d 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json
@@ -1,7 +1,7 @@
[
{
"PublicDescription": "This event counts memory accesses due to load or store instructions. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR.",
- "ArchStdEvent": "MEM_ACCESS",
+ "ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/other.json
index c2ccbf6fbfa0..20d8365756c5 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/other.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/other.json
@@ -1,5 +1,5 @@
[
{
- "ArchStdEvent": "REMOTE_ACCESS",
+ "ArchStdEvent": "REMOTE_ACCESS"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json
index d79f0aeaf7f1..b4e96551d51a 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json
@@ -1,10 +1,10 @@
[
{
"PublicDescription": "The counter counts on any cycle when there are no fetched instructions available to dispatch.",
- "ArchStdEvent": "STALL_FRONTEND",
+ "ArchStdEvent": "STALL_FRONTEND"
},
{
"PublicDescription": "The counter counts on any cycle fetched instructions are not dispatched due to resource constraints.",
- "ArchStdEvent": "STALL_BACKEND",
+ "ArchStdEvent": "STALL_BACKEND"
}
]
--
2.17.1
On 04/10/2021 17:00, Andrew Kilroy wrote:
> There are some syntactical mistakes in the json files for the Cortex A76
> N1 (Neoverse N1). This was obstructing parsing from an external tool.
If the trailing comma is not allowed by standard, then maybe we should
fix our parsing tool to not allow it also. However maybe there is a good
reason why we allow it..
Reviewed-by: John Garry <[email protected]>
>
> This patch fixes the erroneous placement of commas causing the problems.
>
> Signed-off-by: Andrew Kilroy<[email protected]>
> ---
> .../arch/arm64/arm/cortex-a76-n1/branch.json | 4 +--
> .../arch/arm64/arm/cortex-a76-n1/bus.json | 12 +++----
> .../arch/arm64/arm/cortex-a76-n1/cache.json | 34 +++++++++----------
> .../arm64/arm/cortex-a76-n1/exception.json | 4 +--
> .../arm64/arm/cortex-a76-n1/instruction.json | 18 +++++-----
> .../arch/arm64/arm/cortex-a76-n1/memory.json | 2 +-
> .../arch/arm64/arm/cortex-a76-n1/other.json | 2 +-
> .../arm64/arm/cortex-a76-n1/pipeline.json | 4 +--
> 8 files changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> index ec0dc92288ab..db68de188390 100644
> --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> @@ -1,10 +1,10 @@
> [
> {
> "PublicDescription": "This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken",
> - "ArchStdEvent": "BR_MIS_PRED",
> + "ArchStdEvent": "BR_MIS_PRED"
> },
On 05/10/2021 11:10, John Garry wrote:
> On 04/10/2021 17:00, Andrew Kilroy wrote:
>> There are some syntactical mistakes in the json files for the Cortex A76
>> N1 (Neoverse N1). This was obstructing parsing from an external tool.
>
> If the trailing comma is not allowed by standard, then maybe we should fix our parsing tool to not allow it also. However maybe there is a good reason why we allow it..
It would be nice to do, because I have also made similar fixes before. We looked at the STRICT option
in the parser (https://github.com/zserge/jsmn), but even then it seems to allow trailing commas.
Trailing commas are not allowed in the json standard, but there is a split between parsers
where some allow it and others don't. Specifically the Python parser doesn't allow it, and Python
can easily be involved in some workflow that parses these files.
The only way forwards I can think of is either getting a change accepted upstream to the parser
and then updating it in perf, switching to a different parser, or doing some hack to add an extra
step in perf to look for commas. None of which sound ideal.
James
On 06/10/2021 09:43, James Clark wrote:
+ Andi
>
>
> On 05/10/2021 11:10, John Garry wrote:
>> On 04/10/2021 17:00, Andrew Kilroy wrote:
>>> There are some syntactical mistakes in the json files for the Cortex A76
>>> N1 (Neoverse N1). This was obstructing parsing from an external tool.
>>
>> If the trailing comma is not allowed by standard, then maybe we should fix our parsing tool to not allow it also. However maybe there is a good reason why we allow it..
>
> It would be nice to do, because I have also made similar fixes before. We looked at the STRICT option
> in the parser (https://github.com/zserge/jsmn), but even then it seems to allow trailing commas.
>
> Trailing commas are not allowed in the json standard, but there is a split between parsers
> where some allow it and others don't. Specifically the Python parser doesn't allow it, and Python
> can easily be involved in some workflow that parses these files.
>
> The only way forwards I can think of is either getting a change accepted upstream to the parser
> and then updating it in perf, switching to a different parser, or doing some hack to add an extra
> step in perf to look for commas. None of which sound ideal.
>
Looking at the license in jsmn.c, we seem to be ok to modify it (to
error on non-standard trailing ',') - that parser has already apparently
been modified in mainline.
If we do that then I hope that there are not to many violations in out
JSONs, including downstream.
Thanks,
John
On 10/6/2021 9:26 AM, John Garry wrote:
> On 06/10/2021 09:43, James Clark wrote:
>
> + Andi
>
>>
>>
>> On 05/10/2021 11:10, John Garry wrote:
>>> On 04/10/2021 17:00, Andrew Kilroy wrote:
>>>> There are some syntactical mistakes in the json files for the
>>>> Cortex A76
>>>> N1 (Neoverse N1). This was obstructing parsing from an external tool.
>>>
>>> If the trailing comma is not allowed by standard, then maybe we
>>> should fix our parsing tool to not allow it also. However maybe
>>> there is a good reason why we allow it..
>>
>> It would be nice to do, because I have also made similar fixes
>> before. We looked at the STRICT option
>> in the parser (https://github.com/zserge/jsmn), but even then it
>> seems to allow trailing commas.
>>
>> Trailing commas are not allowed in the json standard, but there is a
>> split between parsers
>> where some allow it and others don't. Specifically the Python parser
>> doesn't allow it, and Python
>> can easily be involved in some workflow that parses these files.
>>
>> The only way forwards I can think of is either getting a change
>> accepted upstream to the parser
>> and then updating it in perf, switching to a different parser, or
>> doing some hack to add an extra
>> step in perf to look for commas. None of which sound ideal.
>>
>
> Looking at the license in jsmn.c, we seem to be ok to modify it (to
> error on non-standard trailing ',') - that parser has already
> apparently been modified in mainline.
>
> If we do that then I hope that there are not to many violations in out
> JSONs, including downstream.
Sure we can modify the file. I already did some minor changes when I
submitted it originally.
-Andi
On Thu, Oct 7, 2021 at 5:03 PM Andi Kleen <[email protected]> wrote:
>
>
> On 10/6/2021 9:26 AM, John Garry wrote:
> > On 06/10/2021 09:43, James Clark wrote:
> >
> > + Andi
> >
> >>
> >>
> >> On 05/10/2021 11:10, John Garry wrote:
> >>> On 04/10/2021 17:00, Andrew Kilroy wrote:
> >>>> There are some syntactical mistakes in the json files for the
> >>>> Cortex A76
> >>>> N1 (Neoverse N1). This was obstructing parsing from an external tool.
> >>>
> >>> If the trailing comma is not allowed by standard, then maybe we
> >>> should fix our parsing tool to not allow it also. However maybe
> >>> there is a good reason why we allow it..
> >>
> >> It would be nice to do, because I have also made similar fixes
> >> before. We looked at the STRICT option
> >> in the parser (https://github.com/zserge/jsmn), but even then it
> >> seems to allow trailing commas.
> >>
> >> Trailing commas are not allowed in the json standard, but there is a
> >> split between parsers
> >> where some allow it and others don't. Specifically the Python parser
> >> doesn't allow it, and Python
> >> can easily be involved in some workflow that parses these files.
> >>
> >> The only way forwards I can think of is either getting a change
> >> accepted upstream to the parser
> >> and then updating it in perf, switching to a different parser, or
> >> doing some hack to add an extra
> >> step in perf to look for commas. None of which sound ideal.
> >>
> >
> > Looking at the license in jsmn.c, we seem to be ok to modify it (to
> > error on non-standard trailing ',') - that parser has already
> > apparently been modified in mainline.
> >
> > If we do that then I hope that there are not to many violations in out
> > JSONs, including downstream.
>
>
> Sure we can modify the file. I already did some minor changes when I
> submitted it originally.
>
> -Andi
jsmn is a somewhat frustrating way to work on json code and working on
a forked version of jsmn was frustrating in [1]. Could we assume
python on build systems and rewrite jevents in python?
Thanks,
Ian
[1] https://lore.kernel.org/lkml/[email protected]/
On 08/10/2021 03:59, Ian Rogers wrote:
> On Thu, Oct 7, 2021 at 5:03 PM Andi Kleen <[email protected]> wrote:
>>
>>
>> On 10/6/2021 9:26 AM, John Garry wrote:
>>> On 06/10/2021 09:43, James Clark wrote:
>>>
>>> + Andi
>>>
>>>>
>>>>
>>>> On 05/10/2021 11:10, John Garry wrote:
>>>>> On 04/10/2021 17:00, Andrew Kilroy wrote:
>>>>>> There are some syntactical mistakes in the json files for the
>>>>>> Cortex A76
>>>>>> N1 (Neoverse N1). This was obstructing parsing from an external tool.
>>>>>
>>>>> If the trailing comma is not allowed by standard, then maybe we
>>>>> should fix our parsing tool to not allow it also. However maybe
>>>>> there is a good reason why we allow it..
>>>>
>>>> It would be nice to do, because I have also made similar fixes
>>>> before. We looked at the STRICT option
>>>> in the parser (https://github.com/zserge/jsmn), but even then it
>>>> seems to allow trailing commas.
>>>>
>>>> Trailing commas are not allowed in the json standard, but there is a
>>>> split between parsers
>>>> where some allow it and others don't. Specifically the Python parser
>>>> doesn't allow it, and Python
>>>> can easily be involved in some workflow that parses these files.
>>>>
>>>> The only way forwards I can think of is either getting a change
>>>> accepted upstream to the parser
>>>> and then updating it in perf, switching to a different parser, or
>>>> doing some hack to add an extra
>>>> step in perf to look for commas. None of which sound ideal.
>>>>
>>>
>>> Looking at the license in jsmn.c, we seem to be ok to modify it (to
>>> error on non-standard trailing ',') - that parser has already
>>> apparently been modified in mainline.
>>>
>>> If we do that then I hope that there are not to many violations in out
>>> JSONs, including downstream.
>>
>>
>> Sure we can modify the file. I already did some minor changes when I
>> submitted it originally.
>>
>> -Andi
>
> jsmn is a somewhat frustrating way to work on json code and working on
> a forked version of jsmn was frustrating in [1]. Could we assume
> python on build systems and rewrite jevents in python?
Seems reasonable to me, although maybe a big job. I suppose there could be
an empty generated pmu file for systems that don't have Python and only the
ones listed in pmu-events/arch/ would need it.
James
>
> Thanks,
> Ian
>
> [1] https://lore.kernel.org/lkml/[email protected]/
>