This adds the defines for the power domains provided by the DISP
blk-ctrl.
Signed-off-by: Adam Ford <[email protected]>
---
include/dt-bindings/power/imx8mn-power.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h
index 102ee85a9b62..eedd0e581939 100644
--- a/include/dt-bindings/power/imx8mn-power.h
+++ b/include/dt-bindings/power/imx8mn-power.h
@@ -12,4 +12,9 @@
#define IMX8MN_POWER_DOMAIN_DISPMIX 3
#define IMX8MN_POWER_DOMAIN_MIPI 4
+#define IMX8MN_DISPBLK_PD_MIPI_DSI 0
+#define IMX8MN_DISPBLK_PD_MIPI_CSI 1
+#define IMX8MN_DISPBLK_PD_LCDIF 2
+#define IMX8MN_DISPBLK_PD_ISI 3
+
#endif
--
2.25.1
This adds the DT binding for the i.MX8MN DISP blk-ctrl.
Signed-off-by: Adam Ford <[email protected]>
---
.../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
new file mode 100644
index 000000000000..92d30aff446e
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MN DISP blk-ctrl
+
+maintainers:
+ - Lucas Stach <[email protected]>
+
+description:
+ The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
+ the NoC and ensuring proper power sequencing of the display and MIPI CSI
+ peripherals located in the DISP domain of the SoC.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx8mn-disp-blk-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ power-domains:
+ minItems: 5
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: bus
+ - const: isi
+ - const: lcdif
+ - const: mipi-dsi
+ - const: mipi-csi
+
+ clocks:
+ minItems: 11
+ maxItems: 11
+
+ clock-names:
+ items:
+ - const: disp_axi
+ - const: disp_apb
+ - const: disp_axi_root
+ - const: disp_apb_root
+ - const: lcdif-axi
+ - const: lcdif-apb
+ - const: lcdif-pix
+ - const: dsi-pclk
+ - const: dsi-ref
+ - const: csi-aclk
+ - const: csi-pclk
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - power-domain-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mn-clock.h>
+ #include <dt-bindings/power/imx8mn-power.h>
+
+ disp_blk_ctl: blk_ctrl@32e28000 {
+ compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
+ reg = <0x32e28000 0x100>;
+ power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+ <&pgc_dispmix>, <&pgc_mipi>,
+ <&pgc_mipi>;
+ power-domain-names = "bus", "isi", "lcdif", "mipi-dsi",
+ "mipi-csi";
+ clocks = <&clk IMX8MN_CLK_DISP_AXI>,
+ <&clk IMX8MN_CLK_DISP_APB>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+ <&clk IMX8MN_CLK_DSI_CORE>,
+ <&clk IMX8MN_CLK_DSI_PHY_REF>,
+ <&clk IMX8MN_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
+ clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root",
+ "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
+ "dsi-ref", "csi-aclk", "csi-pclk";
+ #power-domain-cells = <1>;
+ };
--
2.25.1
Now that we have support for the power domain controller on the i.MX8MN,
we can put the USB controller in the respective power domain to allow
it to power down the PHY when possible.
Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 4191b5bfcdf3..ea994dd9fb03 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1021,6 +1021,7 @@ usbotg1: usb@32e40000 {
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
+ power-domains = <&pgc_otg1>;
status = "disabled";
};
--
2.25.1
The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as:
etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203
Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 57f67257d2fd..46144a7482d3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1089,6 +1089,31 @@ gpmi: nand-controller@33002000 {
status = "disabled";
};
+ gpu: gpu@38000000 {
+ compatible = "vivante,gc";
+ reg = <0x38000000 0x8000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_GPU_AHB>,
+ <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+ <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+ <&clk IMX8MN_CLK_GPU_SHADER_DIV>;
+ clock-names = "reg", "bus", "core", "shader";
+ assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
+ <&clk IMX8MN_CLK_GPU_SHADER_SRC>,
+ <&clk IMX8MN_CLK_GPU_AXI>,
+ <&clk IMX8MN_CLK_GPU_AHB>,
+ <&clk IMX8MN_GPU_PLL>,
+ <&clk IMX8MN_CLK_GPU_CORE_DIV>,
+ <&clk IMX8MN_CLK_GPU_SHADER_DIV>;
+ assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
+ <&clk IMX8MN_GPU_PLL_OUT>,
+ <&clk IMX8MN_SYS_PLL1_800M>,
+ <&clk IMX8MN_SYS_PLL1_800M>;
+ assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
+ <400000000>, <400000000>;
+ power-domains = <&pgc_gpumix>;
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
--
2.25.1
Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.
Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 49 +++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index da6c942fb7f9..4191b5bfcdf3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -612,6 +614,53 @@ src: reset-controller@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mn-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_hsiomix: power-domain@0 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
+ clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
+ };
+
+ pgc_otg1: power-domain@1 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_OTG1>;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_gpumix: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
+ clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+ <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
+ <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+ <&clk IMX8MN_CLK_GPU_AHB>;
+ resets = <&src IMX8MQ_RESET_GPU_RESET>;
+ };
+
+ pgc_dispmix: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
+ clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+ };
+
+ pgc_mipi: power-domain@4 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_MIPI>;
+ power-domains = <&pgc_dispmix>;
+ };
+ };
+ };
};
aips2: bus@30400000 {
--
2.25.1
Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains should be functional.
Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index ea994dd9fb03..57f67257d2fd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1011,6 +1011,34 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges;
+ disp_blk_ctrl: blk-ctrl@32e28000 {
+ compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
+ reg = <0x32e28000 0x100>;
+ power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+ <&pgc_dispmix>, <&pgc_mipi>,
+ <&pgc_mipi>;
+ power-domain-names = "bus", "isi",
+ "lcdif", "mipi-dsi",
+ "mipi-csi";
+ clocks = <&clk IMX8MN_CLK_DISP_AXI>,
+ <&clk IMX8MN_CLK_DISP_APB>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+ <&clk IMX8MN_CLK_DSI_CORE>,
+ <&clk IMX8MN_CLK_DSI_PHY_REF>,
+ <&clk IMX8MN_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
+ clock-names = "disp_axi", "disp_apb",
+ "disp_axi_root", "disp_apb_root",
+ "lcdif-axi", "lcdif-apb", "lcdif-pix",
+ "dsi-pclk", "dsi-ref",
+ "csi-aclk", "csi-pclk";
+ #power-domain-cells = <1>;
+ };
+
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
reg = <0x32e40000 0x200>;
--
2.25.1
Am Dienstag, dem 05.10.2021 um 19:04 -0500 schrieb Adam Ford:
> This adds the DT binding for the i.MX8MN DISP blk-ctrl.
>
> Signed-off-by: Adam Ford <[email protected]>
> ---
> .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
> new file mode 100644
> index 000000000000..92d30aff446e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
> @@ -0,0 +1,97 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
mm -> mn in the file name.
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8MN DISP blk-ctrl
> +
> +maintainers:
> + - Lucas Stach <[email protected]>
I'm not opposed to being maintainer for this file, just making sure
that this is what you intended.
Other than that I think this looks okay.
Regards,
Lucas
> +
> +description:
> + The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
> + the NoC and ensuring proper power sequencing of the display and MIPI CSI
> + peripherals located in the DISP domain of the SoC.
> +
> +properties:
> + compatible:
> + items:
> + - const: fsl,imx8mn-disp-blk-ctrl
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + power-domains:
> + minItems: 5
> + maxItems: 5
> +
> + power-domain-names:
> + items:
> + - const: bus
> + - const: isi
> + - const: lcdif
> + - const: mipi-dsi
> + - const: mipi-csi
> +
> + clocks:
> + minItems: 11
> + maxItems: 11
> +
> + clock-names:
> + items:
> + - const: disp_axi
> + - const: disp_apb
> + - const: disp_axi_root
> + - const: disp_apb_root
> + - const: lcdif-axi
> + - const: lcdif-apb
> + - const: lcdif-pix
> + - const: dsi-pclk
> + - const: dsi-ref
> + - const: csi-aclk
> + - const: csi-pclk
> +
> +required:
> + - compatible
> + - reg
> + - power-domains
> + - power-domain-names
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mn-clock.h>
> + #include <dt-bindings/power/imx8mn-power.h>
> +
> + disp_blk_ctl: blk_ctrl@32e28000 {
> + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
> + reg = <0x32e28000 0x100>;
> + power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
> + <&pgc_dispmix>, <&pgc_mipi>,
> + <&pgc_mipi>;
> + power-domain-names = "bus", "isi", "lcdif", "mipi-dsi",
> + "mipi-csi";
> + clocks = <&clk IMX8MN_CLK_DISP_AXI>,
> + <&clk IMX8MN_CLK_DISP_APB>,
> + <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> + <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
> + <&clk IMX8MN_CLK_DSI_CORE>,
> + <&clk IMX8MN_CLK_DSI_PHY_REF>,
> + <&clk IMX8MN_CLK_CSI1_PHY_REF>,
> + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
> + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root",
> + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
> + "dsi-ref", "csi-aclk", "csi-pclk";
> + #power-domain-cells = <1>;
> + };
Am Dienstag, dem 05.10.2021 um 19:05 -0500 schrieb Adam Ford:
> Add the DT node for the GPC, including all the PGC power domains,
> some of them are not fully functional yet, as they require interaction
> with the blk-ctrls to properly power up/down the peripherals.
>
> Signed-off-by: Adam Ford <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 49 +++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index da6c942fb7f9..4191b5bfcdf3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -4,6 +4,8 @@
> */
>
> #include <dt-bindings/clock/imx8mn-clock.h>
> +#include <dt-bindings/power/imx8mn-power.h>
> +#include <dt-bindings/reset/imx8mq-reset.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -612,6 +614,53 @@ src: reset-controller@30390000 {
> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx8mn-gpc";
> + reg = <0x303a0000 0x10000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_hsiomix: power-domain@0 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
> + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
This should be IMX8MN_CLK_USB_BUS.
Regards,
Lucas
> + };
> +
> + pgc_otg1: power-domain@1 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MN_POWER_DOMAIN_OTG1>;
> + power-domains = <&pgc_hsiomix>;
> + };
> +
> + pgc_gpumix: power-domain@2 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
> + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
> + <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
> + <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
> + <&clk IMX8MN_CLK_GPU_AHB>;
> + resets = <&src IMX8MQ_RESET_GPU_RESET>;
> + };
> +
> + pgc_dispmix: power-domain@3 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
> + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MN_CLK_DISP_APB_ROOT>;
> + };
> +
> + pgc_mipi: power-domain@4 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MN_POWER_DOMAIN_MIPI>;
> + power-domains = <&pgc_dispmix>;
> + };
> + };
> + };
> };
>
> aips2: bus@30400000 {
Am Dienstag, dem 05.10.2021 um 19:05 -0500 schrieb Adam Ford:
> Now that we have support for the power domain controller on the i.MX8MN,
> we can put the USB controller in the respective power domain to allow
> it to power down the PHY when possible.
>
> Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 4191b5bfcdf3..ea994dd9fb03 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1021,6 +1021,7 @@ usbotg1: usb@32e40000 {
> assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
> phys = <&usbphynop1>;
> fsl,usbmisc = <&usbmisc1 0>;
> + power-domains = <&pgc_otg1>;
> status = "disabled";
> };
>
Am Dienstag, dem 05.10.2021 um 19:05 -0500 schrieb Adam Ford:
> The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as:
>
> etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203
>
> Signed-off-by: Adam Ford <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 57f67257d2fd..46144a7482d3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1089,6 +1089,31 @@ gpmi: nand-controller@33002000 {
> status = "disabled";
> };
>
> + gpu: gpu@38000000 {
> + compatible = "vivante,gc";
> + reg = <0x38000000 0x8000>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MN_CLK_GPU_AHB>,
> + <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
> + <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
> + <&clk IMX8MN_CLK_GPU_SHADER_DIV>;
Last one should be just IMX8MN_CLK_GPU_SHADER.
> + clock-names = "reg", "bus", "core", "shader";
> + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
> + <&clk IMX8MN_CLK_GPU_SHADER_SRC>,
> + <&clk IMX8MN_CLK_GPU_AXI>,
> + <&clk IMX8MN_CLK_GPU_AHB>,
> + <&clk IMX8MN_GPU_PLL>,
> + <&clk IMX8MN_CLK_GPU_CORE_DIV>,
> + <&clk IMX8MN_CLK_GPU_SHADER_DIV>;
_SRC and _DIV clocks are just legacy aliases for the now composite
clocks and should not be used in new DTs. Please just use the composite
clock handles directly.
Regards,
Lucas
> + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
> + <&clk IMX8MN_GPU_PLL_OUT>,
> + <&clk IMX8MN_SYS_PLL1_800M>,
> + <&clk IMX8MN_SYS_PLL1_800M>;
> + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
> + <400000000>, <400000000>;
> + power-domains = <&pgc_gpumix>;
> + };
> +
> gic: interrupt-controller@38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>,
On Wed, Oct 6, 2021 at 2:39 AM Lucas Stach <[email protected]> wrote:
>
> Am Dienstag, dem 05.10.2021 um 19:04 -0500 schrieb Adam Ford:
> > This adds the DT binding for the i.MX8MN DISP blk-ctrl.
> >
> > Signed-off-by: Adam Ford <[email protected]>
> > ---
> > .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++
> > 1 file changed, 97 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
> > new file mode 100644
> > index 000000000000..92d30aff446e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
> > @@ -0,0 +1,97 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
>
> mm -> mn in the file name.
Oops, I missed one. Thanks for catching.
>
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NXP i.MX8MN DISP blk-ctrl
> > +
> > +maintainers:
> > + - Lucas Stach <[email protected]>
>
> I'm not opposed to being maintainer for this file, just making sure
> that this is what you intended.
Because this yaml file points to the driver you wrote, I thought it
made sense to have you be the maintainer. In hindsight, I should have
asked first. Sorry about that.
>
> Other than that I think this looks okay.
Thanks for reviewing the series. I'll try to get a V2 prepared
tomorrow, and I'll wait a little bit to send it, just in case NXP
wants to give some feedback as well.
adam
>
> Regards,
> Lucas
>
> > +
> > +description:
> > + The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
> > + the NoC and ensuring proper power sequencing of the display and MIPI CSI
> > + peripherals located in the DISP domain of the SoC.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: fsl,imx8mn-disp-blk-ctrl
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#power-domain-cells':
> > + const: 1
> > +
> > + power-domains:
> > + minItems: 5
> > + maxItems: 5
> > +
> > + power-domain-names:
> > + items:
> > + - const: bus
> > + - const: isi
> > + - const: lcdif
> > + - const: mipi-dsi
> > + - const: mipi-csi
> > +
> > + clocks:
> > + minItems: 11
> > + maxItems: 11
> > +
> > + clock-names:
> > + items:
> > + - const: disp_axi
> > + - const: disp_apb
> > + - const: disp_axi_root
> > + - const: disp_apb_root
> > + - const: lcdif-axi
> > + - const: lcdif-apb
> > + - const: lcdif-pix
> > + - const: dsi-pclk
> > + - const: dsi-ref
> > + - const: csi-aclk
> > + - const: csi-pclk
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - power-domains
> > + - power-domain-names
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/imx8mn-clock.h>
> > + #include <dt-bindings/power/imx8mn-power.h>
> > +
> > + disp_blk_ctl: blk_ctrl@32e28000 {
> > + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
> > + reg = <0x32e28000 0x100>;
> > + power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
> > + <&pgc_dispmix>, <&pgc_mipi>,
> > + <&pgc_mipi>;
> > + power-domain-names = "bus", "isi", "lcdif", "mipi-dsi",
> > + "mipi-csi";
> > + clocks = <&clk IMX8MN_CLK_DISP_AXI>,
> > + <&clk IMX8MN_CLK_DISP_APB>,
> > + <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
> > + <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> > + <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
> > + <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> > + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
> > + <&clk IMX8MN_CLK_DSI_CORE>,
> > + <&clk IMX8MN_CLK_DSI_PHY_REF>,
> > + <&clk IMX8MN_CLK_CSI1_PHY_REF>,
> > + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
> > + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root",
> > + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
> > + "dsi-ref", "csi-aclk", "csi-pclk";
> > + #power-domain-cells = <1>;
> > + };
>
>
On Tue, 05 Oct 2021 19:04:59 -0500, Adam Ford wrote:
> This adds the DT binding for the i.MX8MN DISP blk-ctrl.
>
> Signed-off-by: Adam Ford <[email protected]>
> ---
> .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml:78:1: [error] syntax error: found character '\t' that cannot start any token (syntax)
dtschema/dtc warnings/errors:
make[1]: *** Deleting file 'Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.example.dts'
Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 434, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 120, in get_single_data
node = self.composer.get_single_node()
File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node
File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 773, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 848, in _ruamel_yaml.CParser._compose_sequence_node
File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event
ruamel.yaml.scanner.ScannerError: while scanning a block scalar
in "<unicode string>", line 70, column 5
found a tab character where an indentation space is expected
in "<unicode string>", line 78, column 1
make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
./Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml: while scanning a block scalar
in "<unicode string>", line 70, column 5
found a tab character where an indentation space is expected
in "<unicode string>", line 78, column 1
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
make: *** [Makefile:1441: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1536963
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.