From: Alexandru Tachici <[email protected]>
The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
industrial Ethernet applications and is compliant with the IEEE 802.3cg
Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.
The ADIN1100 uses Auto-Negotiation capability in accordance
with IEEE 802.3 Clause 98, providing a mechanism for
exchanging information between PHYs to allow link partners to
agree to a common mode of operation.
The concluded operating mode is the transmit amplitude mode and
master/slave preference common across the two devices.
Both device and LP advertise their ability and request for
increased transmit at:
- BASE-T1 autonegotiation advertisement register [47:32]\
Clause 45.2.7.21 of Standard 802.3
- BIT(13) - 10BASE-T1L High Level Transmit Operating Mode Ability
- BIT(12) - 10BASE-T1L High Level Transmit Operating Mode Request
For 2.4 Vpp (high level transmit) operation, both devices need
to have the High Level Transmit Operating Mode Ability bit set,
and only one of them needs to have the High Level Transmit
Operating Mode Request bit set. Otherwise 1.0 Vpp transmit level
will be used.
Ethtool output:
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT1L/Full
Supported pause frame use: Transmit-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Full
Advertised pause frame use: Transmit-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT1L/Full
Link partner advertised pause frame use: No
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
master-slave cfg: preferred master
master-slave status: master
Port: MII
PHYAD: 0
Transceiver: external
Link detected: yes
SQI: 7/7
1. Add basic support for ADIN1100.
Alexandru Ardelean (1):
net: phy: adin1100: Add initial support for ADIN1100 industrial PHY
1. Added 10baset-T1L link modes.
2. Added 10-BasetT1L registers that are used in ADIN1100 driver.
3. Added BaseT1 auto-negotiation registers. For ADIN1100 these
registers decide master/slave status and TX voltage of the
device and link partner.
4. Allow user to set the master-slave configuration of ADIN1100.
5. Convert MSE to SQI using a predefined table and allow user access
through ethtool.
6. DT bindings for the 2.4 Vpp transmit mode.
7. DT bindings for ADIN1100.
Alexandru Tachici (7):
ethtool: Add 10base-T1L link mode entry
net: phy: Add 10-BaseT1L registers
net: phy: Add BaseT1 auto-negotiation registers
net: phy: adin1100: Add ethtool master-slave support
net: phy: adin1100: Add SQI support
dt-bindings: net: phy: Add 10-baseT1L 2.4 Vpp
dt-bindings: adin1100: Add binding for ADIN1100 Ethernet PHY
Changelog V2 -> V3:
- removed unused defines
- dropped 1 V 2.4 V voltage link entries (will add these features in a separate patch)
- dropped extra PHY stats, will add them in a separate patch
(adin1200/1300 will need rework too as it implements same stats)
- added PMA status register and PCS control register in mdio.h (registers specified in 802.3gc)
- added auto-negotiation advertisement and link partner registers in mdio.h
(Registers specified in 802.3 2018)
- added 10base-t1l-2.4vpp tristate property to ethernet-phy yaml
- replaced standard registers defines in adin1100.c with the ones added to mdio.h
.../devicetree/bindings/net/adi,adin1100.yaml | 30 ++
.../devicetree/bindings/net/ethernet-phy.yaml | 9 +
drivers/net/phy/Kconfig | 7 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/adin1100.c | 403 ++++++++++++++++++
drivers/net/phy/phy-core.c | 3 +-
include/uapi/linux/ethtool.h | 1 +
include/uapi/linux/mdio.h | 56 +++
net/ethtool/common.c | 3 +
9 files changed, 512 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/net/adi,adin1100.yaml
create mode 100644 drivers/net/phy/adin1100.c
--
2.25.1
From: Alexandru Tachici <[email protected]>
Add entry for the 10base-T1L full duplex mode.
Signed-off-by: Alexandru Tachici <[email protected]>
---
drivers/net/phy/phy-core.c | 3 ++-
include/uapi/linux/ethtool.h | 1 +
net/ethtool/common.c | 3 +++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 2870c33b8975..ed137c295a3d 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 93,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
"If a speed or mode has been added please update phy_speed_to_str "
"and the PHY settings array.\n");
@@ -176,6 +176,7 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index b6db6590baf0..2cdbd55566d6 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1661,6 +1661,7 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index c63e0739dc6a..cbc2393a121b 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -200,6 +200,7 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(400000, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
@@ -235,6 +236,7 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
#define __LINK_MODE_LANES_T1 1
#define __LINK_MODE_LANES_X 1
#define __LINK_MODE_LANES_FX 1
+#define __LINK_MODE_LANES_T1L 1
#define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex) \
[ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = { \
@@ -348,6 +350,7 @@ const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);
--
2.25.1
From: Alexandru Tachici <[email protected]>
Added BASE-T1 AN advertisement register (Registers 7.514, 7.515, and
7.516) and BASE-T1 AN LP Base Page ability register (Registers 7.517,
7.518, and 7.519).
Signed-off-by: Alexandru Tachici <[email protected]>
---
include/uapi/linux/mdio.h | 40 +++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 8ae82fe3aece..58ac5cdf7eb4 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -67,6 +67,14 @@
#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
#define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
#define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
+#define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */
+#define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */
+#define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
+#define MDIO_AN_T1_ADV_M 515 /* BASE-T1 AN advertisement register [31:16] */
+#define MDIO_AN_T1_ADV_H 516 /* BASE-T1 AN advertisement register [47:32] */
+#define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP's base page register [15:0] */
+#define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP's base page register [31:16] */
+#define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP's base page register [47:32] */
/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
@@ -278,6 +286,38 @@
#define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */
#define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */
+/* BASE-T1 auto-negotiation advertisement register [15:0] */
+#define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP
+#define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM
+#define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000 /* Force Master/slave Configuration */
+#define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT
+#define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK
+#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE
+
+/* BASE-T1 auto-negotiation advertisement register [31:16] */
+#define MDIO_AN_T1_ADV_M_B10L 0x4000 /* device is compatible with 10BASE-T1L */
+#define MDIO_AN_T1_ADV_M_MST 0x0010 /* advertise master preference */
+
+/* BASE-T1 auto-negotiation advertisement register [47:32] */
+#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */
+#define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level Transmit Ability */
+
+/* BASE-T1 AN LP's base page register [15:0] */
+#define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP
+#define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM
+#define MDIO_AN_T1_LP_L_FORCE_MS 0x1000 /* LP Force Master/slave Configuration */
+#define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT
+#define MDIO_AN_T1_LP_L_ACK LPA_LPACK
+#define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE
+
+/* BASE-T1 AN LP's base page register [31:16] */
+#define MDIO_AN_T1_LP_M_MST 0x0080 /* LP master preference */
+#define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */
+
+/* BASE-T1 AN LP's base page register [47:32] */
+#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
+#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
+
/* EEE Supported/Advertisement/LP Advertisement registers.
*
* EEE capability Register (3.20), Advertisement (7.60) and
--
2.25.1
From: Alexandru Ardelean <[email protected]>
The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
industrial Ethernet applications and is compliant with the IEEE 802.3cg
Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.
Signed-off-by: Alexandru Ardelean <[email protected]>
Signed-off-by: Alexandru Tachici <[email protected]>
---
drivers/net/phy/Kconfig | 7 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/adin1100.c | 279 +++++++++++++++++++++++++++++++++++++
3 files changed, 287 insertions(+)
create mode 100644 drivers/net/phy/adin1100.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 902495afcb38..2f65d39e0f2c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -83,6 +83,13 @@ config ADIN_PHY
- ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
Ethernet PHY
+config ADIN1100_PHY
+ tristate "Analog Devices Industrial Ethernet T1L PHYs"
+ help
+ Adds support for the Analog Devices Industrial T1L Ethernet PHYs.
+ Currently supports the:
+ - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
+
config AQUANTIA_PHY
tristate "Aquantia PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index b2728d00fc9a..b82651b57043 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -31,6 +31,7 @@ sfp-obj-$(CONFIG_SFP) += sfp-bus.o
obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
+obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_AMD_PHY) += amd.o
aquantia-objs += aquantia_main.o
ifdef CONFIG_HWMON
diff --git a/drivers/net/phy/adin1100.c b/drivers/net/phy/adin1100.c
new file mode 100644
index 000000000000..dc5c1987dc43
--- /dev/null
+++ b/drivers/net/phy/adin1100.c
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Driver for Analog Devices Industrial Ethernet T1L PHYs
+ *
+ * Copyright 2020 Analog Devices Inc.
+ */
+#include <linux/kernel.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/phy.h>
+#include <linux/property.h>
+
+#define PHY_ID_ADIN1100 0x0283bc81
+
+static const int phy_10_features_array[] = {
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+};
+
+#define ADIN_CRSM_SFT_RST 0x8810
+#define ADIN_CRSM_SFT_RST_EN BIT(0)
+
+#define ADIN_CRSM_SFT_PD_CNTRL 0x8812
+#define ADIN_CRSM_SFT_PD_CNTRL_EN BIT(0)
+
+#define ADIN_CRSM_STAT 0x8818
+#define ADIN_CRSM_SFT_PD_RDY BIT(1)
+#define ADIN_CRSM_SYS_RDY BIT(0)
+
+/**
+ * struct adin_priv - ADIN PHY driver private data
+ * tx_level_2v4_able set if the PHY supports 2.4V TX levels (10BASE-T1L)
+ * tx_level_2v4 set if the PHY requests 2.4V TX levels (10BASE-T1L)
+ * tx_level_prop_present set if the TX level is specified in DT
+ */
+struct adin_priv {
+ unsigned int tx_level_2v4_able:1;
+ unsigned int tx_level_2v4:1;
+ unsigned int tx_level_prop_present:1;
+};
+
+static void adin_mii_adv_m_to_ethtool_adv_t(unsigned long *advertising, u32 adv)
+{
+ if (adv & MDIO_AN_T1_ADV_M_B10L)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, advertising);
+}
+
+static int adin_read_lpa(struct phy_device *phydev)
+{
+ int val;
+
+ linkmode_zero(phydev->lp_advertising);
+
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
+ if (val < 0)
+ return val;
+
+ if (!(val & MDIO_AN_STAT1_COMPLETE)) {
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ return 0;
+ }
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->lp_advertising);
+
+ /* Read the link partner's base page advertisement */
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
+ if (val < 0)
+ return val;
+
+ phydev->pause = val & MDIO_AN_T1_LP_L_PAUSE_CAP ? 1 : 0;
+ phydev->asym_pause = val & MDIO_AN_T1_LP_L_PAUSE_ASYM ? 1 : 0;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
+ if (val < 0)
+ return val;
+
+ adin_mii_adv_m_to_ethtool_adv_t(phydev->lp_advertising, val);
+
+ return 0;
+}
+
+static int adin_read_status(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = genphy_c45_read_link(phydev);
+ if (ret)
+ return ret;
+
+ phydev->speed = SPEED_UNKNOWN;
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (phydev->autoneg == AUTONEG_ENABLE) {
+ ret = adin_read_lpa(phydev);
+ if (ret)
+ return ret;
+
+ phy_resolve_aneg_linkmode(phydev);
+ } else {
+ /* Only one mode & duplex supported */
+ linkmode_zero(phydev->lp_advertising);
+ phydev->speed = SPEED_10;
+ phydev->duplex = DUPLEX_FULL;
+ }
+
+ return ret;
+}
+
+static int adin_config_aneg(struct phy_device *phydev)
+{
+ struct adin_priv *priv = phydev->priv;
+ int ret;
+
+ /* No sense to continue if auto-neg is disabled,
+ * only one link-mode supported.
+ */
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ return 0;
+
+ /* Request increased transmit level from LP. */
+ if (priv->tx_level_prop_present && priv->tx_level_2v4) {
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
+ MDIO_AN_T1_ADV_H_10L_TX_HI |
+ MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Disable 2.4 Vpp transmit level. */
+ if ((priv->tx_level_prop_present && !priv->tx_level_2v4) || !priv->tx_level_2v4_able) {
+ ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
+ MDIO_AN_T1_ADV_H_10L_TX_HI |
+ MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
+ if (ret < 0)
+ return ret;
+ }
+
+ return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_CTRL, BMCR_ANRESTART);
+}
+
+static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)
+{
+ int ret;
+ int val;
+
+ if (en)
+ val = ADIN_CRSM_SFT_PD_CNTRL_EN;
+ else
+ val = 0;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ ADIN_CRSM_SFT_PD_CNTRL, val);
+ if (ret < 0)
+ return ret;
+
+ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
+ (ret & ADIN_CRSM_SFT_PD_RDY) == val,
+ 1000, 30000, true);
+}
+
+static int adin_suspend(struct phy_device *phydev)
+{
+ return adin_set_powerdown_mode(phydev, true);
+}
+
+static int adin_resume(struct phy_device *phydev)
+{
+ return adin_set_powerdown_mode(phydev, false);
+}
+
+static int adin_set_loopback(struct phy_device *phydev, bool enable)
+{
+ if (enable)
+ return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
+ BMCR_LOOPBACK);
+
+ /* PCS loopback (according to 10BASE-T1L spec) */
+ return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
+ BMCR_LOOPBACK);
+}
+
+static int adin_soft_reset(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
+ if (ret < 0)
+ return ret;
+
+ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
+ (ret & ADIN_CRSM_SYS_RDY),
+ 10000, 30000, true);
+}
+
+static int adin_get_features(struct phy_device *phydev)
+{
+ struct adin_priv *priv = phydev->priv;
+ struct device *dev = &phydev->mdio.dev;
+ int ret;
+ u8 val;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
+ if (ret < 0)
+ return ret;
+
+ /* This depends on the voltage level from the power source */
+ priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);
+
+ phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",
+ priv->tx_level_2v4_able ? "yes" : "no");
+
+ priv->tx_level_prop_present = device_property_present(dev, "10base-t1l-2.4vpp");
+ if (priv->tx_level_prop_present) {
+ ret = device_property_read_u8(dev, "10base-t1l-2.4vpp", &val);
+ if (ret < 0)
+ return ret;
+
+ priv->tx_level_2v4 = val;
+ if (!priv->tx_level_2v4 && priv->tx_level_2v4_able)
+ phydev_info(phydev,
+ "PHY supports 2.4V TX level, but disabled via config\n");
+ }
+
+ linkmode_set_bit_array(phy_basic_ports_array, ARRAY_SIZE(phy_basic_ports_array),
+ phydev->supported);
+
+ linkmode_set_bit_array(phy_10_features_array, ARRAY_SIZE(phy_10_features_array),
+ phydev->supported);
+
+ return 0;
+}
+
+static int adin_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct adin_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static struct phy_driver adin_driver[] = {
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100),
+ .name = "ADIN1100",
+ .get_features = adin_get_features,
+ .soft_reset = adin_soft_reset,
+ .probe = adin_probe,
+ .config_aneg = adin_config_aneg,
+ .read_status = adin_read_status,
+ .set_loopback = adin_set_loopback,
+ .suspend = adin_suspend,
+ .resume = adin_resume,
+ },
+};
+
+module_phy_driver(adin_driver);
+
+static struct mdio_device_id __maybe_unused adin_tbl[] = {
+ { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, adin_tbl);
+MODULE_DESCRIPTION("Analog Devices Industrial Ethernet T1L PHY driver");
+MODULE_LICENSE("Dual BSD/GPL");
--
2.25.1
On Mon, 11 Oct 2021 17:22:11 +0300 [email protected] wrote:
> +/**
> + * struct adin_priv - ADIN PHY driver private data
> + * tx_level_2v4_able set if the PHY supports 2.4V TX levels (10BASE-T1L)
> + * tx_level_2v4 set if the PHY requests 2.4V TX levels (10BASE-T1L)
> + * tx_level_prop_present set if the TX level is specified in DT
> + */
This is not correct kdoc format. Should be
* @member: description
scripts/kernel-doc -none is your friend:
drivers/net/phy/adin1100.c:44: warning: Function parameter or member 'tx_level_2v4_able' not described in 'adin_priv'
drivers/net/phy/adin1100.c:44: warning: Function parameter or member 'tx_level_2v4' not described in 'adin_priv'
drivers/net/phy/adin1100.c:44: warning: Function parameter or member 'tx_level_prop_present' not described in 'adin_priv'
On Mon, Oct 11, 2021 at 05:22:10PM +0300, [email protected] wrote:
> From: Alexandru Tachici <[email protected]>
>
> Added BASE-T1 AN advertisement register (Registers 7.514, 7.515, and
> 7.516) and BASE-T1 AN LP Base Page ability register (Registers 7.517,
> 7.518, and 7.519).
>
> Signed-off-by: Alexandru Tachici <[email protected]>
> ---
> include/uapi/linux/mdio.h | 40 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
> index 8ae82fe3aece..58ac5cdf7eb4 100644
> --- a/include/uapi/linux/mdio.h
> +++ b/include/uapi/linux/mdio.h
> @@ -67,6 +67,14 @@
> #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
> #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
> #define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
> +#define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */
> +#define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */
> +#define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
> +#define MDIO_AN_T1_ADV_M 515 /* BASE-T1 AN advertisement register [31:16] */
> +#define MDIO_AN_T1_ADV_H 516 /* BASE-T1 AN advertisement register [47:32] */
> +#define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP's base page register [15:0] */
> +#define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP's base page register [31:16] */
> +#define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP's base page register [47:32] */
Please use same wording as in the spec: "BASE-T1 AN LP Base Page ability
register".
> /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
> #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
> @@ -278,6 +286,38 @@
> #define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */
> #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */
>
> +/* BASE-T1 auto-negotiation advertisement register [15:0] */
> +#define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP
> +#define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM
> +#define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000 /* Force Master/slave Configuration */
> +#define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT
> +#define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK
> +#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE
> +
> +/* BASE-T1 auto-negotiation advertisement register [31:16] */
> +#define MDIO_AN_T1_ADV_M_B10L 0x4000 /* device is compatible with 10BASE-T1L */
> +#define MDIO_AN_T1_ADV_M_MST 0x0010 /* advertise master preference */
Hm.. MDIO_AN_T1_ADV_M_MST is T4 of Link codeword Base Page. The spec says:
"Transmitted Nonce Field (T[4:0]) is a 5-bit wide field whose lower 4
bits contains a random or pseudorandom number. A new value shall be
generated for each entry to the Ability Detect state"
Should we actually do it?
> +/* BASE-T1 auto-negotiation advertisement register [47:32] */
> +#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */
> +#define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level Transmit Ability */
> +
> +/* BASE-T1 AN LP's base page register [15:0] */
> +#define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP
> +#define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM
> +#define MDIO_AN_T1_LP_L_FORCE_MS 0x1000 /* LP Force Master/slave Configuration */
> +#define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT
> +#define MDIO_AN_T1_LP_L_ACK LPA_LPACK
> +#define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE
> +
> +/* BASE-T1 AN LP's base page register [31:16] */
> +#define MDIO_AN_T1_LP_M_MST 0x0080 /* LP master preference */
0x0080 is A2 == 1000BASE-T1 ability. Not master preference (T4).
> +#define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */
> +
> +/* BASE-T1 AN LP's base page register [47:32] */
> +#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
> +#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
> +
> /* EEE Supported/Advertisement/LP Advertisement registers.
> *
> * EEE capability Register (3.20), Advertisement (7.60) and
> --
> 2.25.1
>
>
Regards,
Oleksij
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Mon, Oct 11, 2021 at 05:22:08PM +0300, [email protected] wrote:
> From: Alexandru Tachici <[email protected]>
>
> Add entry for the 10base-T1L full duplex mode.
>
> Signed-off-by: Alexandru Tachici <[email protected]>
Reviewed-by: Oleksij Rempel <[email protected]>
> ---
> drivers/net/phy/phy-core.c | 3 ++-
> include/uapi/linux/ethtool.h | 1 +
> net/ethtool/common.c | 3 +++
> 3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
> index 2870c33b8975..ed137c295a3d 100644
> --- a/drivers/net/phy/phy-core.c
> +++ b/drivers/net/phy/phy-core.c
> @@ -13,7 +13,7 @@
> */
> const char *phy_speed_to_str(int speed)
> {
> - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
> + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 93,
> "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
> "If a speed or mode has been added please update phy_speed_to_str "
> "and the PHY settings array.\n");
> @@ -176,6 +176,7 @@ static const struct phy_setting settings[] = {
> /* 10M */
> PHY_SETTING( 10, FULL, 10baseT_Full ),
> PHY_SETTING( 10, HALF, 10baseT_Half ),
> + PHY_SETTING( 10, FULL, 10baseT1L_Full ),
> };
> #undef PHY_SETTING
>
> diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
> index b6db6590baf0..2cdbd55566d6 100644
> --- a/include/uapi/linux/ethtool.h
> +++ b/include/uapi/linux/ethtool.h
> @@ -1661,6 +1661,7 @@ enum ethtool_link_mode_bit_indices {
> ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
> ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
> ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
> + ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,
> /* must be last entry */
> __ETHTOOL_LINK_MODE_MASK_NBITS
> };
> diff --git a/net/ethtool/common.c b/net/ethtool/common.c
> index c63e0739dc6a..cbc2393a121b 100644
> --- a/net/ethtool/common.c
> +++ b/net/ethtool/common.c
> @@ -200,6 +200,7 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
> __DEFINE_LINK_MODE_NAME(400000, CR4, Full),
> __DEFINE_LINK_MODE_NAME(100, FX, Half),
> __DEFINE_LINK_MODE_NAME(100, FX, Full),
> + __DEFINE_LINK_MODE_NAME(10, T1L, Full),
> };
> static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
>
> @@ -235,6 +236,7 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
> #define __LINK_MODE_LANES_T1 1
> #define __LINK_MODE_LANES_X 1
> #define __LINK_MODE_LANES_FX 1
> +#define __LINK_MODE_LANES_T1L 1
>
> #define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex) \
> [ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = { \
> @@ -348,6 +350,7 @@ const struct link_mode_info link_mode_params[] = {
> __DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
> __DEFINE_LINK_MODE_PARAMS(100, FX, Half),
> __DEFINE_LINK_MODE_PARAMS(100, FX, Full),
> + __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
> };
> static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);
>
> --
> 2.25.1
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Mon, Oct 11, 2021 at 05:22:11PM +0300, [email protected] wrote:
> From: Alexandru Ardelean <[email protected]>
>
> The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
> industrial Ethernet applications and is compliant with the IEEE 802.3cg
> Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.
>
> Signed-off-by: Alexandru Ardelean <[email protected]>
> Signed-off-by: Alexandru Tachici <[email protected]>
> ---
> drivers/net/phy/Kconfig | 7 +
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/adin1100.c | 279 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 287 insertions(+)
> create mode 100644 drivers/net/phy/adin1100.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 902495afcb38..2f65d39e0f2c 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -83,6 +83,13 @@ config ADIN_PHY
> - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
> Ethernet PHY
>
> +config ADIN1100_PHY
> + tristate "Analog Devices Industrial Ethernet T1L PHYs"
> + help
> + Adds support for the Analog Devices Industrial T1L Ethernet PHYs.
> + Currently supports the:
> + - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
> +
> config AQUANTIA_PHY
> tristate "Aquantia PHYs"
> help
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index b2728d00fc9a..b82651b57043 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -31,6 +31,7 @@ sfp-obj-$(CONFIG_SFP) += sfp-bus.o
> obj-y += $(sfp-obj-y) $(sfp-obj-m)
>
> obj-$(CONFIG_ADIN_PHY) += adin.o
> +obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
> obj-$(CONFIG_AMD_PHY) += amd.o
> aquantia-objs += aquantia_main.o
> ifdef CONFIG_HWMON
> diff --git a/drivers/net/phy/adin1100.c b/drivers/net/phy/adin1100.c
> new file mode 100644
> index 000000000000..dc5c1987dc43
> --- /dev/null
> +++ b/drivers/net/phy/adin1100.c
> @@ -0,0 +1,279 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Driver for Analog Devices Industrial Ethernet T1L PHYs
> + *
> + * Copyright 2020 Analog Devices Inc.
> + */
> +#include <linux/kernel.h>
> +#include <linux/bitfield.h>
> +#include <linux/delay.h>
> +#include <linux/errno.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/mii.h>
> +#include <linux/phy.h>
> +#include <linux/property.h>
> +
> +#define PHY_ID_ADIN1100 0x0283bc81
> +
> +static const int phy_10_features_array[] = {
> + ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
> +};
> +
> +#define ADIN_CRSM_SFT_RST 0x8810
> +#define ADIN_CRSM_SFT_RST_EN BIT(0)
> +
> +#define ADIN_CRSM_SFT_PD_CNTRL 0x8812
> +#define ADIN_CRSM_SFT_PD_CNTRL_EN BIT(0)
> +
> +#define ADIN_CRSM_STAT 0x8818
> +#define ADIN_CRSM_SFT_PD_RDY BIT(1)
> +#define ADIN_CRSM_SYS_RDY BIT(0)
> +
> +/**
> + * struct adin_priv - ADIN PHY driver private data
> + * tx_level_2v4_able set if the PHY supports 2.4V TX levels (10BASE-T1L)
> + * tx_level_2v4 set if the PHY requests 2.4V TX levels (10BASE-T1L)
> + * tx_level_prop_present set if the TX level is specified in DT
> + */
> +struct adin_priv {
> + unsigned int tx_level_2v4_able:1;
> + unsigned int tx_level_2v4:1;
> + unsigned int tx_level_prop_present:1;
> +};
> +
> +static void adin_mii_adv_m_to_ethtool_adv_t(unsigned long *advertising, u32 adv)
> +{
> + if (adv & MDIO_AN_T1_ADV_M_B10L)
> + linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, advertising);
> +}
Please extend genphy_c45_pma_read_abilities() to set 10baseT1L_Full_BIT.
It is already doing most of needed work:
..
if (val & MDIO_PMA_STAT2_EXTABLE) {
val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
// This is 45.2.1.10 PMA/PMD extended ability register (Register 1.11)
// You should test for bit 1.11.11 and read register register 1.18
// to set missing abilities.
> +static int adin_read_lpa(struct phy_device *phydev)
> +{
> + int val;
> +
> + linkmode_zero(phydev->lp_advertising);
> +
> + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
> + if (val < 0)
> + return val;
> +
> + if (!(val & MDIO_AN_STAT1_COMPLETE)) {
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> +
> + return 0;
> + }
> +
> + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
> + phydev->lp_advertising);
> +
> + /* Read the link partner's base page advertisement */
> + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
> + if (val < 0)
> + return val;
> +
> + phydev->pause = val & MDIO_AN_T1_LP_L_PAUSE_CAP ? 1 : 0;
> + phydev->asym_pause = val & MDIO_AN_T1_LP_L_PAUSE_ASYM ? 1 : 0;
> +
> + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
> + if (val < 0)
> + return val;
> +
> + adin_mii_adv_m_to_ethtool_adv_t(phydev->lp_advertising, val);
> +
> + return 0;
> +}
> +
> +static int adin_read_status(struct phy_device *phydev)
> +{
> + int ret;
> +
> + ret = genphy_c45_read_link(phydev);
> + if (ret)
> + return ret;
> +
> + phydev->speed = SPEED_UNKNOWN;
> + phydev->duplex = DUPLEX_UNKNOWN;
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> +
> + if (phydev->autoneg == AUTONEG_ENABLE) {
> + ret = adin_read_lpa(phydev);
> + if (ret)
> + return ret;
> +
> + phy_resolve_aneg_linkmode(phydev);
> + } else {
> + /* Only one mode & duplex supported */
> + linkmode_zero(phydev->lp_advertising);
> + phydev->speed = SPEED_10;
> + phydev->duplex = DUPLEX_FULL;
> + }
> +
> + return ret;
> +}
> +
> +static int adin_config_aneg(struct phy_device *phydev)
> +{
> + struct adin_priv *priv = phydev->priv;
> + int ret;
> +
> + /* No sense to continue if auto-neg is disabled,
> + * only one link-mode supported.
> + */
> + if (phydev->autoneg == AUTONEG_DISABLE)
> + return 0;
> +
> + /* Request increased transmit level from LP. */
> + if (priv->tx_level_prop_present && priv->tx_level_2v4) {
> + ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
> + MDIO_AN_T1_ADV_H_10L_TX_HI |
> + MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /* Disable 2.4 Vpp transmit level. */
> + if ((priv->tx_level_prop_present && !priv->tx_level_2v4) || !priv->tx_level_2v4_able) {
> + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
> + MDIO_AN_T1_ADV_H_10L_TX_HI |
> + MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
> + if (ret < 0)
> + return ret;
> + }
> +
> + return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_CTRL, BMCR_ANRESTART);
> +}
>
> +static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)
> +{
> + int ret;
> + int val;
> +
> + if (en)
> + val = ADIN_CRSM_SFT_PD_CNTRL_EN;
> + else
> + val = 0;
> +
> + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
> + ADIN_CRSM_SFT_PD_CNTRL, val);
> + if (ret < 0)
> + return ret;
> +
> + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
> + (ret & ADIN_CRSM_SFT_PD_RDY) == val,
> + 1000, 30000, true);
> +}
> +
> +static int adin_suspend(struct phy_device *phydev)
> +{
> + return adin_set_powerdown_mode(phydev, true);
> +}
> +
> +static int adin_resume(struct phy_device *phydev)
> +{
> + return adin_set_powerdown_mode(phydev, false);
> +}
> +
> +static int adin_set_loopback(struct phy_device *phydev, bool enable)
> +{
> + if (enable)
> + return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
> + BMCR_LOOPBACK);
> +
> + /* PCS loopback (according to 10BASE-T1L spec) */
> + return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
> + BMCR_LOOPBACK);
> +}
> +
> +static int adin_soft_reset(struct phy_device *phydev)
> +{
> + int ret;
> +
> + ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
> + if (ret < 0)
> + return ret;
> +
> + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
> + (ret & ADIN_CRSM_SYS_RDY),
> + 10000, 30000, true);
> +}
> +
> +static int adin_get_features(struct phy_device *phydev)
> +{
> + struct adin_priv *priv = phydev->priv;
> + struct device *dev = &phydev->mdio.dev;
> + int ret;
> + u8 val;
> +
> + ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
> + if (ret < 0)
> + return ret;
> +
> + /* This depends on the voltage level from the power source */
> + priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);
> +
> + phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",
> + priv->tx_level_2v4_able ? "yes" : "no");
> +
> + priv->tx_level_prop_present = device_property_present(dev, "10base-t1l-2.4vpp");
> + if (priv->tx_level_prop_present) {
> + ret = device_property_read_u8(dev, "10base-t1l-2.4vpp", &val);
> + if (ret < 0)
> + return ret;
> +
> + priv->tx_level_2v4 = val;
> + if (!priv->tx_level_2v4 && priv->tx_level_2v4_able)
> + phydev_info(phydev,
> + "PHY supports 2.4V TX level, but disabled via config\n");
> + }
> +
> + linkmode_set_bit_array(phy_basic_ports_array, ARRAY_SIZE(phy_basic_ports_array),
> + phydev->supported);
> +
> + linkmode_set_bit_array(phy_10_features_array, ARRAY_SIZE(phy_10_features_array),
> + phydev->supported);
> +
> + return 0;
> +}
> +
> +static int adin_probe(struct phy_device *phydev)
> +{
> + struct device *dev = &phydev->mdio.dev;
> + struct adin_priv *priv;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + phydev->priv = priv;
> +
> + return 0;
> +}
> +
Without spending too much time on review right now, I would expect that
most of this code should got to the drivers/net/phy/phy-c45.c
> +static struct phy_driver adin_driver[] = {
> + {
> + PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100),
> + .name = "ADIN1100",
> + .get_features = adin_get_features,
> + .soft_reset = adin_soft_reset,
> + .probe = adin_probe,
> + .config_aneg = adin_config_aneg,
> + .read_status = adin_read_status,
> + .set_loopback = adin_set_loopback,
> + .suspend = adin_suspend,
> + .resume = adin_resume,
> + },
> +};
> +
> +module_phy_driver(adin_driver);
> +
> +static struct mdio_device_id __maybe_unused adin_tbl[] = {
> + { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },
> + { }
> +};
> +
> +MODULE_DEVICE_TABLE(mdio, adin_tbl);
> +MODULE_DESCRIPTION("Analog Devices Industrial Ethernet T1L PHY driver");
> +MODULE_LICENSE("Dual BSD/GPL");
> --
> 2.25.1
>
Regards,
Oleksij
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> Hm.. MDIO_AN_T1_ADV_M_MST is T4 of Link codeword Base Page. The spec says:
> "Transmitted Nonce Field (T[4:0]) is a 5-bit wide field whose lower 4
> bits contains a random or pseudorandom number. A new value shall be
> generated for each entry to the Ability Detect state"
>
> Should we actually do it?
Managed to get some answears from the HW team:
Bits 7.515.3:0 correspond to the lower 4 bits of the Transmitted Nonce Field. We do not allow users to write these bits as they need to be controlled by the auto-negotiation (AN) sequencers in order to ensure that AN remains robust and reliable. However, the Transmitted Nonce value is readable via register 7.515. So we could call these bits out in the documentation and indicate that they are readonly.
Bottom line is that the driver cannot and should not do anything with the lower 4 Transmitted Nonce bits. The PHY controls them.
Also from 802.3 98.2.1.2.3 Transmitted Nonce Field:
If the device has received a DME page with good CRC16 and the link partner has a Transmitted Nonce Field
(T[4:0]) that matches the devices generated T[4:0], the device shall invert its T[0] bit and regenerate a new
random value for T[3:1] and use that as its new T[4:0] value. Since the DME pages are exchanged in a halfduplex manner, it is possible to swap to a new T[4:0] value prior to transmitting the DME page. One device
will always see a DME page with good CRC16 before the other device hence this swapping will guarantee
that nonce_match will never be true.
Seems that there must be hardware to deal with nonce collisions.
Regards,
Alexandru