Changelog v1 -> v2:
- https://lore.kernel.org/all/[email protected]
- Order compatilbe in alphabetic order
- Fix comments in yaml
- Grup struct by types
- Drop usless "if (err)"
- Handle error in ad3552r_read_reg_wrapper
- ad3552r_find_range: u32 -> s32
- Add fwnode_handle_put(custom_gain_child); in good path too
- Vals[0] -> val
- Fix: fwnode_handle_put in ad3552r_configure_device
- Fix indio_dev->name
- Rename custom_gain_child -> gain_child
- Remove intermediary functions and write code inline where possible
- Add ad3552r_field_prep helper function
- Dev_err -> dev_warn for vref supply check
- Replace dev_err with dev_err_probe
- Remove channel for simultaneous update and do update mask register if both
channels values are the same.
Changelog v0 -> v1:
- Split https://lore.kernel.org/all/[email protected]
and move ad3552r driver to this serie.
- Remove precision_mode abi
- Remove adi,synch_channels dt property
- Use vref-supply instead of adi,vref-select
- Remove unimplemented spi modes
- Change output-range format and use enums
- Update description for custom-output-range-config to be more clear
- Add datasheet tag
- Use GENMASK for defines
- Remove tomicro define
- Use get_unaligned_be16 and put_unaligned_be16
- Remove unnecessary checks
- Add comment for AD3552R_CH_DAC_PAGE channel
- Fix indent
- Remove irq trigger
- Remove irelevant checks
- Rename ad3552r_read_reg_pool to ad3552r_read_reg_wrapper.
- Add support for ad3542r
V0:
* Add ad3552r example to https://lore.kernel.org/linux-iio/[email protected]
Mihail Chindris (2):
dt-bindings: iio: dac: Add adi,ad3552r.yaml
drivers:iio:dac: Add AD3552R driver support
.../bindings/iio/dac/adi,ad3552r.yaml | 190 +++
drivers/iio/dac/Kconfig | 10 +
drivers/iio/dac/Makefile | 1 +
drivers/iio/dac/ad3552r.c | 1208 +++++++++++++++++
4 files changed, 1409 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
create mode 100644 drivers/iio/dac/ad3552r.c
base-commit: ef226dcf3d88697a06335fbc55c4263ab164b135
--
2.27.0
Add documentation for ad3552r
Signed-off-by: Mihail Chindris <[email protected]>
---
.../bindings/iio/dac/adi,ad3552r.yaml | 190 ++++++++++++++++++
1 file changed, 190 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
new file mode 100644
index 000000000000..c6999bb4c7a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
@@ -0,0 +1,190 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ad3552r.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD2552R DAC device driver
+
+maintainers:
+ - Mihail Chindris <[email protected]>
+
+description: |
+ Bindings for the Analog Devices AD3552R DAC device and similar.
+ Datasheet can be found here:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad3542r.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad3552r.pdf
+properties:
+ compatible:
+ enum:
+ - adi,ad3542r
+ - adi,ad3552r
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 30000000
+
+ reset-gpios:
+ maxItems: 1
+
+ ldac-gpios:
+ description: |
+ LDAC pin to be used as a hardware trigger to update the DAC channels.
+ maxItems: 1
+
+ vref-supply:
+ description:
+ The regulator to use as an external reference. If it does not exists the
+ internal reference will be used. External reference must be 2.5V
+
+ adi,vref-out-en:
+ description: Vref I/O driven by internal vref to 2.5V. If not set, Vref pin
+ will be floating.
+ type: boolean
+
+ adi,sdo-drive-strength:
+ description: |
+ Configure SDIO0 and SDIO1 strength levels:
+ - 0: low SDO drive strength.
+ - 1: medium low SDO drive strength.
+ - 2: medium high SDO drive strength.
+ - 3: high SDO drive strength
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+
+patternProperties:
+ "^channel@([0-1])$":
+ type: object
+ description: Configurations of the DAC Channels
+ properties:
+ reg:
+ description: Channel number
+ enum: [0, 1]
+
+ custom-output-range-config:
+ type: object
+ description: Configuration of custom range when
+ adi,output-range-microvolt is not present.
+ The formulas for calculation the output voltages are
+ Vout_fs = 2.5 + [(GainN + Offset/1024) * 2.5 * Rfbx * 1.03]
+ Vout_zs = 2.5 - [(GainP + Offset/1024) * 2.5 * Rfbx * 1.03]
+ properties:
+ adi,gain-offset:
+ description: Gain offset used in the above formula
+ $ref: /schemas/types.yaml#/definitions/int32
+ maximum: 511
+ minimum: -511
+ adi,gain-scaling-p-inv-log2:
+ description: GainP = 1 / ( 2 ^ adi,gain-scaling-p-inv-log2)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ adi,gain-scaling-n-inv-log2:
+ description: GainN = 1 / ( 2 ^ adi,gain-scaling-n-inv-log2)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ adi,rfb-ohms:
+ description: Feedback Resistor
+ required:
+ - adi,gain-offset
+ - adi,gain-scaling-p-inv-log2
+ - adi,gain-scaling-n-inv-log2
+ - adi,rfb-ohms
+ required:
+ - reg
+
+ oneOf:
+ # If adi,output-range-microvolt is missing,
+ # custom-output-range-config must be used
+ - required:
+ - adi,output-range-microvolt
+ - required:
+ - custom-output-range-config
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,ad3542r
+ then:
+ patternProperties:
+ "^channel@([0-1])$":
+ type: object
+ properties:
+ adi,output-range-microvolt:
+ description: |
+ Voltage output range of the channel as <minimum, maximum>
+ Required connections:
+ Rfb1x for: 0 to 2.5 V; 0 to 3V; 0 to 5 V;
+ Rfb2x for: 0 to 10 V; 2.5 to 7.5V; -5 to 5 V;
+ oneOf:
+ - items:
+ - const: 0
+ - enum: [2500000, 3000000, 5000000, 10000000]
+ - items:
+ - const: -2500000
+ - const: 7500000
+ - items:
+ - const: -5000000
+ - const: 5000000
+ required:
+ - adi,output-range-microvolt
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,ad3552r
+ then:
+ patternProperties:
+ "^channel@([0-1])$":
+ type: object
+ properties:
+ adi,output-range-microvolt:
+ description: |
+ Voltage output range of the channel as <minimum, maximum>
+ Required connections:
+ Rfb1x for: 0 to 2.5 V; 0 to 5 V;
+ Rfb2x for: 0 to 10 V; -5 to 5 V;
+ Rfb4x for: -10 to 10V
+ oneOf:
+ - items:
+ - const: 0
+ - enum: [2500000, 5000000, 10000000]
+ - items:
+ - const: -5000000
+ - const: 5000000
+ - items:
+ - const: -10000000
+ - const: 10000000
+
+required:
+ - compatible
+ - reg
+ - spi-max-frequency
+
+additionalProperties: false
+
+examples:
+ - |
+ ad3552r {
+ compatible = "adi,ad3552r";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ channel@0 {
+ reg = <0>;
+ adi,output-range-microvolt = <0 10000000>;
+ };
+ channel@1 {
+ reg = <1>;
+ custom-output-range-config {
+ adi,gain-offset = <5>;
+ adi,gain-scaling-p-inv-log2 = <1>;
+ adi,gain-scaling-n-inv-log2 = <2>;
+ adi,rfb-ohms = <1>;
+ };
+ };
+ };
+...
--
2.27.0
The AD3552R-16 is a low drift ultrafast, 16-bit accuracy,
current output digital-to-analog converter (DAC) designed
to generate multiple output voltage span ranges.
The AD3552R-16 operates with a fixed 2.5V reference.
Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ad3552r.pdf
Signed-off-by: Mihail Chindris <[email protected]>
---
drivers/iio/dac/Kconfig | 10 +
drivers/iio/dac/Makefile | 1 +
drivers/iio/dac/ad3552r.c | 1208 +++++++++++++++++++++++++++++++++++++
3 files changed, 1219 insertions(+)
create mode 100644 drivers/iio/dac/ad3552r.c
diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig
index 75e1f2b48638..ced6428f2c92 100644
--- a/drivers/iio/dac/Kconfig
+++ b/drivers/iio/dac/Kconfig
@@ -6,6 +6,16 @@
menu "Digital to analog converters"
+config AD3552R
+ tristate "Analog Devices AD3552R DAC driver"
+ depends on SPI_MASTER
+ help
+ Say yes here to build support for Analog Devices AD3552R
+ Digital to Analog Converter.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ad3552r.
+
config AD5064
tristate "Analog Devices AD5064 and similar multi-channel DAC driver"
depends on (SPI_MASTER && I2C!=m) || I2C
diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile
index 33e16f14902a..dffe36efd8ff 100644
--- a/drivers/iio/dac/Makefile
+++ b/drivers/iio/dac/Makefile
@@ -4,6 +4,7 @@
#
# When adding new entries keep the list in alphabetical order
+obj-$(CONFIG_AD3552R) += ad3552r.o
obj-$(CONFIG_AD5360) += ad5360.o
obj-$(CONFIG_AD5380) += ad5380.o
obj-$(CONFIG_AD5421) += ad5421.o
diff --git a/drivers/iio/dac/ad3552r.c b/drivers/iio/dac/ad3552r.c
new file mode 100644
index 000000000000..fd70883c692e
--- /dev/null
+++ b/drivers/iio/dac/ad3552r.c
@@ -0,0 +1,1208 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Analog Devices AD3552R
+ * Digital to Analog converter driver
+ *
+ * Copyright 2021 Analog Devices Inc.
+ */
+#include <asm/unaligned.h>
+#include <linux/device.h>
+#include <linux/iio/trigger.h>
+#include <linux/iio/triggered_buffer.h>
+#include <linux/iio/trigger_consumer.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+
+/* Register addresses */
+/* Primary address space */
+#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A 0x00
+#define AD3552R_MASK_SOFTWARE_RESET (BIT(7) | BIT(0))
+#define AD3552R_MASK_ADDR_ASCENSION BIT(5)
+#define AD3552R_MASK_SDO_ACTIVE BIT(4)
+#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B 0x01
+#define AD3552R_MASK_SINGLE_INST BIT(7)
+#define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)
+#define AD3552R_REG_ADDR_DEVICE_CONFIG 0x02
+#define AD3552R_MASK_DEVICE_STATUS(n) BIT(4 + (n))
+#define AD3552R_MASK_CUSTOM_MODES GENMASK(3, 2)
+#define AD3552R_MASK_OPERATING_MODES GENMASK(1, 0)
+#define AD3552R_REG_ADDR_CHIP_TYPE 0x03
+#define AD3552R_MASK_CLASS GENMASK(7, 0)
+#define AD3552R_REG_ADDR_PRODUCT_ID_L 0x04
+#define AD3552R_REG_ADDR_PRODUCT_ID_H 0x05
+#define AD3552R_REG_ADDR_CHIP_GRADE 0x06
+#define AD3552R_MASK_GRADE GENMASK(7, 4)
+#define AD3552R_MASK_DEVICE_REVISION GENMASK(3, 0)
+#define AD3552R_REG_ADDR_SCRATCH_PAD 0x0A
+#define AD3552R_REG_ADDR_SPI_REVISION 0x0B
+#define AD3552R_REG_ADDR_VENDOR_L 0x0C
+#define AD3552R_REG_ADDR_VENDOR_H 0x0D
+#define AD3552R_REG_ADDR_STREAM_MODE 0x0E
+#define AD3552R_MASK_LENGTH GENMASK(7, 0)
+#define AD3552R_REG_ADDR_TRANSFER_REGISTER 0x0F
+#define AD3552R_MASK_MULTI_IO_MODE GENMASK(7, 6)
+#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE BIT(2)
+#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C 0x10
+#define AD3552R_MASK_CRC_ENABLE (GENMASK(7, 6) |\
+ GENMASK(1, 0))
+#define AD3552R_MASK_STRICT_REGISTER_ACCESS BIT(5)
+#define AD3552R_REG_ADDR_INTERFACE_STATUS_A 0x11
+#define AD3552R_MASK_INTERFACE_NOT_READY BIT(7)
+#define AD3552R_MASK_CLOCK_COUNTING_ERROR BIT(5)
+#define AD3552R_MASK_INVALID_OR_NO_CRC BIT(3)
+#define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER BIT(2)
+#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS BIT(1)
+#define AD3552R_MASK_REGISTER_ADDRESS_INVALID BIT(0)
+#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D 0x14
+#define AD3552R_MASK_ALERT_ENABLE_PULLUP BIT(6)
+#define AD3552R_MASK_MEM_CRC_EN BIT(4)
+#define AD3552R_MASK_SDO_DRIVE_STRENGTH GENMASK(3, 2)
+#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN BIT(1)
+#define AD3552R_MASK_SPI_CONFIG_DDR BIT(0)
+#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG 0x15
+#define AD3552R_MASK_IDUMP_FAST_MODE BIT(6)
+#define AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN BIT(5)
+#define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM GENMASK(4, 3)
+#define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE BIT(2)
+#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL GENMASK(1, 0)
+#define AD3552R_REG_ADDR_ERR_ALARM_MASK 0x16
+#define AD3552R_MASK_REF_RANGE_ALARM BIT(6)
+#define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM BIT(5)
+#define AD3552R_MASK_MEM_CRC_ERR_ALARM BIT(4)
+#define AD3552R_MASK_SPI_CRC_ERR_ALARM BIT(3)
+#define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM BIT(2)
+#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM BIT(1)
+#define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM BIT(0)
+#define AD3552R_REG_ADDR_ERR_STATUS 0x17
+#define AD3552R_MASK_REF_RANGE_ERR_STATUS BIT(6)
+#define AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS BIT(5)
+#define AD3552R_MASK_MEM_CRC_ERR_STATUS BIT(4)
+#define AD3552R_MASK_RESET_STATUS BIT(0)
+#define AD3552R_REG_ADDR_POWERDOWN_CONFIG 0x18
+#define AD3552R_MASK_CH_DAC_POWERDOWN(ch) BIT(4 + (ch))
+#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch) BIT(ch)
+#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE 0x19
+#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch) ((ch) ? GENMASK(7, 4) :\
+ GENMASK(3, 0))
+#define AD3552R_REG_ADDR_CH_OFFSET(ch) (0x1B + (ch) * 2)
+#define AD3552R_MASK_CH_OFFSET_BITS_0_7 GENMASK(7, 0)
+#define AD3552R_REG_ADDR_CH_GAIN(ch) (0x1C + (ch) * 2)
+#define AD3552R_MASK_CH_RANGE_OVERRIDE BIT(7)
+#define AD3552R_MASK_CH_GAIN_SCALING_N GENMASK(6, 5)
+#define AD3552R_MASK_CH_GAIN_SCALING_P GENMASK(4, 3)
+#define AD3552R_MASK_CH_OFFSET_POLARITY BIT(2)
+#define AD3552R_MASK_CH_OFFSET_BIT_8 BIT(0)
+/*
+ * Secondary region
+ * For multibyte registers specify the highest address because the access is
+ * done in descending order
+ */
+#define AD3552R_SECONDARY_REGION_START 0x28
+#define AD3552R_REG_ADDR_HW_LDAC_16B 0x28
+#define AD3552R_REG_ADDR_CH_DAC_16B(ch) (0x2C - (1 - ch) * 2)
+#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B 0x2E
+#define AD3552R_REG_ADDR_CH_SELECT_16B 0x2F
+#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B 0x31
+#define AD3552R_REG_ADDR_SW_LDAC_16B 0x32
+#define AD3552R_REG_ADDR_CH_INPUT_16B(ch) (0x36 - (1 - ch) * 2)
+/* 3 bytes registers */
+#define AD3552R_REG_START_24B 0x37
+#define AD3552R_REG_ADDR_HW_LDAC_24B 0x37
+#define AD3552R_REG_ADDR_CH_DAC_24B(ch) (0x3D - (1 - ch) * 3)
+#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B 0x40
+#define AD3552R_REG_ADDR_CH_SELECT_24B 0x41
+#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B 0x44
+#define AD3552R_REG_ADDR_SW_LDAC_24B 0x45
+#define AD3552R_REG_ADDR_CH_INPUT_24B(ch) (0x4B - (1 - ch) * 3)
+
+/* Useful defines */
+#define AD3552R_NUM_CH 2
+#define AD3552R_MASK_CH(ch) BIT(ch)
+#define AD3552R_MASK_ALL_CH GENMASK(1, 0)
+#define AD3552R_MAX_REG_SIZE 3
+#define AD3552R_READ_BIT (1 << 7)
+#define AD3552R_ADDR_MASK GENMASK(6, 0)
+#define AD3552R_CRC_ENABLE_VALUE (BIT(6) | BIT(1))
+#define AD3552R_CRC_DISABLE_VALUE GENMASK(1, 0)
+#define AD3552R_CRC_POLY 0x07
+#define AD3552R_CRC_SEED 0xA5
+#define AD3552R_MASK_DAC_12B 0xFFF0
+#define AD3552R_DEFAULT_CONFIG_B_VALUE 0x8
+#define AD3552R_SCRATCH_PAD_TEST_VAL1 0x34
+#define AD3552R_SCRATCH_PAD_TEST_VAL2 0xB2
+#define AD3552R_GAIN_SCALE 1000
+#define AD3552R_LDAC_PULSE_US 100
+
+enum ad3552r_ch_vref_select {
+ /* Internal source with Vref I/O floating */
+ AD3552R_INTERNAL_VREF_PIN_FLOATING,
+ /* Internal source with Vref I/O at 2.5V */
+ AD3552R_INTERNAL_VREF_PIN_2P5V,
+ /* External source with Vref I/O as input */
+ AD3552R_EXTERNAL_VREF_PIN_INPUT
+};
+
+enum ad3542r_id {
+ AD3542R_ID = 0x4008,
+ AD3552R_ID = 0x4009,
+};
+
+enum ad3552r_ch_output_range {
+ /* Range from 0 V to 2.5 V. Requires Rfb1x connection */
+ AD3552R_CH_OUTPUT_RANGE_0__2P5V,
+ /* Range from 0 V to 5 V. Requires Rfb1x connection */
+ AD3552R_CH_OUTPUT_RANGE_0__5V,
+ /* Range from 0 V to 10 V. Requires Rfb2x connection */
+ AD3552R_CH_OUTPUT_RANGE_0__10V,
+ /* Range from -5 V to 5 V. Requires Rfb2x connection */
+ AD3552R_CH_OUTPUT_RANGE_NEG_5__5V,
+ /* Range from -10 V to 10 V. Requires Rfb4x connection */
+ AD3552R_CH_OUTPUT_RANGE_NEG_10__10V,
+};
+
+static const s32 ad3552r_ch_ranges[][2] = {
+ [AD3552R_CH_OUTPUT_RANGE_0__2P5V] = {0, 2500},
+ [AD3552R_CH_OUTPUT_RANGE_0__5V] = {0, 5000},
+ [AD3552R_CH_OUTPUT_RANGE_0__10V] = {0, 10000},
+ [AD3552R_CH_OUTPUT_RANGE_NEG_5__5V] = {-5000, 5000},
+ [AD3552R_CH_OUTPUT_RANGE_NEG_10__10V] = {-10000, 10000}
+};
+
+enum ad3542r_ch_output_range {
+ /* Range from 0 V to 2.5 V. Requires Rfb1x connection */
+ AD3542R_CH_OUTPUT_RANGE_0__2P5V,
+ /* Range from 0 V to 3 V. Requires Rfb1x connection */
+ AD3542R_CH_OUTPUT_RANGE_0__3V,
+ /* Range from 0 V to 5 V. Requires Rfb1x connection */
+ AD3542R_CH_OUTPUT_RANGE_0__5V,
+ /* Range from 0 V to 10 V. Requires Rfb2x connection */
+ AD3542R_CH_OUTPUT_RANGE_0__10V,
+ /* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */
+ AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V,
+ /* Range from -5 V to 5 V. Requires Rfb2x connection */
+ AD3542R_CH_OUTPUT_RANGE_NEG_5__5V,
+};
+
+static const s32 ad3542r_ch_ranges[][2] = {
+ [AD3542R_CH_OUTPUT_RANGE_0__2P5V] = {0, 2500},
+ [AD3542R_CH_OUTPUT_RANGE_0__3V] = {0, 3000},
+ [AD3542R_CH_OUTPUT_RANGE_0__5V] = {0, 5000},
+ [AD3542R_CH_OUTPUT_RANGE_0__10V] = {0, 10000},
+ [AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V] = {-2500, 7500},
+ [AD3542R_CH_OUTPUT_RANGE_NEG_5__5V] = {-5000, 5000}
+};
+
+enum ad3552r_ch_gain_scaling {
+ /* Gain scaling of 1 */
+ AD3552R_CH_GAIN_SCALING_1,
+ /* Gain scaling of 0.5 */
+ AD3552R_CH_GAIN_SCALING_0_5,
+ /* Gain scaling of 0.25 */
+ AD3552R_CH_GAIN_SCALING_0_25,
+ /* Gain scaling of 0.125 */
+ AD3552R_CH_GAIN_SCALING_0_125,
+};
+
+/* Gain * AD3552R_GAIN_SCALE */
+static const s32 gains_scaling_table[] = {
+ [AD3552R_CH_GAIN_SCALING_1] = 1000,
+ [AD3552R_CH_GAIN_SCALING_0_5] = 500,
+ [AD3552R_CH_GAIN_SCALING_0_25] = 250,
+ [AD3552R_CH_GAIN_SCALING_0_125] = 125
+};
+
+enum ad3552r_dev_attributes {
+ /* - Direct register values */
+ /* From 0-3 */
+ AD3552R_SDO_DRIVE_STRENGTH,
+ /*
+ * 0 -> Internal Vref, vref_io pin floating (default)
+ * 1 -> Internal Vref, vref_io driven by internal vref
+ * 2 or 3 -> External Vref
+ */
+ AD3552R_VREF_SELECT,
+ /* Enable / Disable CRC */
+ AD3552R_CRC_ENABLE,
+ /* Spi mode: Strandard, Dual or Quad */
+ AD3552R_SPI_MULTI_IO_MODE,
+ /* Spi data rate: Single or dual */
+ AD3552R_SPI_DATA_RATE,
+ /* Dual spi synchronous mode */
+ AD3552R_SPI_SYNCHRONOUS_ENABLE,
+
+ /* - Direct register values (Private) */
+ /* Read registers in ascending order if set. Else descending */
+ AD3552R_ADDR_ASCENSION,
+ /* Single instruction mode if set. Else, stream mode */
+ AD3552R_SINGLE_INST,
+ /* Number of addresses to loop on when stream writing. */
+ AD3552R_STREAM_MODE,
+ /* Keep stream value if set. */
+ AD3552R_STREAM_LENGTH_KEEP_VALUE,
+};
+
+enum ad3552r_ch_attributes {
+ /* DAC powerdown */
+ AD3552R_CH_DAC_POWERDOWN,
+ /* DAC amplifier powerdown */
+ AD3552R_CH_AMPLIFIER_POWERDOWN,
+ /* Select the output range. Select from enum ad3552r_ch_output_range */
+ AD3552R_CH_OUTPUT_RANGE_SEL,
+ /*
+ * Over-rider the range selector in order to manually set the output
+ * voltage range
+ */
+ AD3552R_CH_RANGE_OVERRIDE,
+ /* Manually set the offset voltage */
+ AD3552R_CH_GAIN_OFFSET,
+ /* Sets the polarity of the offset. */
+ AD3552R_CH_GAIN_OFFSET_POLARITY,
+ /* PDAC gain scaling */
+ AD3552R_CH_GAIN_SCALING_P,
+ /* NDAC gain scaling */
+ AD3552R_CH_GAIN_SCALING_N,
+ /* Trigger a software LDAC */
+ AD3552R_CH_TRIGGER_SOFTWARE_LDAC,
+ /* Hardware LDAC Mask */
+ AD3552R_CH_HW_LDAC_MASK,
+ /* Rfb value */
+ AD3552R_CH_RFB,
+ /* Channel select. When set allow Input -> DAC and Mask -> DAC */
+ AD3552R_CH_SELECT,
+};
+
+struct ad3552r_ch_data {
+ s32 scale_int;
+ s32 scale_dec;
+ s32 offset_int;
+ s32 offset_dec;
+ s16 gain_offset;
+ u16 rfb;
+ u8 n;
+ u8 p;
+ u8 range;
+ bool range_override;
+};
+
+struct ad3552r_desc {
+ /* Used to look the spi bus for atomic operations where needed */
+ struct mutex lock;
+ struct gpio_desc *gpio_reset;
+ struct gpio_desc *gpio_ldac;
+ struct spi_device *spi;
+ struct ad3552r_ch_data ch_data[AD3552R_NUM_CH];
+ struct iio_chan_spec channels[AD3552R_NUM_CH + 1];
+ unsigned long enabled_ch;
+ unsigned int num_ch;
+ enum ad3542r_id chip_id;
+ /*
+ * The maximum spi transfer size consist 1 bytes (reg address)
+ * + 2 registers of 3 bytes + 1 reg of 1 byte (SW LDAC)
+ */
+ u8 buf_data[8] ____cacheline_aligned;
+};
+
+static const u16 addr_mask_map[][2] = {
+ [AD3552R_ADDR_ASCENSION] = {
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
+ AD3552R_MASK_ADDR_ASCENSION
+ },
+ [AD3552R_SINGLE_INST] = {
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
+ AD3552R_MASK_SINGLE_INST
+ },
+ [AD3552R_STREAM_MODE] = {
+ AD3552R_REG_ADDR_STREAM_MODE,
+ AD3552R_MASK_LENGTH
+ },
+ [AD3552R_STREAM_LENGTH_KEEP_VALUE] = {
+ AD3552R_REG_ADDR_TRANSFER_REGISTER,
+ AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE
+ },
+ [AD3552R_SDO_DRIVE_STRENGTH] = {
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
+ AD3552R_MASK_SDO_DRIVE_STRENGTH
+ },
+ [AD3552R_VREF_SELECT] = {
+ AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
+ AD3552R_MASK_REFERENCE_VOLTAGE_SEL
+ },
+ [AD3552R_CRC_ENABLE] = {
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_C,
+ AD3552R_MASK_CRC_ENABLE
+ },
+ [AD3552R_SPI_MULTI_IO_MODE] = {
+ AD3552R_REG_ADDR_TRANSFER_REGISTER,
+ AD3552R_MASK_MULTI_IO_MODE
+ },
+ [AD3552R_SPI_DATA_RATE] = {
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
+ AD3552R_MASK_SPI_CONFIG_DDR
+ },
+ [AD3552R_SPI_SYNCHRONOUS_ENABLE] = {
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
+ AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN
+ },
+};
+
+/* 0 -> reg addr, 1->ch0 mask, 2->ch1 mask */
+static const u16 addr_mask_map_ch[][3] = {
+ [AD3552R_CH_DAC_POWERDOWN] = {
+ AD3552R_REG_ADDR_POWERDOWN_CONFIG,
+ AD3552R_MASK_CH_DAC_POWERDOWN(0),
+ AD3552R_MASK_CH_DAC_POWERDOWN(1)
+ },
+ [AD3552R_CH_AMPLIFIER_POWERDOWN] = {
+ AD3552R_REG_ADDR_POWERDOWN_CONFIG,
+ AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0),
+ AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1)
+ },
+ [AD3552R_CH_OUTPUT_RANGE_SEL] = {
+ AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
+ AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0),
+ AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1)
+ },
+ /*
+ * This attributes are update by the chip on 16B and 24B no matter to
+ * what register the write is done
+ */
+ [AD3552R_CH_TRIGGER_SOFTWARE_LDAC] = {
+ AD3552R_REG_ADDR_SW_LDAC_16B,
+ AD3552R_MASK_CH(0),
+ AD3552R_MASK_CH(1)
+ },
+ [AD3552R_CH_HW_LDAC_MASK] = {
+ AD3552R_REG_ADDR_HW_LDAC_16B,
+ AD3552R_MASK_CH(0),
+ AD3552R_MASK_CH(1)
+ },
+ [AD3552R_CH_SELECT] = {
+ AD3552R_REG_ADDR_CH_SELECT_16B,
+ AD3552R_MASK_CH(0),
+ AD3552R_MASK_CH(1)
+ }
+};
+
+static u8 _ad3552r_reg_len(u8 addr)
+{
+ switch (addr) {
+ case AD3552R_REG_ADDR_HW_LDAC_16B:
+ case AD3552R_REG_ADDR_CH_SELECT_16B:
+ case AD3552R_REG_ADDR_SW_LDAC_16B:
+ case AD3552R_REG_ADDR_HW_LDAC_24B:
+ case AD3552R_REG_ADDR_CH_SELECT_24B:
+ case AD3552R_REG_ADDR_SW_LDAC_24B:
+ return 1;
+ default:
+ break;
+ }
+
+ if (addr > AD3552R_REG_ADDR_HW_LDAC_24B)
+ return 3;
+ if (addr > AD3552R_REG_ADDR_HW_LDAC_16B)
+ return 2;
+
+ return 1;
+}
+
+/* SPI transfer to device */
+static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len,
+ u8 *data, bool is_read)
+{
+ u8 instr;
+
+ instr = addr & AD3552R_ADDR_MASK;
+ instr |= is_read ? AD3552R_READ_BIT : 0;
+ if (is_read)
+ return spi_write_then_read(dac->spi, &instr, 1, data, len);
+
+ dac->buf_data[0] = instr;
+ memcpy(dac->buf_data + 1, data, len);
+ return spi_write(dac->spi, dac->buf_data, len + 1);
+}
+
+static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)
+{
+ u8 reg_len;
+ u8 buf[AD3552R_MAX_REG_SIZE] = { 0 };
+
+ reg_len = _ad3552r_reg_len(addr);
+ if (reg_len == 2)
+ /* Only DAC register are 2 bytes wide */
+ val &= AD3552R_MASK_DAC_12B;
+ if (reg_len == 1)
+ buf[0] = val & 0xFF;
+ else
+ /* reg_len can be 2 or 3, but 3rd bytes needs to be set to 0 */
+ put_unaligned_be16(val, buf);
+
+ return ad3552r_transfer(dac, addr, reg_len, buf, false);
+}
+
+static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)
+{
+ int err;
+ u8 reg_len, buf[AD3552R_MAX_REG_SIZE] = { 0 };
+
+ reg_len = _ad3552r_reg_len(addr);
+ err = ad3552r_transfer(dac, addr, reg_len, buf, true);
+ if (err)
+ return err;
+
+ if (reg_len == 1)
+ *val = buf[0];
+ else
+ /* reg_len can be 2 or 3, but only first 2 bytes are relevant */
+ *val = get_unaligned_be16(buf);
+
+ return 0;
+}
+
+static u16 ad3552r_field_prep(u16 val, u16 mask)
+{
+ return (val << __ffs(mask)) & mask;
+}
+
+/* Update field of a register, shift val if needed */
+static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask,
+ u16 val)
+{
+ int ret;
+ u16 reg;
+
+ ret = ad3552r_read_reg(dac, addr, ®);
+ if (ret < 0)
+ return ret;
+
+ reg &= ~mask;
+ reg |= ad3552r_field_prep(val, mask);
+
+ return ad3552r_write_reg(dac, addr, reg);
+}
+
+static int ad3552r_write_and_trigger(struct ad3552r_desc *dac, u8 addr, u16 val,
+ u32 mask)
+{
+ int err;
+
+ err = ad3552r_write_reg(dac, addr, val);
+ if (err)
+ return err;
+
+ if (!dac->gpio_ldac) {
+ err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B,
+ mask);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data)
+{
+ int err, ch, len;
+ u8 addr, buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE + 1];
+ u16 val1, val2;
+
+ val1 = be16_to_cpu(*((u16 *)data));
+ if (mask == AD3552R_MASK_ALL_CH) {
+ val2 = be16_to_cpu(*((u16 *)(data + 2)));
+ if (val1 == val2) {
+ err = ad3552r_write_and_trigger(dac,
+ AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B,
+ val1,
+ AD3552R_MASK_ALL_CH);
+ if (err)
+ return err;
+ } else {
+ addr = AD3552R_REG_ADDR_CH_INPUT_24B(1);
+ /* CH1 */
+ buff[0] = data[2];
+ buff[1] = data[3];
+ buff[2] = 0;
+ /* CH0 */
+ buff[3] = data[0];
+ buff[4] = data[1];
+ buff[5] = 0;
+ len = 6;
+ if (!dac->gpio_ldac) {
+ /* Software LDAC */
+ buff[6] = AD3552R_MASK_ALL_CH;
+ ++len;
+ }
+ err = ad3552r_transfer(dac, addr, len, buff, false);
+ if (err)
+ return err;
+ }
+ } else {
+ ch = __ffs(mask);
+ err = ad3552r_write_and_trigger(dac,
+ AD3552R_REG_ADDR_CH_INPUT_24B(ch),
+ val1,
+ mask);
+ if (err)
+ return err;
+ }
+
+ if (dac->gpio_ldac) {
+ gpiod_set_value_cansleep(dac->gpio_ldac, 0);
+ usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10);
+ gpiod_set_value_cansleep(dac->gpio_ldac, 1);
+ }
+
+ return 0;
+}
+
+static int ad3552r_set_ch_value(struct ad3552r_desc *dac,
+ enum ad3552r_ch_attributes attr,
+ u8 ch,
+ u16 val)
+{
+ /* Update register related to attributes in chip */
+ return ad3552r_update_reg_field(dac, addr_mask_map_ch[attr][0],
+ addr_mask_map_ch[attr][ch + 1], val);
+}
+
+#define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) { \
+ .type = IIO_VOLTAGE, \
+ .output = true, \
+ .indexed = true, \
+ .channel = _idx, \
+ .scan_index = _idx, \
+ .scan_type = { \
+ .sign = 'u', \
+ .realbits = 16, \
+ .storagebits = 16, \
+ .endianness = IIO_BE, \
+ }, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_ENABLE) | \
+ BIT(IIO_CHAN_INFO_OFFSET), \
+})
+
+static int ad3552r_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long mask)
+{
+ struct ad3552r_desc *dac = iio_priv(indio_dev);
+ u16 tmp_val;
+ int err;
+ u8 ch = chan->channel;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ mutex_lock(&dac->lock);
+ err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch),
+ &tmp_val);
+ if (err < 0) {
+ mutex_unlock(&dac->lock);
+ return err;
+ }
+ *val = tmp_val;
+ mutex_unlock(&dac->lock);
+ break;
+ case IIO_CHAN_INFO_ENABLE:
+ mutex_lock(&dac->lock);
+ err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,
+ &tmp_val);
+ if (err < 0) {
+ mutex_unlock(&dac->lock);
+ return err;
+ }
+ *val = !((tmp_val & AD3552R_MASK_CH_DAC_POWERDOWN(ch)) >>
+ __ffs(AD3552R_MASK_CH_DAC_POWERDOWN(ch)));
+ mutex_unlock(&dac->lock);
+ break;
+ case IIO_CHAN_INFO_SCALE:
+ *val = dac->ch_data[ch].scale_int;
+ *val2 = dac->ch_data[ch].scale_dec;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_CHAN_INFO_OFFSET:
+ *val = dac->ch_data[ch].offset_int;
+ *val2 = dac->ch_data[ch].offset_dec;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+
+ return IIO_VAL_INT;
+}
+
+static int ad3552r_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ struct ad3552r_desc *dac = iio_priv(indio_dev);
+ int err = 0;
+
+ mutex_lock(&dac->lock);
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ err = ad3552r_write_reg(dac,
+ AD3552R_REG_ADDR_CH_DAC_24B(chan->channel),
+ val);
+ break;
+ case IIO_CHAN_INFO_ENABLE:
+ err = ad3552r_set_ch_value(dac, AD3552R_CH_DAC_POWERDOWN,
+ chan->channel, !val);
+ break;
+ default:
+ err = -EINVAL;
+ break;
+ }
+ mutex_unlock(&dac->lock);
+
+ return err;
+}
+
+/*
+ * Device type specific information.
+ */
+static const struct iio_info ad3552r_iio_info = {
+ .read_raw = ad3552r_read_raw,
+ .write_raw = ad3552r_write_raw
+};
+
+static irqreturn_t ad3552r_trigger_handler(int irq, void *p)
+{
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->indio_dev;
+ struct iio_buffer *buf = indio_dev->buffer;
+ struct ad3552r_desc *dac = iio_priv(indio_dev);
+ char buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE];
+ int err;
+
+ memset(buff, 0, sizeof(buff));
+ err = iio_pop_from_buffer(buf, buff);
+ if (err)
+ goto end;
+
+ mutex_lock(&dac->lock);
+ ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff);
+ mutex_unlock(&dac->lock);
+end:
+ iio_trigger_notify_done(indio_dev->trig);
+
+ return IRQ_HANDLED;
+}
+
+static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac)
+{
+ const u16 val1 = AD3552R_SCRATCH_PAD_TEST_VAL1;
+ const u16 val2 = AD3552R_SCRATCH_PAD_TEST_VAL2;
+ u16 val;
+ int err;
+
+ err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val1);
+ if (err < 0)
+ return err;
+
+ err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
+ if (err < 0)
+ return err;
+
+ if (val1 != val)
+ return -ENODEV;
+
+ err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val2);
+ if (err < 0)
+ return err;
+
+ err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
+ if (err < 0)
+ return err;
+
+ if (val2 != val)
+ return -ENODEV;
+
+ return 0;
+}
+
+struct reg_addr_pool {
+ struct ad3552r_desc *dac;
+ u8 addr;
+};
+
+static u16 ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)
+{
+ int err;
+ u16 val = 0;
+
+ err = ad3552r_read_reg(addr->dac, addr->addr, &val);
+ if (err)
+ return err;
+
+ return val;
+}
+
+static int ad3552r_reset(struct ad3552r_desc *dac)
+{
+ struct reg_addr_pool addr;
+ int ret;
+ u16 val;
+
+ dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(dac->gpio_reset))
+ return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset),
+ "Error while getting gpio reset");
+
+ if (dac->gpio_reset) {
+ /* Perform hardware reset */
+ usleep_range(10, 20);
+ gpiod_set_value_cansleep(dac->gpio_reset, 1);
+ } else {
+ /* Perform software reset if no GPIO provided */
+ ret = ad3552r_update_reg_field(dac,
+ AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
+ AD3552R_MASK_SOFTWARE_RESET,
+ AD3552R_MASK_SOFTWARE_RESET);
+ if (ret < 0)
+ return ret;
+
+ }
+
+ addr.dac = dac;
+ addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B;
+ ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
+ val == AD3552R_DEFAULT_CONFIG_B_VALUE ||
+ val < 0,
+ 5000, 50000);
+ if (val < 0)
+ ret = val;
+ if (ret)
+ return dev_err_probe(&dac->spi->dev, ret,
+ "Error while resetting");
+
+ ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
+ !(val & AD3552R_MASK_INTERFACE_NOT_READY) ||
+ val < 0,
+ 5000, 50000);
+ if (val < 0)
+ ret = val;
+ if (ret)
+ return dev_err_probe(&dac->spi->dev, ret, "Error while reseting");
+
+ return ad3552r_update_reg_field(dac,
+ addr_mask_map[AD3552R_ADDR_ASCENSION][0],
+ addr_mask_map[AD3552R_ADDR_ASCENSION][1],
+ val);
+}
+
+static void ad3552r_get_custom_range(struct ad3552r_desc *dac, s32 i, s32 *v_min,
+ s32 *v_max)
+{
+ s64 vref, tmp, common, offset, gn, gp;
+ /*
+ * From datasheet formula (In Volts):
+ * Vmin = 2.5 + [(GainN + Offset / 1024) * 2.5 * Rfb * 1.03]
+ * Vmax = 2.5 - [(GainP + Offset / 1024) * 2.5 * Rfb * 1.03]
+ * Calculus are converted to milivolts
+ */
+ vref = 2500;
+ /* 2.5 * 1.03 * 1000 (To mV) */
+ common = 2575 * dac->ch_data[i].rfb;
+ offset = dac->ch_data[i].gain_offset;
+
+ gn = gains_scaling_table[dac->ch_data[i].n];
+ tmp = (1024 * gn + AD3552R_GAIN_SCALE * offset) * common;
+ tmp = div_s64(tmp, 1024 * AD3552R_GAIN_SCALE);
+ *v_max = vref + tmp;
+
+ gp = gains_scaling_table[dac->ch_data[i].p];
+ tmp = (1024 * gp - AD3552R_GAIN_SCALE * offset) * common;
+ tmp = div_s64(tmp, 1024 * AD3552R_GAIN_SCALE);
+ *v_min = vref - tmp;
+}
+
+static void ad3552r_calc_gain_and_offset(struct ad3552r_desc *dac, s32 ch)
+{
+ s32 idx, v_max, v_min, span, rem;
+ s64 tmp;
+
+ if (dac->ch_data[ch].range_override) {
+ ad3552r_get_custom_range(dac, ch, &v_min, &v_max);
+ } else {
+ /* Normal range */
+ idx = dac->ch_data[ch].range;
+ if (dac->chip_id == AD3542R_ID) {
+ v_min = ad3542r_ch_ranges[idx][0];
+ v_max = ad3542r_ch_ranges[idx][1];
+ } else {
+ v_min = ad3552r_ch_ranges[idx][0];
+ v_max = ad3552r_ch_ranges[idx][1];
+ }
+ }
+
+ /*
+ * From datasheet formula:
+ * Vout = Span * (D / 65536) + Vmin
+ * Converted to scale and offset:
+ * Scale = Span / 65536
+ * Offset = 65536 * Vmin / Span
+ *
+ * Reminders are in micros in order to be printed as
+ * IIO_VAL_INT_PLUS_MICRO
+ */
+ span = v_max - v_min;
+ dac->ch_data[ch].scale_int = div_s64_rem(span, 65536, &rem);
+ /* Do operations in microvolts */
+ dac->ch_data[ch].scale_dec = DIV_ROUND_CLOSEST((s64)rem * 1000000,
+ 65536);
+
+ dac->ch_data[ch].offset_int = div_s64_rem(v_min * 65536, span,
+ &rem);
+ tmp = (s64)rem * 1000000;
+ dac->ch_data[ch].offset_dec = div_s64(tmp, span);
+}
+
+static int ad3552r_find_range(u16 id, s32 *vals)
+{
+ int i, len;
+ const s32 (*ranges)[2];
+
+ if (id == AD3542R_ID) {
+ len = ARRAY_SIZE(ad3542r_ch_ranges);
+ ranges = ad3542r_ch_ranges;
+ } else {
+ len = ARRAY_SIZE(ad3552r_ch_ranges);
+ ranges = ad3552r_ch_ranges;
+ }
+
+ for (i = 0; i < len; i++)
+ if (vals[0] == ranges[i][0] * 1000 &&
+ vals[1] == ranges[i][1] * 1000)
+ return i;
+
+ return -EINVAL;
+}
+
+static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac,
+ struct fwnode_handle *child,
+ u32 ch)
+{
+ struct device *dev = &dac->spi->dev;
+ struct fwnode_handle *gain_child;
+ u32 val;
+ int err;
+ u8 addr;
+ u16 mask = 0, reg = 0, offset;
+
+ gain_child = fwnode_get_named_child_node(child,
+ "custom-output-range-config");
+ if (IS_ERR(gain_child))
+ return dev_err_probe(dev, PTR_ERR(gain_child),
+ "mandatory custom-output-range-config property missing\n");
+
+ dac->ch_data[ch].range_override = 1;
+ reg |= ad3552r_field_prep(1, AD3552R_MASK_CH_RANGE_OVERRIDE);
+ mask |= AD3552R_MASK_CH_RANGE_OVERRIDE;
+
+ err = fwnode_property_read_u32(gain_child, "adi,gain-scaling-p", &val);
+ if (err) {
+ dev_err_probe(dev, err,
+ "mandatory adi,gain-scaling-p property missing\n");
+ goto put_child;
+ }
+ reg |= ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_P);
+ mask |= AD3552R_MASK_CH_GAIN_SCALING_P;
+ dac->ch_data[ch].p = val;
+
+ err = fwnode_property_read_u32(gain_child, "adi,gain-scaling-n", &val);
+ if (err) {
+ dev_err_probe(dev, err,
+ "mandatory adi,gain-scaling-n property missing\n");
+ goto put_child;
+ }
+ reg |= ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_N);
+ mask |= AD3552R_MASK_CH_GAIN_SCALING_N;
+ dac->ch_data[ch].n = val;
+
+ err = fwnode_property_read_u32(gain_child, "adi,rfb-ohms", &val);
+ if (err) {
+ dev_err_probe(dev, err,
+ "mandatory adi,rfb-ohms property missing\n");
+ goto put_child;
+ }
+ dac->ch_data[ch].rfb = val;
+
+ err = fwnode_property_read_u32(gain_child, "adi,gain-offset", &val);
+ if (err) {
+ dev_err_probe(dev, err,
+ "mandatory adi,gain-offset property missing\n");
+ goto put_child;
+ }
+ dac->ch_data[ch].gain_offset = val;
+
+ offset = abs((s32)val);
+ reg |= ad3552r_field_prep((offset >> 8), AD3552R_MASK_CH_OFFSET_BIT_8);
+ mask |= AD3552R_MASK_CH_OFFSET_BIT_8;
+
+ reg |= ad3552r_field_prep((s32)val < 0, AD3552R_MASK_CH_OFFSET_POLARITY);
+ mask |= AD3552R_MASK_CH_OFFSET_POLARITY;
+ addr = AD3552R_REG_ADDR_CH_GAIN(ch);
+ err = ad3552r_write_reg(dac, addr,
+ offset & AD3552R_MASK_CH_OFFSET_BITS_0_7);
+ if (err) {
+ dev_err_probe(dev, err, "Error writing register\n");
+ goto put_child;
+ }
+
+ err = ad3552r_write_reg(dac, addr, reg);
+ if (err) {
+ dev_err_probe(dev, err, "Error writing register\n");
+ goto put_child;
+ }
+
+put_child:
+ fwnode_handle_put(gain_child);
+
+ return err;
+}
+
+static int ad3552r_configure_device(struct ad3552r_desc *dac)
+{
+ struct device *dev = &dac->spi->dev;
+ struct fwnode_handle *child;
+ struct regulator *vref;
+ int err, cnt = 0, voltage, delta = 100000;
+ u32 vals[2], val, ch;
+ bool is_custom;
+
+ dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH);
+ if (IS_ERR(dac->gpio_ldac))
+ return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac),
+ "Error getting gpio ldac");
+
+ vref = devm_regulator_get_optional(dev, "vref");
+ if (IS_ERR(vref)) {
+ if (PTR_ERR(vref) != -ENODEV)
+ return dev_err_probe(dev, PTR_ERR(vref),
+ "Error getting vref");
+ vref = NULL;
+ }
+ if (vref) {
+ voltage = regulator_get_voltage(vref);
+ if (voltage > 2500000 + delta || voltage < 2500000 - delta) {
+ dev_warn(dev, "vref-supply must be 2.5V");
+ return -EINVAL;
+ }
+ val = AD3552R_EXTERNAL_VREF_PIN_INPUT;
+ } else {
+ if (device_property_read_bool(dev, "adi,vref-out-en"))
+ val = AD3552R_INTERNAL_VREF_PIN_2P5V;
+ else
+ val = AD3552R_INTERNAL_VREF_PIN_FLOATING;
+ }
+ err = ad3552r_update_reg_field(dac,
+ addr_mask_map[AD3552R_VREF_SELECT][0],
+ addr_mask_map[AD3552R_VREF_SELECT][1],
+ val);
+ if (err)
+ return err;
+
+ err = device_property_read_u32(dev, "adi,sdo-drive-strength", &val);
+ if (!err) {
+ if (val > 3)
+ return dev_err_probe(dev, -EINVAL,
+ "adi,sdo-drive-strength must be less than 4\n");
+
+ err = ad3552r_update_reg_field(dac,
+ addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][0],
+ addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][1],
+ val);
+ if (err)
+ return err;
+ }
+
+ dac->num_ch = device_get_child_node_count(dev);
+ if (!dac->num_ch)
+ return dev_err_probe(dev, -ENODEV, "No channels defined\n");
+
+ device_for_each_child_node(dev, child) {
+ err = fwnode_property_read_u32(child, "reg", &ch);
+ if (err) {
+ dev_err_probe(dev, err,
+ "mandatory reg property missing\n");
+ goto put_child;
+ }
+ if (ch >= AD3552R_NUM_CH) {
+ dev_err_probe(dev, err, "reg must be less than %d\n",
+ AD3552R_NUM_CH);
+ err = -EINVAL;
+ goto put_child;
+ }
+
+ if (fwnode_property_present(child, "adi,output-range-microvolt")) {
+ is_custom = false;
+ err = fwnode_property_read_u32_array(child,
+ "adi,output-range-microvolt",
+ vals,
+ 2);
+ if (err) {
+ dev_err_probe(dev, err,
+ "mandatory adi,output-range-microvolt property missing\n");
+ goto put_child;
+ }
+
+ val = ad3552r_find_range(dac->chip_id, vals);
+ if ((s32)val < 0) {
+ err = -EINVAL;
+ dev_err_probe(dev, err,
+ "Invalid adi,output-range-microvolt value\n");
+ goto put_child;
+ }
+ err = ad3552r_set_ch_value(dac,
+ AD3552R_CH_OUTPUT_RANGE_SEL,
+ ch, val);
+ if (err)
+ goto put_child;
+
+ dac->ch_data[ch].range = val;
+ } else {
+ is_custom = true;
+ err = ad3552r_configure_custom_gain(dac, child, ch);
+ if (err)
+ goto put_child;
+ }
+
+ ad3552r_calc_gain_and_offset(dac, ch);
+ dac->enabled_ch |= BIT(ch);
+
+ err = ad3552r_set_ch_value(dac, AD3552R_CH_SELECT, ch, 1);
+ if (err < 0)
+ return err;
+
+ dac->channels[cnt] = AD3552R_CH_DAC(ch);
+ ++cnt;
+
+ }
+
+ /* Disable unused channels */
+ for_each_clear_bit(ch, &dac->enabled_ch, AD3552R_NUM_CH) {
+ err = ad3552r_set_ch_value(dac, AD3552R_CH_AMPLIFIER_POWERDOWN,
+ ch, 0);
+ if (err)
+ return err;
+ }
+
+ dac->num_ch = cnt;
+
+ return 0;
+put_child:
+ fwnode_handle_put(child);
+
+ return err;
+}
+
+static int ad3552r_init(struct ad3552r_desc *dac)
+{
+ int err;
+ u16 val, id;
+
+ err = ad3552r_reset(dac);
+ if (err)
+ return dev_err_probe(&dac->spi->dev, err, "Reset failed\n");
+
+ err = ad3552r_check_scratch_pad(dac);
+ if (err)
+ return dev_err_probe(&dac->spi->dev, err,
+ "Scratch pad test failed\n");
+
+ err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val);
+ if (err)
+ return dev_err_probe(&dac->spi->dev, err,
+ "Fail read PRODUCT_ID_L\n");
+
+ id = val;
+ err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val);
+ if (err)
+ return dev_err_probe(&dac->spi->dev, err,
+ "Fail read PRODUCT_ID_H\n");
+
+ id |= val << 8;
+ if (id != dac->chip_id)
+ return dev_err_probe(&dac->spi->dev, -ENODEV,
+ "Product id not matching\n");
+
+ return ad3552r_configure_device(dac);
+}
+
+static int ad3552r_probe(struct spi_device *spi)
+{
+ const struct spi_device_id *id = spi_get_device_id(spi);
+ struct ad3552r_desc *dac;
+ struct iio_dev *indio_dev;
+ int err;
+
+ indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dac));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ dac = iio_priv(indio_dev);
+ dac->spi = spi;
+ dac->chip_id = id->driver_data;
+
+ mutex_init(&dac->lock);
+
+ err = ad3552r_init(dac);
+ if (err)
+ return err;
+
+ /* Config triggered buffer device */
+ if (dac->chip_id == AD3552R_ID)
+ indio_dev->name = "ad3552r";
+ else
+ indio_dev->name = "ad3542r";
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->info = &ad3552r_iio_info;
+ indio_dev->num_channels = dac->num_ch;
+ indio_dev->channels = dac->channels;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+
+ err = devm_iio_triggered_buffer_setup_ext(&indio_dev->dev, indio_dev, NULL,
+ &ad3552r_trigger_handler,
+ IIO_BUFFER_DIRECTION_OUT,
+ NULL,
+ NULL);
+ if (err)
+ return err;
+
+ return devm_iio_device_register(&spi->dev, indio_dev);
+}
+
+static const struct spi_device_id ad3552r_id[] = {
+ { "ad3542r", AD3542R_ID },
+ { "ad3552r", AD3552R_ID },
+ { }
+};
+MODULE_DEVICE_TABLE(spi, ad3552r_id);
+
+static const struct of_device_id ad3552r_of_match[] = {
+ { .compatible = "adi,ad3542r"},
+ { .compatible = "adi,ad3552r"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, ad3552r_of_match);
+
+static struct spi_driver ad3552r_driver = {
+ .driver = {
+ .name = "ad3552r",
+ .of_match_table = ad3552r_of_match,
+ },
+ .probe = ad3552r_probe,
+ .id_table = ad3552r_id
+};
+module_spi_driver(ad3552r_driver);
+
+MODULE_AUTHOR("Mihail Chindris <[email protected]>");
+MODULE_DESCRIPTION("Analog Device AD3552R DAC");
+MODULE_LICENSE("GPL v2");
--
2.27.0
Copy unresolved comment from previous version
Mihail
> +patternProperties:
> + "^channel@([0-1])$":
> + type: object
> + description: Configurations of the DAC Channels
> + properties:
> + reg:
> + description: Channel number
> + enum: [0, 1]
> +
> + custom-output-range-config:
> > >
> > > Not a generic property so I think this needs an adi prefix.
> > > Jonathan
> >
> > I tried with adi prefix but I get weird errors while running dt_binding_check for properties with adi prefix and with type:object
> > Do you have any suggestion for this issues?
> >
> > Mihail
> >
@Rob
On Thu, 21 Oct 2021 07:09:26 +0000
Mihail Chindris <[email protected]> wrote:
> The AD3552R-16 is a low drift ultrafast, 16-bit accuracy,
> current output digital-to-analog converter (DAC) designed
> to generate multiple output voltage span ranges.
> The AD3552R-16 operates with a fixed 2.5V reference.
>
> Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ad3552r.pdf
>
> Signed-off-by: Mihail Chindris <[email protected]>
Hi Mihail,
I have a feeling you will end up revisiting the decision to use the
device IDs rather than an enum + lookup into a structure table to
handle the different chip variants. Current solution doesn't scale
well as we add more parts. However there is nothing wrong with how you
have it today so no need to change it yet!
You should also look at what dev_err_probe() is for. It's not for all
errors during probe, but rather just for those that might result in
a deferred probe. So stuff dependent on other drivers having loaded such
as regulators, gpios and clocks.
As normal (unfortunately) I missed some stuff in previous reviews.
In particular I'm unconvinced that it makes sense to present the channels
in the kfifo to userspace as be16. We do that to minimise conversions, but
in this case we end up always converting it at least once anyway so might
as well make the u16 and the code simpler.
> ---
> drivers/iio/dac/Kconfig | 10 +
> drivers/iio/dac/Makefile | 1 +
> drivers/iio/dac/ad3552r.c | 1208 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 1219 insertions(+)
> create mode 100644 drivers/iio/dac/ad3552r.c
>
> diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig
> index 75e1f2b48638..ced6428f2c92 100644
> --- a/drivers/iio/dac/Kconfig
> +++ b/drivers/iio/dac/Kconfig
> @@ -6,6 +6,16 @@
>
> menu "Digital to analog converters"
>
> +config AD3552R
> + tristate "Analog Devices AD3552R DAC driver"
> + depends on SPI_MASTER
> + help
> + Say yes here to build support for Analog Devices AD3552R
> + Digital to Analog Converter.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called ad3552r.
> +
> config AD5064
> tristate "Analog Devices AD5064 and similar multi-channel DAC driver"
> depends on (SPI_MASTER && I2C!=m) || I2C
> diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile
> index 33e16f14902a..dffe36efd8ff 100644
> --- a/drivers/iio/dac/Makefile
> +++ b/drivers/iio/dac/Makefile
> @@ -4,6 +4,7 @@
> #
>
> # When adding new entries keep the list in alphabetical order
> +obj-$(CONFIG_AD3552R) += ad3552r.o
> obj-$(CONFIG_AD5360) += ad5360.o
> obj-$(CONFIG_AD5380) += ad5380.o
> obj-$(CONFIG_AD5421) += ad5421.o
> diff --git a/drivers/iio/dac/ad3552r.c b/drivers/iio/dac/ad3552r.c
> new file mode 100644
> index 000000000000..fd70883c692e
> --- /dev/null
> +++ b/drivers/iio/dac/ad3552r.c
> @@ -0,0 +1,1208 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Analog Devices AD3552R
> + * Digital to Analog converter driver
> + *
> + * Copyright 2021 Analog Devices Inc.
> + */
> +#include <asm/unaligned.h>
> +#include <linux/device.h>
> +#include <linux/iio/trigger.h>
I doubt you need trigger.h as that is normally only needed for drivers implementing
their own trigger.
> +#include <linux/iio/triggered_buffer.h>
> +#include <linux/iio/trigger_consumer.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/spi/spi.h>
...
> +
> +static int ad3552r_write_and_trigger(struct ad3552r_desc *dac, u8 addr, u16 val,
> + u32 mask)
Hmm. Whilst it would be a little more code, I'd pull the gpio write in here as well
+ duplicate it for the one path that doesn't use this function. Otherwise we have
a function that 'might trigger' which is a little confusing.
> +{
> + int err;
> +
> + err = ad3552r_write_reg(dac, addr, val);
> + if (err)
> + return err;
> +
> + if (!dac->gpio_ldac) {
> + err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B,
> + mask);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data)
> +{
> + int err, ch, len;
> + u8 addr, buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE + 1];
> + u16 val1, val2;
> +
> + val1 = be16_to_cpu(*((u16 *)data));
> + if (mask == AD3552R_MASK_ALL_CH) {
> + val2 = be16_to_cpu(*((u16 *)(data + 2)));
At least locally it's not obvious that this is aligned. So you should
use get_unaligned_be16()
Bounce backwards and forwards from big endian to cpu endian is a bit
messy and rather defeats the point of having it big endian in the kfifo.
If you can keep it in big endian all the way through that would be better
if that doesn't make sense, then make the buffer cpu endian and do the
put_unaligned_be16 in the few places it will be needed.
> + if (val1 == val2) {
Should work fine for __be16 as well..
> + err = ad3552r_write_and_trigger(dac,
> + AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B,
> + val1,
This would need to take a __be16.
> + AD3552R_MASK_ALL_CH);
> + if (err)
> + return err;
> + } else {
> + addr = AD3552R_REG_ADDR_CH_INPUT_24B(1);
> + /* CH1 */
> + buff[0] = data[2];
> + buff[1] = data[3];
These should be probably be memcpy, or potentially use a packed struct to allow you to just
do assignment. Given I'm suggesting above that you should use cpu endian for the channel
type anyway, you will just end with these being put_unaligned_be16()
> + buff[2] = 0;
> + /* CH0 */
> + buff[3] = data[0];
> + buff[4] = data[1];
> + buff[5] = 0;
> + len = 6;
> + if (!dac->gpio_ldac) {
> + /* Software LDAC */
> + buff[6] = AD3552R_MASK_ALL_CH;
> + ++len;
> + }
> + err = ad3552r_transfer(dac, addr, len, buff, false);
> + if (err)
> + return err;
> + }
> + } else {
> + ch = __ffs(mask);
> + err = ad3552r_write_and_trigger(dac,
> + AD3552R_REG_ADDR_CH_INPUT_24B(ch),
> + val1,
> + mask);
> + if (err)
> + return err;
> + }
> +
> + if (dac->gpio_ldac) {
> + gpiod_set_value_cansleep(dac->gpio_ldac, 0);
> + usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10);
> + gpiod_set_value_cansleep(dac->gpio_ldac, 1);
> + }
> +
> + return 0;
> +}
> +
> +> +static irqreturn_t ad3552r_trigger_handler(int irq, void *p)
> +{
> + struct iio_poll_func *pf = p;
> + struct iio_dev *indio_dev = pf->indio_dev;
> + struct iio_buffer *buf = indio_dev->buffer;
> + struct ad3552r_desc *dac = iio_priv(indio_dev);
> + char buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE];
Why this size? Also u8 for consistency.
> + int err;
> +
> + memset(buff, 0, sizeof(buff));
> + err = iio_pop_from_buffer(buf, buff);
> + if (err)
> + goto end;
> +
> + mutex_lock(&dac->lock);
> + ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff);
> + mutex_unlock(&dac->lock);
> +end:
> + iio_trigger_notify_done(indio_dev->trig);
> +
> + return IRQ_HANDLED;
> +}
> +static int ad3552r_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val,
> + int *val2,
> + long mask)
> +{
> + struct ad3552r_desc *dac = iio_priv(indio_dev);
> + u16 tmp_val;
> + int err;
> + u8 ch = chan->channel;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + mutex_lock(&dac->lock);
> + err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch),
> + &tmp_val);
> + if (err < 0) {
> + mutex_unlock(&dac->lock);
> + return err;
> + }
> + *val = tmp_val;
I don't thing this assignment needs to be under the lock. Moving it out allows for
this common pattern used when we need to release a lock whether or not there was an error.
Same applies to similar cases elsewhere.
mutex_lock(&dac->lock);
err = ad3552r_read_reg();
muteX_unlock(&dac->lock)
if (err < 0)
return err;
*val = tmp_val;
return IIO_VAL_INT;
> + mutex_unlock(&dac->lock);
> + break;
> + case IIO_CHAN_INFO_ENABLE:
> + mutex_lock(&dac->lock);
> + err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,
> + &tmp_val);
> + if (err < 0) {
> + mutex_unlock(&dac->lock);
> + return err;
> + }
> + *val = !((tmp_val & AD3552R_MASK_CH_DAC_POWERDOWN(ch)) >>
> + __ffs(AD3552R_MASK_CH_DAC_POWERDOWN(ch)));
> + mutex_unlock(&dac->lock);
> + break;
> + case IIO_CHAN_INFO_SCALE:
> + *val = dac->ch_data[ch].scale_int;
> + *val2 = dac->ch_data[ch].scale_dec;
> + return IIO_VAL_INT_PLUS_MICRO;
> + case IIO_CHAN_INFO_OFFSET:
> + *val = dac->ch_data[ch].offset_int;
> + *val2 = dac->ch_data[ch].offset_dec;
> + return IIO_VAL_INT_PLUS_MICRO;
> + default:
> + return -EINVAL;
> + }
> +
> + return IIO_VAL_INT;
Better to return from all switch cases as that puts the type near where the
data is set.
> +}
> +
> +static u16 ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)
> +{
> + int err;
> + u16 val = 0;
The compiler should have visibility enough to tell that there is
not path in which we use an unassigned val. Unless you are getting warnings
I would prefer you remove that assignment to make it clear we never actually
use it. If the compiler is being fussy - add a comment that this is warning
suppression.
> +
> + err = ad3552r_read_reg(addr->dac, addr->addr, &val);
> + if (err)
> + return err;
> +
> + return val;
I think this function needs to return an integer (See below)
> +}
> +
> +static int ad3552r_reset(struct ad3552r_desc *dac)
> +{
> + struct reg_addr_pool addr;
> + int ret;
> + u16 val;
> +
> + dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",
> + GPIOD_OUT_LOW);
> + if (IS_ERR(dac->gpio_reset))
> + return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset),
> + "Error while getting gpio reset");
> +
> + if (dac->gpio_reset) {
> + /* Perform hardware reset */
> + usleep_range(10, 20);
> + gpiod_set_value_cansleep(dac->gpio_reset, 1);
> + } else {
> + /* Perform software reset if no GPIO provided */
> + ret = ad3552r_update_reg_field(dac,
> + AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
> + AD3552R_MASK_SOFTWARE_RESET,
> + AD3552R_MASK_SOFTWARE_RESET);
> + if (ret < 0)
> + return ret;
> +
> + }
> +
> + addr.dac = dac;
> + addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B;
> + ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
> + val == AD3552R_DEFAULT_CONFIG_B_VALUE ||
> + val < 0,
> + 5000, 50000);
> + if (val < 0)
> + ret = val;
> + if (ret)
> + return dev_err_probe(&dac->spi->dev, ret,
> + "Error while resetting");
> +
> + ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
> + !(val & AD3552R_MASK_INTERFACE_NOT_READY) ||
> + val < 0,
Won't happen as val is u16.
> + 5000, 50000);
> + if (val < 0)
> + ret = val;
> + if (ret)
> + return dev_err_probe(&dac->spi->dev, ret, "Error while reseting");
> +
> + return ad3552r_update_reg_field(dac,
> + addr_mask_map[AD3552R_ADDR_ASCENSION][0],
> + addr_mask_map[AD3552R_ADDR_ASCENSION][1],
> + val);
> +}
> +static int ad3552r_configure_device(struct ad3552r_desc *dac)
> +{
> + struct device *dev = &dac->spi->dev;
> + struct fwnode_handle *child;
> + struct regulator *vref;
> + int err, cnt = 0, voltage, delta = 100000;
> + u32 vals[2], val, ch;
> + bool is_custom;
> +
> + dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH);
> + if (IS_ERR(dac->gpio_ldac))
> + return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac),
> + "Error getting gpio ldac");
> +
> + vref = devm_regulator_get_optional(dev, "vref");
> + if (IS_ERR(vref)) {
> + if (PTR_ERR(vref) != -ENODEV)
> + return dev_err_probe(dev, PTR_ERR(vref),
> + "Error getting vref");
> + vref = NULL;
> + }
> + if (vref) {
> + voltage = regulator_get_voltage(vref);
> + if (voltage > 2500000 + delta || voltage < 2500000 - delta) {
> + dev_warn(dev, "vref-supply must be 2.5V");
> + return -EINVAL;
> + }
> + val = AD3552R_EXTERNAL_VREF_PIN_INPUT;
> + } else {
> + if (device_property_read_bool(dev, "adi,vref-out-en"))
> + val = AD3552R_INTERNAL_VREF_PIN_2P5V;
> + else
> + val = AD3552R_INTERNAL_VREF_PIN_FLOATING;
> + }
> + err = ad3552r_update_reg_field(dac,
> + addr_mask_map[AD3552R_VREF_SELECT][0],
> + addr_mask_map[AD3552R_VREF_SELECT][1],
> + val);
> + if (err)
> + return err;
> +
> + err = device_property_read_u32(dev, "adi,sdo-drive-strength", &val);
> + if (!err) {
> + if (val > 3)
> + return dev_err_probe(dev, -EINVAL,
> + "adi,sdo-drive-strength must be less than 4\n");
> +
> + err = ad3552r_update_reg_field(dac,
> + addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][0],
> + addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][1],
> + val);
> + if (err)
> + return err;
> + }
> +
> + dac->num_ch = device_get_child_node_count(dev);
> + if (!dac->num_ch)
> + return dev_err_probe(dev, -ENODEV, "No channels defined\n");
> +
> + device_for_each_child_node(dev, child) {
> + err = fwnode_property_read_u32(child, "reg", &ch);
> + if (err) {
> + dev_err_probe(dev, err,
> + "mandatory reg property missing\n");
> + goto put_child;
> + }
> + if (ch >= AD3552R_NUM_CH) {
> + dev_err_probe(dev, err, "reg must be less than %d\n",
> + AD3552R_NUM_CH);
> + err = -EINVAL;
> + goto put_child;
> + }
> +
> + if (fwnode_property_present(child, "adi,output-range-microvolt")) {
> + is_custom = false;
> + err = fwnode_property_read_u32_array(child,
> + "adi,output-range-microvolt",
> + vals,
> + 2);
> + if (err) {
> + dev_err_probe(dev, err,
> + "mandatory adi,output-range-microvolt property missing\n");
> + goto put_child;
> + }
> +
> + val = ad3552r_find_range(dac->chip_id, vals);
> + if ((s32)val < 0) {
return value is an int, so use something like
err = ad3552r_...
if (err < 0) {
...
}
val = err;
> + err = -EINVAL;
> + dev_err_probe(dev, err,
> + "Invalid adi,output-range-microvolt value\n");
> + goto put_child;
> + }
> + err = ad3552r_set_ch_value(dac,
> + AD3552R_CH_OUTPUT_RANGE_SEL,
> + ch, val);
> + if (err)
> + goto put_child;
> +
> + dac->ch_data[ch].range = val;
> + } else {
> + is_custom = true;
> + err = ad3552r_configure_custom_gain(dac, child, ch);
> + if (err)
> + goto put_child;
> + }
> +
> + ad3552r_calc_gain_and_offset(dac, ch);
> + dac->enabled_ch |= BIT(ch);
> +
> + err = ad3552r_set_ch_value(dac, AD3552R_CH_SELECT, ch, 1);
> + if (err < 0)
goto put_child?
> + return err;
> +
> + dac->channels[cnt] = AD3552R_CH_DAC(ch);
> + ++cnt;
> +
> + }
> +
> + /* Disable unused channels */
> + for_each_clear_bit(ch, &dac->enabled_ch, AD3552R_NUM_CH) {
> + err = ad3552r_set_ch_value(dac, AD3552R_CH_AMPLIFIER_POWERDOWN,
> + ch, 0);
> + if (err)
> + return err;
> + }
> +
> + dac->num_ch = cnt;
> +
> + return 0;
> +put_child:
> + fwnode_handle_put(child);
> +
> + return err;
> +}
> +
> +static int ad3552r_init(struct ad3552r_desc *dac)
> +{
> + int err;
> + u16 val, id;
> +
> + err = ad3552r_reset(dac);
> + if (err)
> + return dev_err_probe(&dac->spi->dev, err, "Reset failed\n");
> +
> + err = ad3552r_check_scratch_pad(dac);
> + if (err)
> + return dev_err_probe(&dac->spi->dev, err,
These should not be dev_err_probe as they can't (I think) ever return
that the probe is deferred.
> + "Scratch pad test failed\n");
> +
> + err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val);
> + if (err)
> + return dev_err_probe(&dac->spi->dev, err,
> + "Fail read PRODUCT_ID_L\n");
> +
> + id = val;
> + err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val);
> + if (err)
> + return dev_err_probe(&dac->spi->dev, err,
> + "Fail read PRODUCT_ID_H\n");
> +
> + id |= val << 8;
> + if (id != dac->chip_id)
> + return dev_err_probe(&dac->spi->dev, -ENODEV,
> + "Product id not matching\n");
> +
> + return ad3552r_configure_device(dac);
> +}
> +
...
Hi Mihail,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on ef226dcf3d88697a06335fbc55c4263ab164b135]
url: https://github.com/0day-ci/linux/commits/Mihail-Chindris/drivers-iio-dac-Add-AD3552R-driver-support/20211021-151417
base: ef226dcf3d88697a06335fbc55c4263ab164b135
config: nios2-allyesconfig (attached as .config)
compiler: nios2-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/6c22b3c7b44166beec8e31f25025042cc0da1ba7
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Mihail-Chindris/drivers-iio-dac-Add-AD3552R-driver-support/20211021-151417
git checkout 6c22b3c7b44166beec8e31f25025042cc0da1ba7
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=nios2
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
drivers/iio/dac/ad3552r.c: In function 'ad3552r_configure_device':
>> drivers/iio/dac/ad3552r.c:978:14: error: variable 'is_custom' set but not used [-Werror=unused-but-set-variable]
978 | bool is_custom;
| ^~~~~~~~~
cc1: all warnings being treated as errors
vim +/is_custom +978 drivers/iio/dac/ad3552r.c
970
971 static int ad3552r_configure_device(struct ad3552r_desc *dac)
972 {
973 struct device *dev = &dac->spi->dev;
974 struct fwnode_handle *child;
975 struct regulator *vref;
976 int err, cnt = 0, voltage, delta = 100000;
977 u32 vals[2], val, ch;
> 978 bool is_custom;
979
980 dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH);
981 if (IS_ERR(dac->gpio_ldac))
982 return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac),
983 "Error getting gpio ldac");
984
985 vref = devm_regulator_get_optional(dev, "vref");
986 if (IS_ERR(vref)) {
987 if (PTR_ERR(vref) != -ENODEV)
988 return dev_err_probe(dev, PTR_ERR(vref),
989 "Error getting vref");
990 vref = NULL;
991 }
992 if (vref) {
993 voltage = regulator_get_voltage(vref);
994 if (voltage > 2500000 + delta || voltage < 2500000 - delta) {
995 dev_warn(dev, "vref-supply must be 2.5V");
996 return -EINVAL;
997 }
998 val = AD3552R_EXTERNAL_VREF_PIN_INPUT;
999 } else {
1000 if (device_property_read_bool(dev, "adi,vref-out-en"))
1001 val = AD3552R_INTERNAL_VREF_PIN_2P5V;
1002 else
1003 val = AD3552R_INTERNAL_VREF_PIN_FLOATING;
1004 }
1005 err = ad3552r_update_reg_field(dac,
1006 addr_mask_map[AD3552R_VREF_SELECT][0],
1007 addr_mask_map[AD3552R_VREF_SELECT][1],
1008 val);
1009 if (err)
1010 return err;
1011
1012 err = device_property_read_u32(dev, "adi,sdo-drive-strength", &val);
1013 if (!err) {
1014 if (val > 3)
1015 return dev_err_probe(dev, -EINVAL,
1016 "adi,sdo-drive-strength must be less than 4\n");
1017
1018 err = ad3552r_update_reg_field(dac,
1019 addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][0],
1020 addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][1],
1021 val);
1022 if (err)
1023 return err;
1024 }
1025
1026 dac->num_ch = device_get_child_node_count(dev);
1027 if (!dac->num_ch)
1028 return dev_err_probe(dev, -ENODEV, "No channels defined\n");
1029
1030 device_for_each_child_node(dev, child) {
1031 err = fwnode_property_read_u32(child, "reg", &ch);
1032 if (err) {
1033 dev_err_probe(dev, err,
1034 "mandatory reg property missing\n");
1035 goto put_child;
1036 }
1037 if (ch >= AD3552R_NUM_CH) {
1038 dev_err_probe(dev, err, "reg must be less than %d\n",
1039 AD3552R_NUM_CH);
1040 err = -EINVAL;
1041 goto put_child;
1042 }
1043
1044 if (fwnode_property_present(child, "adi,output-range-microvolt")) {
1045 is_custom = false;
1046 err = fwnode_property_read_u32_array(child,
1047 "adi,output-range-microvolt",
1048 vals,
1049 2);
1050 if (err) {
1051 dev_err_probe(dev, err,
1052 "mandatory adi,output-range-microvolt property missing\n");
1053 goto put_child;
1054 }
1055
1056 val = ad3552r_find_range(dac->chip_id, vals);
1057 if ((s32)val < 0) {
1058 err = -EINVAL;
1059 dev_err_probe(dev, err,
1060 "Invalid adi,output-range-microvolt value\n");
1061 goto put_child;
1062 }
1063 err = ad3552r_set_ch_value(dac,
1064 AD3552R_CH_OUTPUT_RANGE_SEL,
1065 ch, val);
1066 if (err)
1067 goto put_child;
1068
1069 dac->ch_data[ch].range = val;
1070 } else {
1071 is_custom = true;
1072 err = ad3552r_configure_custom_gain(dac, child, ch);
1073 if (err)
1074 goto put_child;
1075 }
1076
1077 ad3552r_calc_gain_and_offset(dac, ch);
1078 dac->enabled_ch |= BIT(ch);
1079
1080 err = ad3552r_set_ch_value(dac, AD3552R_CH_SELECT, ch, 1);
1081 if (err < 0)
1082 return err;
1083
1084 dac->channels[cnt] = AD3552R_CH_DAC(ch);
1085 ++cnt;
1086
1087 }
1088
1089 /* Disable unused channels */
1090 for_each_clear_bit(ch, &dac->enabled_ch, AD3552R_NUM_CH) {
1091 err = ad3552r_set_ch_value(dac, AD3552R_CH_AMPLIFIER_POWERDOWN,
1092 ch, 0);
1093 if (err)
1094 return err;
1095 }
1096
1097 dac->num_ch = cnt;
1098
1099 return 0;
1100 put_child:
1101 fwnode_handle_put(child);
1102
1103 return err;
1104 }
1105
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]