The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29:
Linux 5.15-rc3 (2021-09-26 14:08:19 -0700)
are available in the Git repository at:
[email protected]:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16.v3
for you to fetch changes up to 561ced0bb90a4be298b7db5fb54f29731d74a3f6:
arm64: errata: Enable TRBE workaround for write to out-of-range address (2021-10-27 11:46:06 -0600)
----------------------------------------------------------------
Coresight changes for v5.16
- A new option to make coresight cpu-debug capabilities available as early
as possible in the kernel boot process.
- Make trace sessions more enduring by coping with scenarios where events
are scheduled on CPUs that can't reach the selected sink.
- A set of improvement to make the TMC-ETR driver more efficient.
- Enhancements to the TRBE driver to correct several errata.
- An enhancement to make the AXI burts size configurable for TMC devices
that can't work with the default value.
- A fix in the CTI module to use the correct device when calling
pm_runtime_put()
- The addition of the Kryo-5xx device to the list of support ETMs.
Signed-off-by: Mathieu Poirier <[email protected]>
----------------------------------------------------------------
Brian Norris (1):
coresight: cpu-debug: Control default behavior via Kconfig
James Clark (1):
coresight: Don't immediately close events that are run on invalid CPU/sink combos
Leo Yan (5):
coresight: tmc-etr: Add barrier after updating AUX ring buffer
coresight: tmc-etf: Add comment for store ordering
coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer
coresight: Update comments for removing cs_etm_find_snapshot()
coresight: tmc-etr: Speed up for bounce buffer in flat mode
Suzuki K Poulose (28):
arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
arm64: errata: Add detection for TRBE overwrite in FILL mode
arm64: errata: Add workaround for TSB flush failures
arm64: errata: Add detection for TRBE write to out-of-range
coresight: etm4x: Save restore TRFCR_EL1
coresight: etm4x: Use Trace Filtering controls dynamically
coresight: etm-pmu: Ensure the AUX handle is valid
coresight: trbe: Ensure the format flag is always set
coresight: trbe: Drop duplicate TRUNCATE flags
coresight: trbe: Unify the enabling sequence
coresight: trbe: irq handler: Do not disable TRBE if no action is needed
coresight: trbe: Fix handling of spurious interrupts
coresight: trbe: Do not truncate buffer on IRQ
coresight: trbe: End the AUX handle on truncation
coresight: trbe: Prohibit trace before disabling TRBE
coresight: trbe: Fix incorrect access of the sink specific data
coresight: trbe: Defer the probe on offline CPUs
coresight: trbe: Add a helper to calculate the trace generated
coresight: trbe: Add a helper to pad a given buffer area
coresight: trbe: Decouple buffer base from the hardware base
coresight: trbe: Allow driver to choose a different alignment
coresight: trbe: Add infrastructure for Errata handling
coresight: trbe: Workaround TRBE errata overwrite in FILL mode
coresight: trbe: Add a helper to determine the minimum buffer size
coresight: trbe: Make sure we have enough space
coresight: trbe: Work around write to out of range
arm64: errata: Enable workaround for TRBE overwrite in FILL mode
arm64: errata: Enable TRBE workaround for write to out-of-range address
Tanmay Jagdale (2):
dt-bindings: coresight: Add burst size for TMC
coresight: tmc: Configure AXI write burst size
Tao Zhang (2):
coresight: cti: Correct the parameter for pm_runtime_put
coresight: etm4x: Add ETM PID for Kryo-5XX
Documentation/arm64/silicon-errata.rst | 12 +
.../devicetree/bindings/arm/coresight.txt | 5 +
arch/arm64/Kconfig | 111 +++++
arch/arm64/include/asm/barrier.h | 16 +-
arch/arm64/include/asm/cputype.h | 4 +
arch/arm64/kernel/cpu_errata.c | 64 +++
arch/arm64/tools/cpucaps | 3 +
drivers/hwtracing/coresight/Kconfig | 13 +
drivers/hwtracing/coresight/coresight-cpu-debug.c | 2 +-
drivers/hwtracing/coresight/coresight-cti-core.c | 2 +-
drivers/hwtracing/coresight/coresight-etb10.c | 5 +-
drivers/hwtracing/coresight/coresight-etm-perf.c | 56 ++-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 101 +++-
drivers/hwtracing/coresight/coresight-etm4x.h | 9 +-
.../coresight/coresight-self-hosted-trace.h | 33 ++
drivers/hwtracing/coresight/coresight-tmc-core.c | 21 +-
drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 +-
drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 +-
drivers/hwtracing/coresight/coresight-tmc.h | 6 +-
drivers/hwtracing/coresight/coresight-trbe.c | 534 +++++++++++++++++----
20 files changed, 905 insertions(+), 154 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h
On Wed, Oct 27, 2021 at 01:52:24PM -0600, Mathieu Poirier wrote:
> The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29:
>
> Linux 5.15-rc3 (2021-09-26 14:08:19 -0700)
>
> are available in the Git repository at:
>
> [email protected]:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16.v3
Much better, thanks!
Now pulled and pushed out.
greg k-h