This series of patches handles the scenarios where error injection
fails silently on mce-inject module. It also sets the valid bit in
MCA_STATUS register unconditionally to correct Val=0 injection made by the
user and finally returns error code to userspace on failures injecting the
module.
Error injection fails if the bank is unpopulated (MCA_IPID register reads
zero) or if the platform enforces write ignored behavior on status
registers.
The first patch checks for an unpopulated bank by reading the value out
from MCA_IPID register and the third patch checks for writes ignored from
MCA_STATUS and MCA_DESTAT.
The second patch sets valid bit before doing error injection.
The fourth and fifth patch does some cleanup in prepare_msrs(). No
functional changes in these two patches.
The final patch returns error code to userspace from mce-inject module.
Smita Koralahalli (6):
x86/mce/inject: Check if a bank is unpopulated before error injection
x86/mce/inject: Set the valid bit in MCA_STATUS before error injection
x86/mce/inject: Check for writes ignored in status registers
x86/mce/inject: Simplify evaluation of writes ignored in status
registers
x86/mce/inject: Restructure prepare_msrs()
x86/mce/mce-inject: Return error code to userspace from mce-inject
module
arch/x86/kernel/cpu/mce/inject.c | 106 ++++++++++++++++++++++++++-----
1 file changed, 90 insertions(+), 16 deletions(-)
--
2.17.1
Rearrange the calls and write to registers MCx_{ADDR, MISC, SYND} and
MCG_STATUS so that they are only done if error injection is available.
Signed-off-by: Smita Koralahalli <[email protected]>
---
arch/x86/kernel/cpu/mce/inject.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 8772d8820994..d4e6d753018f 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -484,23 +484,19 @@ static void prepare_msrs(void *info)
u8 b = m.bank;
u32 status_reg = MSR_IA32_MCx_STATUS(b);
-
- wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
+ u32 addr_reg = MSR_IA32_MCx_ADDR(b);
+ u32 misc_reg = MSR_IA32_MCx_MISC(b);
if (boot_cpu_has(X86_FEATURE_SMCA)) {
if (m.inject_flags == DFR_INT_INJ) {
status_reg = MSR_AMD64_SMCA_MCx_DESTAT(b);
- wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr);
+ addr_reg = MSR_AMD64_SMCA_MCx_DEADDR(b);
} else {
status_reg = MSR_AMD64_SMCA_MCx_STATUS(b);
- wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr);
+ addr_reg = MSR_AMD64_SMCA_MCx_ADDR(b);
}
- wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc);
- wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd);
- } else {
- wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr);
- wrmsrl(MSR_IA32_MCx_MISC(b), m.misc);
+ misc_reg = MSR_AMD64_SMCA_MCx_MISC(b);
}
wrmsrl(status_reg, m.status);
@@ -511,6 +507,13 @@ static void prepare_msrs(void *info)
i_mce_err->err = -EINVAL;
return;
}
+
+ wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
+ wrmsrl(addr_reg, m.addr);
+ wrmsrl(misc_reg, m.misc);
+
+ if (boot_cpu_has(X86_FEATURE_SMCA))
+ wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd);
}
static void do_inject(void)
--
2.17.1