Hi Bjorn and Vinod,
I'm trying to enable the display subsystem on SM8150 but am having
trouble enabling the DISP_CC_MDSS_AHB_CLK. Trace shows "disp_cc_mdss_ahb_clk
status stuck at off". Do you have any pointers on enabling this clock?
msm_dsi_phy ae94400.dsi-phy: [drm:dsi_phy_driver_probe [msm]] *ERROR* dsi_phy_driver_probe: Unable to get ahb clk
disp_cc-sm8250 af00000.clock-controller: supply mmcx not found, using dummy regulator
platform ae96000.dsi: Fixing up cyclic dependency with ae00000.mdss:mdp@ae010000
------------[ cut here ]------------
disp_cc_mdss_ahb_clk status stuck at 'off'
WARNING: CPU: 6 PID: 76 at drivers/clk/qcom/clk-branch.c:91 clk_branch_wait+0x14c/0x164
CPU: 6 PID: 76 Comm: kworker/u16:2 Not tainted 5.15.0 #17
Hardware name: Microsoft Surface Duo (DT)
Workqueue: events_unbound deferred_probe_work_func
pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : clk_branch_wait+0x14c/0x164
lr : clk_branch_wait+0x14c/0x164
sp : ffff80001078ba40
x29: ffff80001078ba40 x28: 0000000000000000 x27: ffff65e6008e2100
x26: ffffb8630ec8e278 x25: ffff65e60005e005 x24: ffffb8630ebc0f98
x23: ffffb8630e234dd8 x22: 0000000000000001 x21: ffffb8630d5b8b60
x20: 0000000000000000 x19: ffffb8630eb5e7b8 x18: 0000000000000030
x17: 2e726f74616c7567 x16: ffffb8630d5a3800 x15: ffffffffffffffff
x14: 0000000000000000 x13: 6f27207461206b63 x12: 7574732073757461
x11: 77705f313439386d x10: 0000000000000027 x9 : ffffb8630cf974bc
x8 : 0000000000000027 x7 : 0000000000000002 x6 : 0000000000000027
x5 : ffff65e6f93cc9a8 x4 : ffff80001078b890 x3 : 0000000000000001
x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff65e600851d80
Call trace:
clk_branch_wait+0x14c/0x164
clk_branch2_enable+0x3c/0x60
clk_core_enable+0x78/0x220
clk_enable+0x38/0x60
dsi_phy_enable_resource+0x98/0xac [msm]
dsi_phy_driver_probe+0x29c/0x4f8 [msm]
platform_probe+0x74/0xe4
really_probe.part.0+0xa4/0x328
__driver_probe_device+0xa0/0x150
driver_probe_device+0x4c/0x164
__device_attach_driver+0xc0/0x128
bus_for_each_drv+0x84/0xe0
__device_attach+0xe0/0x188
device_initial_probe+0x20/0x2c
bus_probe_device+0xa8/0xbc
deferred_probe_work_func+0x90/0xc8
process_one_work+0x1f4/0x43c
worker_thread+0x78/0x4f0
kthread+0x154/0x160
ret_from_fork+0x10/0x20
---[ end trace 734ed75908fc6b0e ]---
Katherine Perez (4):
arm64: dts: qcom: sm8150: add dispcc node
arm64: dts: qcom: sm8150: add display nodes
arm64: dts: qcom: sm8150: add DSI display nodes
arm64: dts: qcom: sm8150: display support for Microsoft Surface Duo
.../dts/qcom/sm8150-microsoft-surface-duo.dts | 26 ++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 292 ++++++++++++++++++
2 files changed, 318 insertions(+)
--
2.31.1
Add the display clock controller node to sm8150.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Katherine Perez <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 81b4ff2cc4cd..ee40af469fab 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
@@ -3260,6 +3261,30 @@ camnoc_virt: interconnect@ac00000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8150-dispcc";
+ reg = <0 0x0af00000 0 0x10000>;
+ power-domains = <&rpmhpd SM8150_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
--
2.31.1
Add DSI controller and PHY nodes to sm8150.
Signed-off-by: Katherine Perez <[email protected]>
---
Changes in v3:
- Move dsi-opp-table out of /soc (Bjorn Andresson)
- Rename DSI nodes (Bjorn Andersson)
arch/arm64/boot/dts/qcom/sm8150.dtsi | 185 ++++++++++++++++++++++++++-
1 file changed, 181 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 38dbc39103ba..8a80f7910e07 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3351,6 +3351,183 @@ opp-460000000 {
};
};
};
+
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8150_MMCX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-7nm-8150";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss_dsi1: dsi@ae96000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8150_CX>;
+
+ phys = <&mdss_dsi1_phy>;
+ phy-names = "dsi";
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: dsi-phy@ae96400 {
+ compatible = "qcom,dsi-phy-7nm-8150";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+
+ dsi_opp_table: dsi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-180000000 {
+ opp-hz = /bits/ 64 <180000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-328580000 {
+ opp-hz = /bits/ 64 <328580000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
};
dispcc: clock-controller@af00000 {
@@ -3359,10 +3536,10 @@ dispcc: clock-controller@af00000 {
power-domains = <&rpmhpd SM8150_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
<0>,
<0>;
clock-names = "bi_tcxo",
--
2.31.1
Add MDSS and MDP nodes to sm8150.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Katherine Perez <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 ++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index ee40af469fab..38dbc39103ba 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3261,6 +3261,98 @@ camnoc_virt: interconnect@ac00000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ mdss: mdss@ae00000 {
+ compatible = "qcom,sm8150-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "ahb",
+ "core";
+
+ iommus = <&apps_smmu 0x800 0x420>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: mdp@ae010000 {
+ compatible = "qcom,sm8150-dpu";
+ reg = <0x0ae01000 0x84208>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <460000000>,
+ <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8150_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: mdp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sm8150-dispcc";
reg = <0 0x0af00000 0 0x10000>;
--
2.31.1
Add support for display to Microsoft Surface Duo.
Signed-off-by: Katherine Perez <[email protected]>
---
Changes in v3:
- Update dsi nodes to match mdss_dsi*
.../dts/qcom/sm8150-microsoft-surface-duo.dts | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
index 5901c28e6696..6135a820037b 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
@@ -270,6 +270,8 @@ vdda_hv_ebi1:
vdda_hv_ebi2:
vdda_hv_ebi3:
vdda_hv_refgen0:
+ vdda_mipi_dsi0_1p2:
+ vdda_mipi_dsi1_1p2:
vdda_qlink_hv_ck:
vreg_l3c_1p2: ldo3 {
regulator-min-microvolt = <1200000>;
@@ -359,6 +361,26 @@ vreg_l6f_2p85: ldo6 {
};
};
+&mdss_dsi0 {
+ status = "okay";
+ vdda-supply = <&vdda_mipi_dsi0_1p2>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+ vdds-supply = <&vdda_dsi_0_pll_0p9>;
+};
+
+&mdss_dsi1 {
+ status = "okay";
+ vdda-supply = <&vdda_mipi_dsi1_1p2>;
+};
+
+&mdss_dsi1_phy {
+ status = "okay";
+ vdds-supply = <&vdda_dsi_1_pll_0p9>;
+};
+
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@@ -430,6 +452,10 @@ &i2c19 {
/* MAX34417 @ 0x1e */
};
+&mdss {
+ status = "okay";
+};
+
&pon {
pwrkey {
status = "okay";
--
2.31.1
On Tue 16 Nov 19:35 CST 2021, Katherine Perez wrote:
> Hi Bjorn and Vinod,
>
> I'm trying to enable the display subsystem on SM8150 but am having
> trouble enabling the DISP_CC_MDSS_AHB_CLK. Trace shows "disp_cc_mdss_ahb_clk
> status stuck at off". Do you have any pointers on enabling this clock?
>
Hi Katherine,
This looks quite similar to an issue I'm chasing the past few days on
the sc8180x platform (which is derived from sm8150).
The problem seems to come down to the fact that we're not holding the
MMCX power-domain at a high enough performance_state through the boot
process and in contrast with other platforms these two are stricter in
their requirements.
For these platforms, the essence of the solution is that we need to hold
MMCX at nominal as long as there's display clocks ticking at high speed,
unfortunately there doesn't seem to be any quick way to achieve this -
so I now have a handful of patches that fix various aspects of this
issue, but not something reliable enough to post just yet.
Regards,
Bjorn
> msm_dsi_phy ae94400.dsi-phy: [drm:dsi_phy_driver_probe [msm]] *ERROR* dsi_phy_driver_probe: Unable to get ahb clk
> disp_cc-sm8250 af00000.clock-controller: supply mmcx not found, using dummy regulator
> platform ae96000.dsi: Fixing up cyclic dependency with ae00000.mdss:mdp@ae010000
> ------------[ cut here ]------------
> disp_cc_mdss_ahb_clk status stuck at 'off'
> WARNING: CPU: 6 PID: 76 at drivers/clk/qcom/clk-branch.c:91 clk_branch_wait+0x14c/0x164
> CPU: 6 PID: 76 Comm: kworker/u16:2 Not tainted 5.15.0 #17
> Hardware name: Microsoft Surface Duo (DT)
> Workqueue: events_unbound deferred_probe_work_func
> pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> pc : clk_branch_wait+0x14c/0x164
> lr : clk_branch_wait+0x14c/0x164
> sp : ffff80001078ba40
> x29: ffff80001078ba40 x28: 0000000000000000 x27: ffff65e6008e2100
> x26: ffffb8630ec8e278 x25: ffff65e60005e005 x24: ffffb8630ebc0f98
> x23: ffffb8630e234dd8 x22: 0000000000000001 x21: ffffb8630d5b8b60
> x20: 0000000000000000 x19: ffffb8630eb5e7b8 x18: 0000000000000030
> x17: 2e726f74616c7567 x16: ffffb8630d5a3800 x15: ffffffffffffffff
> x14: 0000000000000000 x13: 6f27207461206b63 x12: 7574732073757461
> x11: 77705f313439386d x10: 0000000000000027 x9 : ffffb8630cf974bc
> x8 : 0000000000000027 x7 : 0000000000000002 x6 : 0000000000000027
> x5 : ffff65e6f93cc9a8 x4 : ffff80001078b890 x3 : 0000000000000001
> x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff65e600851d80
> Call trace:
> clk_branch_wait+0x14c/0x164
> clk_branch2_enable+0x3c/0x60
> clk_core_enable+0x78/0x220
> clk_enable+0x38/0x60
> dsi_phy_enable_resource+0x98/0xac [msm]
> dsi_phy_driver_probe+0x29c/0x4f8 [msm]
> platform_probe+0x74/0xe4
> really_probe.part.0+0xa4/0x328
> __driver_probe_device+0xa0/0x150
> driver_probe_device+0x4c/0x164
> __device_attach_driver+0xc0/0x128
> bus_for_each_drv+0x84/0xe0
> __device_attach+0xe0/0x188
> device_initial_probe+0x20/0x2c
> bus_probe_device+0xa8/0xbc
> deferred_probe_work_func+0x90/0xc8
> process_one_work+0x1f4/0x43c
> worker_thread+0x78/0x4f0
> kthread+0x154/0x160
> ret_from_fork+0x10/0x20
> ---[ end trace 734ed75908fc6b0e ]---
>
> Katherine Perez (4):
> arm64: dts: qcom: sm8150: add dispcc node
> arm64: dts: qcom: sm8150: add display nodes
> arm64: dts: qcom: sm8150: add DSI display nodes
> arm64: dts: qcom: sm8150: display support for Microsoft Surface Duo
>
> .../dts/qcom/sm8150-microsoft-surface-duo.dts | 26 ++
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 292 ++++++++++++++++++
> 2 files changed, 318 insertions(+)
>
> --
> 2.31.1
>