A first serie to correct a large amount of DT warnings seen when
building with the W=1 option and mainly due to having several time
the same reg property (clock) or having unnecessary reg value.
The first 3 patches related to clocks require that recent serie [1] of
clock drivers improvements be first merged.
[1] https://lore.kernel.org/linux-clk/[email protected]/T/#t
Alain Volmat (12):
ARM: dts: sti: ensure unique unit-address in stih407-clock
ARM: dts: sti: ensure unique unit-address in stih410-clock
ARM: dts: sti: ensure unique unit-address in stih418-clock
ARM: dts: sti: move some nodes out of the soc section in
stih407-family.dtsi
ARM: dts: sti: update stih410-b2260 following stih407-family DT update
ARM: dts: sti: update stih418-b2199 following stih407-family DT update
ARM: dts: sti: update stihxxx-b2120 following stih407-family DT update
ARM: dts: sti: remove delta node from stih410.dtsi
ARM: dts: sti: move usb picophy nodes out of soc in stih410.dtsi
ARM: dts: sti: move usb picophy nodes out of soc in stih418.dtsi
ARM: dts: sti: move usb picophy nodes in stih410-b2120.dts
ARM: dts: sti: move usb picophy nodes in stih410-b2260.dts
arch/arm/boot/dts/stih407-clock.dtsi | 101 +++++-----
arch/arm/boot/dts/stih407-family.dtsi | 262 +++++++++++++-------------
arch/arm/boot/dts/stih410-b2120.dts | 16 +-
arch/arm/boot/dts/stih410-b2260.dts | 30 +--
arch/arm/boot/dts/stih410-clock.dtsi | 100 +++++-----
arch/arm/boot/dts/stih410.dtsi | 52 ++---
arch/arm/boot/dts/stih418-b2199.dts | 22 +--
arch/arm/boot/dts/stih418-clock.dtsi | 101 +++++-----
arch/arm/boot/dts/stih418.dtsi | 38 ++--
arch/arm/boot/dts/stihxxx-b2120.dtsi | 22 +--
10 files changed, 351 insertions(+), 393 deletions(-)
--
2.25.1
Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih407-clock.dtsi | 101 ++++++++++++---------------
1 file changed, 46 insertions(+), 55 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 9cce9541e26b..350bcfcf498b 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -29,7 +29,7 @@ clocks {
*/
clockgen-a9@92b0000 {
compatible = "st,clkgen-c32";
- reg = <0x92b0000 0xffff>;
+ reg = <0x92b0000 0x10000>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
@@ -37,32 +37,27 @@ clockgen_a9_pll: clockgen-a9-pll {
clocks = <&clk_sysin>;
};
- };
- /*
- * ARM CPU related clocks.
- */
- clk_m_a9: clk-m-a9@92b0000 {
- #clock-cells = <0>;
- compatible = "st,stih407-clkgen-a9-mux";
- reg = <0x92b0000 0x10000>;
-
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_s_c0_flexgen 13>,
- <&clk_m_a9_ext2f_div2>;
+ clk_m_a9: clk-m-a9 {
+ #clock-cells = <0>;
+ compatible = "st,stih407-clkgen-a9-mux";
+ clocks = <&clockgen_a9_pll 0>,
+ <&clockgen_a9_pll 0>,
+ <&clk_s_c0_flexgen 13>,
+ <&clk_m_a9_ext2f_div2>;
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -87,14 +82,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
};
};
- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-pll";
- reg = <0x9103000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clk_s_c0: clockgen-c@9103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@@ -113,6 +100,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 {
clocks = <&clk_sysin>;
};
+ clk_s_c0_quadfs: clk-s-c0-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-pll";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-c0";
@@ -142,18 +136,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
};
};
- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d0";
- reg = <0x9104000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d0@9104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
+ clk_s_d0_quadfs: clk-s-d0-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d0";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d0";
@@ -166,18 +159,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
};
};
- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d2";
- reg = <0x9106000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
+ clk_s_d2_quadfs: clk-s-d2-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d2";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d2";
@@ -192,18 +184,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
};
};
- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d3";
- reg = <0x9107000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d3@9107000 {
compatible = "st,clkgen-c32";
reg = <0x9107000 0x1000>;
+ clk_s_d3_quadfs: clk-s-d3-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d3";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d3_flexgen: clk-s-d3-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d3";
--
2.25.1
Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih418-clock.dtsi | 101 +++++++++++++--------------
1 file changed, 48 insertions(+), 53 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index e84c476b83ed..e1749e92a2e7 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -32,7 +32,7 @@ clocks {
*/
clockgen-a9@92b0000 {
compatible = "st,clkgen-c32";
- reg = <0x92b0000 0xffff>;
+ reg = <0x92b0000 0x10000>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
@@ -40,30 +40,29 @@ clockgen_a9_pll: clockgen-a9-pll {
clocks = <&clk_sysin>;
};
- };
-
- /*
- * ARM CPU related clocks.
- */
- clk_m_a9: clk-m-a9@92b0000 {
- #clock-cells = <0>;
- compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
- reg = <0x92b0000 0x10000>;
-
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_s_c0_flexgen 13>,
- <&clk_m_a9_ext2f_div2>;
/*
- * ARM Peripheral clock for timers
+ * ARM CPU related clocks.
*/
- arm_periph_clk: clk-m-a9-periphs {
+ clk_m_a9: clk-m-a9 {
#clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
+ compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+
+ clocks = <&clockgen_a9_pll 0>,
+ <&clockgen_a9_pll 0>,
+ <&clk_s_c0_flexgen 13>,
+ <&clk_m_a9_ext2f_div2>;
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -88,14 +87,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
};
};
- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-pll";
- reg = <0x9103000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clk_s_c0: clockgen-c@9103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@@ -114,6 +105,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 {
clocks = <&clk_sysin>;
};
+ clk_s_c0_quadfs: clk-s-c0-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-pll";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih418-c0";
@@ -143,18 +141,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
};
};
- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d0";
- reg = <0x9104000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d0@9104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
+ clk_s_d0_quadfs: clk-s-d0-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d0";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih410-d0";
@@ -167,18 +164,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
};
};
- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d2";
- reg = <0x9106000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
+ clk_s_d2_quadfs: clk-s-d2-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d2";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih418-d2";
@@ -193,18 +189,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
};
};
- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d3";
- reg = <0x9107000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d3@9107000 {
compatible = "st,clkgen-c32";
reg = <0x9107000 0x1000>;
+ clk_s_d3_quadfs: clk-s-d3-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d3";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d3_flexgen: clk-s-d3-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d3";
--
2.25.1
Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih410-clock.dtsi | 100 +++++++++++++--------------
1 file changed, 48 insertions(+), 52 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index 6b0e6d4477a3..abac98a1810b 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -32,7 +32,7 @@ clocks {
*/
clockgen-a9@92b0000 {
compatible = "st,clkgen-c32";
- reg = <0x92b0000 0xffff>;
+ reg = <0x92b0000 0x10000>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
@@ -40,29 +40,29 @@ clockgen_a9_pll: clockgen-a9-pll {
clocks = <&clk_sysin>;
};
- };
- /*
- * ARM CPU related clocks.
- */
- clk_m_a9: clk-m-a9@92b0000 {
- #clock-cells = <0>;
- compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
- reg = <0x92b0000 0x10000>;
-
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_s_c0_flexgen 13>,
- <&clk_m_a9_ext2f_div2>;
/*
- * ARM Peripheral clock for timers
+ * ARM CPU related clocks.
*/
- arm_periph_clk: clk-m-a9-periphs {
+ clk_m_a9: clk-m-a9 {
#clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
+ compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+
+ clocks = <&clockgen_a9_pll 0>,
+ <&clockgen_a9_pll 0>,
+ <&clk_s_c0_flexgen 13>,
+ <&clk_m_a9_ext2f_div2>;
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -87,14 +87,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
};
};
- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-pll";
- reg = <0x9103000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clk_s_c0: clockgen-c@9103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@@ -113,6 +105,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 {
clocks = <&clk_sysin>;
};
+ clk_s_c0_quadfs: clk-s-c0-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-pll";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih410-c0";
@@ -142,18 +141,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
};
};
- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d0";
- reg = <0x9104000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d0@9104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
+ clk_s_d0_quadfs: clk-s-d0-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d0";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih410-d0";
@@ -166,18 +164,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
};
};
- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d2";
- reg = <0x9106000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
+ clk_s_d2_quadfs: clk-s-d2-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d2";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d2";
@@ -192,18 +189,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
};
};
- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d3";
- reg = <0x9107000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d3@9107000 {
compatible = "st,clkgen-c32";
reg = <0x9107000 0x1000>;
+ clk_s_d3_quadfs: clk-s-d3-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d3";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d3_flexgen: clk-s-d3-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d3";
--
2.25.1
Put of the miphy28lp_phy node out of the soc section following similar
update within stih407-family.dtsi file update.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih418-b2199.dts | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
index b66e2b29edea..d21bcc7c1271 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -37,6 +37,17 @@ green {
};
};
+ miphy28lp_phy: miphy28lp {
+
+ phy_port0: port@9b22000 {
+ st,osc-rdy;
+ };
+
+ phy_port1: port@9b2a000 {
+ st,osc-force-ext;
+ };
+ };
+
soc {
sbc_serial0: serial@9530000 {
status = "okay";
@@ -84,17 +95,6 @@ mmc0: sdhci@9060000 {
non-removable;
};
- miphy28lp_phy: miphy28lp@0 {
-
- phy_port0: port@9b22000 {
- st,osc-rdy;
- };
-
- phy_port1: port@9b2a000 {
- st,osc-force-ext;
- };
- };
-
st_dwc3: dwc3@8f94000 {
status = "okay";
};
--
2.25.1
Put of the miphy28lp_phy node out of the soc section following similar
update within stih407-family.dtsi file update.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stihxxx-b2120.dtsi | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index d051f080e52e..4c72dedcd1be 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -71,6 +71,17 @@ codec {
};
};
+ miphy28lp_phy: miphy28lp {
+
+ phy_port0: port@9b22000 {
+ st,osc-rdy;
+ };
+
+ phy_port1: port@9b2a000 {
+ st,osc-force-ext;
+ };
+ };
+
soc {
sbc_serial0: serial@9530000 {
status = "okay";
@@ -128,17 +139,6 @@ hdmiddc: i2c@9541000 {
st,i2c-min-sda-pulse-width-us = <5>;
};
- miphy28lp_phy: miphy28lp@0 {
-
- phy_port0: port@9b22000 {
- st,osc-rdy;
- };
-
- phy_port1: port@9b2a000 {
- st,osc-force-ext;
- };
- };
-
st_dwc3: dwc3@8f94000 {
status = "okay";
};
--
2.25.1
The delta0 node within stih410.dtsi is identical to the
one already written within stih407-family.dtsi and included
within stih410.dtsi.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih410.dtsi | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 6d847019c554..fe83d9a522bf 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -274,16 +274,6 @@ thermal@91a0000 {
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
};
- delta0@0 {
- compatible = "st,st-delta";
- clock-names = "delta",
- "delta-st231",
- "delta-flash-promip";
- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
- <&clk_s_c0_flexgen CLK_ST231_DMU>,
- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
- };
-
sti-cec@94a087c {
compatible = "st,stih-cec";
reg = <0x94a087c 0x64>;
--
2.25.1
Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section.
Since they are controlled via syscfg, there is no reg property needed,
which is required when having the node within the soc section.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih410.dtsi | 42 ++++++++++++++++------------------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index fe83d9a522bf..ce2f62cf129b 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -12,31 +12,29 @@ aliases {
bdisp0 = &bdisp0;
};
- soc {
- usb2_picophy1: phy2@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0xf8 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY0_RESET>;
- reset-names = "global", "port";
+ usb2_picophy1: phy2 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core 0xf8 0xf4>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY0_RESET>;
+ reset-names = "global", "port";
+
+ status = "disabled";
+ };
- status = "disabled";
- };
+ usb2_picophy2: phy3 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core 0xfc 0xf4>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY1_RESET>;
+ reset-names = "global", "port";
- usb2_picophy2: phy3@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0xfc 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY1_RESET>;
- reset-names = "global", "port";
-
- status = "disabled";
- };
+ status = "disabled";
+ };
+ soc {
ohci0: usb@9a03c00 {
compatible = "st,st-ohci-300x";
reg = <0x9a03c00 0x100>;
--
2.25.1
Update usb picophy nodes out of the soc section following the
related update within the stih410.dtsi file.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih410-b2120.dts | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
index 9d3b118f5f0f..538ff98ca1b1 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -24,6 +24,14 @@ aliases {
ethernet0 = ðernet0;
};
+ usb2_picophy1: phy2 {
+ status = "okay";
+ };
+
+ usb2_picophy2: phy3 {
+ status = "okay";
+ };
+
soc {
mmc0: sdhci@9060000 {
@@ -33,14 +41,6 @@ mmc0: sdhci@9060000 {
sd-uhs-ddr50;
};
- usb2_picophy1: phy2@0 {
- status = "okay";
- };
-
- usb2_picophy2: phy3@0 {
- status = "okay";
- };
-
ohci0: usb@9a03c00 {
status = "okay";
};
--
2.25.1
Update usb picophy nodes out of the soc section following the
related update within the stih410.dtsi file.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih410-b2260.dts | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index c2d3b6de55d0..26d93f26f6d0 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -82,6 +82,14 @@ phy_port1: port@9b2a000 {
};
};
+ usb2_picophy1: phy2 {
+ status = "okay";
+ };
+
+ usb2_picophy2: phy3 {
+ status = "okay";
+ };
+
soc {
/* Low speed expansion connector */
uart0: serial@9830000 {
@@ -152,14 +160,6 @@ pwm1: pwm@9510000 {
status = "okay";
};
- usb2_picophy1: phy2@0 {
- status = "okay";
- };
-
- usb2_picophy2: phy3@0 {
- status = "okay";
- };
-
ohci0: usb@9a03c00 {
status = "okay";
};
--
2.25.1
Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section.
Since they are controlled via syscfg, there is no reg property needed,
which is required when having the node within the soc section.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih418.dtsi | 38 ++++++++++++++++------------------
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index 97eda4392fbe..b35b9b7a7ccc 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -26,31 +26,29 @@ cpu@3 {
};
};
+ usb2_picophy1: phy2 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core 0xf8 0xf4>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY0_RESET>;
+ reset-names = "global", "port";
+ };
+
+ usb2_picophy2: phy3 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core 0xfc 0xf4>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY1_RESET>;
+ reset-names = "global", "port";
+ };
+
soc {
rng11: rng@8a8a000 {
status = "disabled";
};
- usb2_picophy1: phy2@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0xf8 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY0_RESET>;
- reset-names = "global", "port";
- };
-
- usb2_picophy2: phy3@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0xfc 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY1_RESET>;
- reset-names = "global", "port";
- };
-
ohci0: usb@9a03c00 {
compatible = "st,st-ohci-300x";
reg = <0x9a03c00 0x100>;
--
2.25.1
Move all nodes without reg property out of the soc section of
stih407-family.dtsi. This avoid to set a <0> reg property.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 262 +++++++++++++-------------
1 file changed, 126 insertions(+), 136 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 21f3347a91d6..1713f7878117 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -115,37 +115,140 @@ pwm_regulator: pwm-regulator {
status = "okay";
};
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
+ restart: restart-controller {
+ compatible = "st,stih407-restart";
+ st,syscfg = <&syscfg_sbc_reg>;
+ status = "okay";
+ };
+
+ powerdown: powerdown-controller {
+ compatible = "st,stih407-powerdown";
+ #reset-cells = <1>;
+ };
+
+ softreset: softreset-controller {
+ compatible = "st,stih407-softreset";
+ #reset-cells = <1>;
+ };
+
+ picophyreset: picophyreset-controller {
+ compatible = "st,stih407-picophyreset";
+ #reset-cells = <1>;
+ };
+
+ irq-syscfg {
+ compatible = "st,stih407-irq-syscfg";
+ st,syscfg = <&syscfg_core>;
+ st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+ <ST_IRQ_SYSCFG_PMU_1>;
+ st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+ <ST_IRQ_SYSCFG_DISABLED>;
+ };
+
+ usb2_picophy0: phy1 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core 0x100 0xf4>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY2_RESET>;
+ reset-names = "global", "port";
+ };
+
+ miphy28lp_phy: miphy28lp {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
ranges;
- compatible = "simple-bus";
- restart: restart-controller@0 {
- compatible = "st,stih407-restart";
- reg = <0 0>;
- st,syscfg = <&syscfg_sbc_reg>;
- status = "okay";
- };
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew";
+
+ st,syscfg = <0x114 0x818 0xe0 0xec>;
+ #phy-cells = <1>;
- powerdown: powerdown-controller@0 {
- compatible = "st,stih407-powerdown";
- reg = <0 0>;
- #reset-cells = <1>;
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
};
- softreset: softreset-controller@0 {
- compatible = "st,stih407-softreset";
- reg = <0 0>;
- #reset-cells = <1>;
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew";
+
+ st,syscfg = <0x118 0x81c 0xe4 0xf0>;
+
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
};
- picophyreset: picophyreset-controller@0 {
- compatible = "st,stih407-picophyreset";
- reg = <0 0>;
- #reset-cells = <1>;
+ phy_port2: port@8f95000 {
+ reg = <0x8f95000 0xff>,
+ <0x8f90000 0xff>;
+ reg-names = "pipew",
+ "usb3-up";
+
+ st,syscfg = <0x11c 0x820>;
+
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
};
+ };
+
+ st231_gp0: st231-gp0 {
+ compatible = "st,st231-rproc";
+ memory-region = <&gp0_reserved>;
+ resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x22c>;
+ #mbox-cells = <1>;
+ mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
+ mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
+ };
+
+ st231_delta: st231-delta {
+ compatible = "st,st231-rproc";
+ memory-region = <&delta_reserved>;
+ resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x224>;
+ #mbox-cells = <1>;
+ mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
+ mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
+ };
+
+ delta0 {
+ compatible = "st,st-delta";
+ clock-names = "delta",
+ "delta-st231",
+ "delta-flash-promip";
+ clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
+ <&clk_s_c0_flexgen CLK_ST231_DMU>,
+ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
syscfg_sbc: sbc-syscfg@9620000 {
compatible = "st,stih407-sbc-syscfg", "syscon";
@@ -189,16 +292,6 @@ syscfg_lpm: lpm-syscfg@94b5100 {
reg = <0x94b5100 0x1000>;
};
- irq-syscfg@0 {
- compatible = "st,stih407-irq-syscfg";
- reg = <0 0>;
- st,syscfg = <&syscfg_core>;
- st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
- <ST_IRQ_SYSCFG_PMU_1>;
- st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
- <ST_IRQ_SYSCFG_DISABLED>;
- };
-
/* Display */
vtg_main: sti-vtg-main@8d02800 {
compatible = "st,vtg";
@@ -389,70 +482,6 @@ i2c@9541000 {
status = "disabled";
};
- usb2_picophy0: phy1@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0x100 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY2_RESET>;
- reset-names = "global", "port";
- };
-
- miphy28lp_phy: miphy28lp@0 {
- compatible = "st,miphy28lp-phy";
- st,syscfg = <&syscfg_core>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- reg = <0 0>;
-
- phy_port0: port@9b22000 {
- reg = <0x9b22000 0xff>,
- <0x9b09000 0xff>,
- <0x9b04000 0xff>;
- reg-names = "sata-up",
- "pcie-up",
- "pipew";
-
- st,syscfg = <0x114 0x818 0xe0 0xec>;
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
- };
-
- phy_port1: port@9b2a000 {
- reg = <0x9b2a000 0xff>,
- <0x9b19000 0xff>,
- <0x9b14000 0xff>;
- reg-names = "sata-up",
- "pcie-up",
- "pipew";
-
- st,syscfg = <0x118 0x81c 0xe4 0xf0>;
-
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
- };
-
- phy_port2: port@8f95000 {
- reg = <0x8f95000 0xff>,
- <0x8f90000 0xff>;
- reg-names = "pipew",
- "usb3-up";
-
- st,syscfg = <0x11c 0x820>;
-
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
- };
- };
-
spi@9840000 {
compatible = "st,comms-ssc4-spi";
reg = <0x9840000 0x110>;
@@ -815,34 +844,6 @@ mailbox3: mailbox@8f03000 {
status = "okay";
};
- st231_gp0: st231-gp0@0 {
- compatible = "st,st231-rproc";
- reg = <0 0>;
- memory-region = <&gp0_reserved>;
- resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
- reset-names = "sw_reset";
- clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
- clock-frequency = <600000000>;
- st,syscfg = <&syscfg_core 0x22c>;
- #mbox-cells = <1>;
- mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
- mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
- };
-
- st231_delta: st231-delta@0 {
- compatible = "st,st231-rproc";
- reg = <0 0>;
- memory-region = <&delta_reserved>;
- resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
- reset-names = "sw_reset";
- clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
- clock-frequency = <600000000>;
- st,syscfg = <&syscfg_core 0x224>;
- #mbox-cells = <1>;
- mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
- mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
- };
-
/* fdma audio */
fdma0: dma-controller@8e20000 {
compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
@@ -986,16 +987,5 @@ sti_uni_reader1: sti-uni-reader@8d84000 {
status = "disabled";
};
-
- delta0@0 {
- compatible = "st,st-delta";
- reg = <0 0>;
- clock-names = "delta",
- "delta-st231",
- "delta-flash-promip";
- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
- <&clk_s_c0_flexgen CLK_ST231_DMU>,
- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
- };
};
};
--
2.25.1
Put of the miphy28lp_phy node out of the soc section following similar
update within stih407-family.dtsi file update.
Signed-off-by: Alain Volmat <[email protected]>
---
arch/arm/boot/dts/stih410-b2260.dts | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index 9d579c16c295..c2d3b6de55d0 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -75,6 +75,13 @@ codec {
};
};
+ miphy28lp_phy: miphy28lp {
+
+ phy_port1: port@9b2a000 {
+ st,osc-force-ext;
+ };
+ };
+
soc {
/* Low speed expansion connector */
uart0: serial@9830000 {
@@ -196,13 +203,6 @@ hdmiddc: i2c@9541000 {
status = "okay";
};
- miphy28lp_phy: miphy28lp@0 {
-
- phy_port1: port@9b2a000 {
- st,osc-force-ext;
- };
- };
-
sata1: sata@9b28000 {
status = "okay";
};
--
2.25.1
Hi Alain
On 12/2/21 08:51, Alain Volmat wrote:
> Put of the miphy28lp_phy node out of the soc section following similar
> update within stih407-family.dtsi file update.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stihxxx-b2120.dtsi | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
> index d051f080e52e..4c72dedcd1be 100644
> --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
> +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
> @@ -71,6 +71,17 @@ codec {
> };
> };
>
> + miphy28lp_phy: miphy28lp {
> +
> + phy_port0: port@9b22000 {
> + st,osc-rdy;
> + };
> +
> + phy_port1: port@9b2a000 {
> + st,osc-force-ext;
> + };
> + };
> +
> soc {
> sbc_serial0: serial@9530000 {
> status = "okay";
> @@ -128,17 +139,6 @@ hdmiddc: i2c@9541000 {
> st,i2c-min-sda-pulse-width-us = <5>;
> };
>
> - miphy28lp_phy: miphy28lp@0 {
> -
> - phy_port0: port@9b22000 {
> - st,osc-rdy;
> - };
> -
> - phy_port1: port@9b2a000 {
> - st,osc-force-ext;
> - };
> - };
> -
> st_dwc3: dwc3@8f94000 {
> status = "okay";
> };
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
Pleased resubmit this series by squashing PATCH 1/4/5/6/7 together, the
compilation is broken and doesn't allow bisection.
The same with patches 9/11/12.
Thanks
Patrice
On 12/2/21 08:50, Alain Volmat wrote:
> A first serie to correct a large amount of DT warnings seen when
> building with the W=1 option and mainly due to having several time
> the same reg property (clock) or having unnecessary reg value.
>
> The first 3 patches related to clocks require that recent serie [1] of
> clock drivers improvements be first merged.
>
> [1] https://lore.kernel.org/linux-clk/[email protected]/T/#t
>
> Alain Volmat (12):
> ARM: dts: sti: ensure unique unit-address in stih407-clock
> ARM: dts: sti: ensure unique unit-address in stih410-clock
> ARM: dts: sti: ensure unique unit-address in stih418-clock
> ARM: dts: sti: move some nodes out of the soc section in
> stih407-family.dtsi
> ARM: dts: sti: update stih410-b2260 following stih407-family DT update
> ARM: dts: sti: update stih418-b2199 following stih407-family DT update
> ARM: dts: sti: update stihxxx-b2120 following stih407-family DT update
> ARM: dts: sti: remove delta node from stih410.dtsi
> ARM: dts: sti: move usb picophy nodes out of soc in stih410.dtsi
> ARM: dts: sti: move usb picophy nodes out of soc in stih418.dtsi
> ARM: dts: sti: move usb picophy nodes in stih410-b2120.dts
> ARM: dts: sti: move usb picophy nodes in stih410-b2260.dts
>
> arch/arm/boot/dts/stih407-clock.dtsi | 101 +++++-----
> arch/arm/boot/dts/stih407-family.dtsi | 262 +++++++++++++-------------
> arch/arm/boot/dts/stih410-b2120.dts | 16 +-
> arch/arm/boot/dts/stih410-b2260.dts | 30 +--
> arch/arm/boot/dts/stih410-clock.dtsi | 100 +++++-----
> arch/arm/boot/dts/stih410.dtsi | 52 ++---
> arch/arm/boot/dts/stih418-b2199.dts | 22 +--
> arch/arm/boot/dts/stih418-clock.dtsi | 101 +++++-----
> arch/arm/boot/dts/stih418.dtsi | 38 ++--
> arch/arm/boot/dts/stihxxx-b2120.dtsi | 22 +--
> 10 files changed, 351 insertions(+), 393 deletions(-)
>
Hi Alain
On 12/2/21 08:51, Alain Volmat wrote:
> Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section.
> Since they are controlled via syscfg, there is no reg property needed,
> which is required when having the node within the soc section.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih410.dtsi | 42 ++++++++++++++++------------------
> 1 file changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
> index fe83d9a522bf..ce2f62cf129b 100644
> --- a/arch/arm/boot/dts/stih410.dtsi
> +++ b/arch/arm/boot/dts/stih410.dtsi
> @@ -12,31 +12,29 @@ aliases {
> bdisp0 = &bdisp0;
> };
>
> - soc {
> - usb2_picophy1: phy2@0 {
> - compatible = "st,stih407-usb2-phy";
> - reg = <0 0>;
> - #phy-cells = <0>;
> - st,syscfg = <&syscfg_core 0xf8 0xf4>;
> - resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> - <&picophyreset STIH407_PICOPHY0_RESET>;
> - reset-names = "global", "port";
> + usb2_picophy1: phy2 {
> + compatible = "st,stih407-usb2-phy";
> + #phy-cells = <0>;
> + st,syscfg = <&syscfg_core 0xf8 0xf4>;
> + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> + <&picophyreset STIH407_PICOPHY0_RESET>;
> + reset-names = "global", "port";
> +
> + status = "disabled";
> + };
>
> - status = "disabled";
> - };
> + usb2_picophy2: phy3 {
> + compatible = "st,stih407-usb2-phy";
> + #phy-cells = <0>;
> + st,syscfg = <&syscfg_core 0xfc 0xf4>;
> + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> + <&picophyreset STIH407_PICOPHY1_RESET>;
> + reset-names = "global", "port";
>
> - usb2_picophy2: phy3@0 {
> - compatible = "st,stih407-usb2-phy";
> - reg = <0 0>;
> - #phy-cells = <0>;
> - st,syscfg = <&syscfg_core 0xfc 0xf4>;
> - resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> - <&picophyreset STIH407_PICOPHY1_RESET>;
> - reset-names = "global", "port";
> -
> - status = "disabled";
> - };
> + status = "disabled";
> + };
>
> + soc {
> ohci0: usb@9a03c00 {
> compatible = "st,st-ohci-300x";
> reg = <0x9a03c00 0x100>;
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:51, Alain Volmat wrote:
> Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section.
> Since they are controlled via syscfg, there is no reg property needed,
> which is required when having the node within the soc section.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih418.dtsi | 38 ++++++++++++++++------------------
> 1 file changed, 18 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
> index 97eda4392fbe..b35b9b7a7ccc 100644
> --- a/arch/arm/boot/dts/stih418.dtsi
> +++ b/arch/arm/boot/dts/stih418.dtsi
> @@ -26,31 +26,29 @@ cpu@3 {
> };
> };
>
> + usb2_picophy1: phy2 {
> + compatible = "st,stih407-usb2-phy";
> + #phy-cells = <0>;
> + st,syscfg = <&syscfg_core 0xf8 0xf4>;
> + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> + <&picophyreset STIH407_PICOPHY0_RESET>;
> + reset-names = "global", "port";
> + };
> +
> + usb2_picophy2: phy3 {
> + compatible = "st,stih407-usb2-phy";
> + #phy-cells = <0>;
> + st,syscfg = <&syscfg_core 0xfc 0xf4>;
> + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> + <&picophyreset STIH407_PICOPHY1_RESET>;
> + reset-names = "global", "port";
> + };
> +
> soc {
> rng11: rng@8a8a000 {
> status = "disabled";
> };
>
> - usb2_picophy1: phy2@0 {
> - compatible = "st,stih407-usb2-phy";
> - reg = <0 0>;
> - #phy-cells = <0>;
> - st,syscfg = <&syscfg_core 0xf8 0xf4>;
> - resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> - <&picophyreset STIH407_PICOPHY0_RESET>;
> - reset-names = "global", "port";
> - };
> -
> - usb2_picophy2: phy3@0 {
> - compatible = "st,stih407-usb2-phy";
> - reg = <0 0>;
> - #phy-cells = <0>;
> - st,syscfg = <&syscfg_core 0xfc 0xf4>;
> - resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> - <&picophyreset STIH407_PICOPHY1_RESET>;
> - reset-names = "global", "port";
> - };
> -
> ohci0: usb@9a03c00 {
> compatible = "st,st-ohci-300x";
> reg = <0x9a03c00 0x100>;
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:50, Alain Volmat wrote:
> Move quadfs and a9-mux clocks nodes into clockgen nodes so
> that they can get the reg property from the parent node and
> ensure only one node has the address.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih410-clock.dtsi | 100 +++++++++++++--------------
> 1 file changed, 48 insertions(+), 52 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
> index 6b0e6d4477a3..abac98a1810b 100644
> --- a/arch/arm/boot/dts/stih410-clock.dtsi
> +++ b/arch/arm/boot/dts/stih410-clock.dtsi
> @@ -32,7 +32,7 @@ clocks {
> */
> clockgen-a9@92b0000 {
> compatible = "st,clkgen-c32";
> - reg = <0x92b0000 0xffff>;
> + reg = <0x92b0000 0x10000>;
>
> clockgen_a9_pll: clockgen-a9-pll {
> #clock-cells = <1>;
> @@ -40,29 +40,29 @@ clockgen_a9_pll: clockgen-a9-pll {
>
> clocks = <&clk_sysin>;
> };
> - };
>
> - /*
> - * ARM CPU related clocks.
> - */
> - clk_m_a9: clk-m-a9@92b0000 {
> - #clock-cells = <0>;
> - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
> - reg = <0x92b0000 0x10000>;
> -
> - clocks = <&clockgen_a9_pll 0>,
> - <&clockgen_a9_pll 0>,
> - <&clk_s_c0_flexgen 13>,
> - <&clk_m_a9_ext2f_div2>;
> /*
> - * ARM Peripheral clock for timers
> + * ARM CPU related clocks.
> */
> - arm_periph_clk: clk-m-a9-periphs {
> + clk_m_a9: clk-m-a9 {
> #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&clk_m_a9>;
> - clock-div = <2>;
> - clock-mult = <1>;
> + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
> +
> + clocks = <&clockgen_a9_pll 0>,
> + <&clockgen_a9_pll 0>,
> + <&clk_s_c0_flexgen 13>,
> + <&clk_m_a9_ext2f_div2>;
> +
> + /*
> + * ARM Peripheral clock for timers
> + */
> + arm_periph_clk: clk-m-a9-periphs {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clocks = <&clk_m_a9>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> };
> };
>
> @@ -87,14 +87,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
> };
> };
>
> - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-pll";
> - reg = <0x9103000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clk_s_c0: clockgen-c@9103000 {
> compatible = "st,clkgen-c32";
> reg = <0x9103000 0x1000>;
> @@ -113,6 +105,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 {
> clocks = <&clk_sysin>;
> };
>
> + clk_s_c0_quadfs: clk-s-c0-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-pll";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_c0_flexgen: clk-s-c0-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih410-c0";
> @@ -142,18 +141,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
> };
> };
>
> - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d0";
> - reg = <0x9104000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d0@9104000 {
> compatible = "st,clkgen-c32";
> reg = <0x9104000 0x1000>;
>
> + clk_s_d0_quadfs: clk-s-d0-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d0";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d0_flexgen: clk-s-d0-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih410-d0";
> @@ -166,18 +164,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
> };
> };
>
> - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d2";
> - reg = <0x9106000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d2@9106000 {
> compatible = "st,clkgen-c32";
> reg = <0x9106000 0x1000>;
>
> + clk_s_d2_quadfs: clk-s-d2-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d2";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d2_flexgen: clk-s-d2-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih407-d2";
> @@ -192,18 +189,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
> };
> };
>
> - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d3";
> - reg = <0x9107000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d3@9107000 {
> compatible = "st,clkgen-c32";
> reg = <0x9107000 0x1000>;
>
> + clk_s_d3_quadfs: clk-s-d3-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d3";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d3_flexgen: clk-s-d3-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih407-d3";
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
HI Alain
On 12/2/21 08:51, Alain Volmat wrote:
> Update usb picophy nodes out of the soc section following the
> related update within the stih410.dtsi file.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih410-b2120.dts | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
> index 9d3b118f5f0f..538ff98ca1b1 100644
> --- a/arch/arm/boot/dts/stih410-b2120.dts
> +++ b/arch/arm/boot/dts/stih410-b2120.dts
> @@ -24,6 +24,14 @@ aliases {
> ethernet0 = ðernet0;
> };
>
> + usb2_picophy1: phy2 {
> + status = "okay";
> + };
> +
> + usb2_picophy2: phy3 {
> + status = "okay";
> + };
> +
> soc {
>
> mmc0: sdhci@9060000 {
> @@ -33,14 +41,6 @@ mmc0: sdhci@9060000 {
> sd-uhs-ddr50;
> };
>
> - usb2_picophy1: phy2@0 {
> - status = "okay";
> - };
> -
> - usb2_picophy2: phy3@0 {
> - status = "okay";
> - };
> -
> ohci0: usb@9a03c00 {
> status = "okay";
> };
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:50, Alain Volmat wrote:
> Put of the miphy28lp_phy node out of the soc section following similar
> update within stih407-family.dtsi file update.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih410-b2260.dts | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
> index 9d579c16c295..c2d3b6de55d0 100644
> --- a/arch/arm/boot/dts/stih410-b2260.dts
> +++ b/arch/arm/boot/dts/stih410-b2260.dts
> @@ -75,6 +75,13 @@ codec {
> };
> };
>
> + miphy28lp_phy: miphy28lp {
> +
> + phy_port1: port@9b2a000 {
> + st,osc-force-ext;
> + };
> + };
> +
> soc {
> /* Low speed expansion connector */
> uart0: serial@9830000 {
> @@ -196,13 +203,6 @@ hdmiddc: i2c@9541000 {
> status = "okay";
> };
>
> - miphy28lp_phy: miphy28lp@0 {
> -
> - phy_port1: port@9b2a000 {
> - st,osc-force-ext;
> - };
> - };
> -
> sata1: sata@9b28000 {
> status = "okay";
> };
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:50, Alain Volmat wrote:
> Put of the miphy28lp_phy node out of the soc section following similar
> update within stih407-family.dtsi file update.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih418-b2199.dts | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
> index b66e2b29edea..d21bcc7c1271 100644
> --- a/arch/arm/boot/dts/stih418-b2199.dts
> +++ b/arch/arm/boot/dts/stih418-b2199.dts
> @@ -37,6 +37,17 @@ green {
> };
> };
>
> + miphy28lp_phy: miphy28lp {
> +
> + phy_port0: port@9b22000 {
> + st,osc-rdy;
> + };
> +
> + phy_port1: port@9b2a000 {
> + st,osc-force-ext;
> + };
> + };
> +
> soc {
> sbc_serial0: serial@9530000 {
> status = "okay";
> @@ -84,17 +95,6 @@ mmc0: sdhci@9060000 {
> non-removable;
> };
>
> - miphy28lp_phy: miphy28lp@0 {
> -
> - phy_port0: port@9b22000 {
> - st,osc-rdy;
> - };
> -
> - phy_port1: port@9b2a000 {
> - st,osc-force-ext;
> - };
> - };
> -
> st_dwc3: dwc3@8f94000 {
> status = "okay";
> };
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:51, Alain Volmat wrote:
> The delta0 node within stih410.dtsi is identical to the
> one already written within stih407-family.dtsi and included
> within stih410.dtsi.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih410.dtsi | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
> index 6d847019c554..fe83d9a522bf 100644
> --- a/arch/arm/boot/dts/stih410.dtsi
> +++ b/arch/arm/boot/dts/stih410.dtsi
> @@ -274,16 +274,6 @@ thermal@91a0000 {
> interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
> };
>
> - delta0@0 {
> - compatible = "st,st-delta";
> - clock-names = "delta",
> - "delta-st231",
> - "delta-flash-promip";
> - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
> - <&clk_s_c0_flexgen CLK_ST231_DMU>,
> - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
> - };
> -
> sti-cec@94a087c {
> compatible = "st,stih-cec";
> reg = <0x94a087c 0x64>;
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:50, Alain Volmat wrote:
> Move all nodes without reg property out of the soc section of
> stih407-family.dtsi. This avoid to set a <0> reg property.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih407-family.dtsi | 262 +++++++++++++-------------
> 1 file changed, 126 insertions(+), 136 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
> index 21f3347a91d6..1713f7878117 100644
> --- a/arch/arm/boot/dts/stih407-family.dtsi
> +++ b/arch/arm/boot/dts/stih407-family.dtsi
> @@ -115,37 +115,140 @@ pwm_regulator: pwm-regulator {
> status = "okay";
> };
>
> - soc {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&intc>;
> + restart: restart-controller {
> + compatible = "st,stih407-restart";
> + st,syscfg = <&syscfg_sbc_reg>;
> + status = "okay";
> + };
> +
> + powerdown: powerdown-controller {
> + compatible = "st,stih407-powerdown";
> + #reset-cells = <1>;
> + };
> +
> + softreset: softreset-controller {
> + compatible = "st,stih407-softreset";
> + #reset-cells = <1>;
> + };
> +
> + picophyreset: picophyreset-controller {
> + compatible = "st,stih407-picophyreset";
> + #reset-cells = <1>;
> + };
> +
> + irq-syscfg {
> + compatible = "st,stih407-irq-syscfg";
> + st,syscfg = <&syscfg_core>;
> + st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
> + <ST_IRQ_SYSCFG_PMU_1>;
> + st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
> + <ST_IRQ_SYSCFG_DISABLED>;
> + };
> +
> + usb2_picophy0: phy1 {
> + compatible = "st,stih407-usb2-phy";
> + #phy-cells = <0>;
> + st,syscfg = <&syscfg_core 0x100 0xf4>;
> + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> + <&picophyreset STIH407_PICOPHY2_RESET>;
> + reset-names = "global", "port";
> + };
> +
> + miphy28lp_phy: miphy28lp {
> + compatible = "st,miphy28lp-phy";
> + st,syscfg = <&syscfg_core>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> ranges;
> - compatible = "simple-bus";
>
> - restart: restart-controller@0 {
> - compatible = "st,stih407-restart";
> - reg = <0 0>;
> - st,syscfg = <&syscfg_sbc_reg>;
> - status = "okay";
> - };
> + phy_port0: port@9b22000 {
> + reg = <0x9b22000 0xff>,
> + <0x9b09000 0xff>,
> + <0x9b04000 0xff>;
> + reg-names = "sata-up",
> + "pcie-up",
> + "pipew";
> +
> + st,syscfg = <0x114 0x818 0xe0 0xec>;
> + #phy-cells = <1>;
>
> - powerdown: powerdown-controller@0 {
> - compatible = "st,stih407-powerdown";
> - reg = <0 0>;
> - #reset-cells = <1>;
> + reset-names = "miphy-sw-rst";
> + resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
> };
>
> - softreset: softreset-controller@0 {
> - compatible = "st,stih407-softreset";
> - reg = <0 0>;
> - #reset-cells = <1>;
> + phy_port1: port@9b2a000 {
> + reg = <0x9b2a000 0xff>,
> + <0x9b19000 0xff>,
> + <0x9b14000 0xff>;
> + reg-names = "sata-up",
> + "pcie-up",
> + "pipew";
> +
> + st,syscfg = <0x118 0x81c 0xe4 0xf0>;
> +
> + #phy-cells = <1>;
> +
> + reset-names = "miphy-sw-rst";
> + resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
> };
>
> - picophyreset: picophyreset-controller@0 {
> - compatible = "st,stih407-picophyreset";
> - reg = <0 0>;
> - #reset-cells = <1>;
> + phy_port2: port@8f95000 {
> + reg = <0x8f95000 0xff>,
> + <0x8f90000 0xff>;
> + reg-names = "pipew",
> + "usb3-up";
> +
> + st,syscfg = <0x11c 0x820>;
> +
> + #phy-cells = <1>;
> +
> + reset-names = "miphy-sw-rst";
> + resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
> };
> + };
> +
> + st231_gp0: st231-gp0 {
> + compatible = "st,st231-rproc";
> + memory-region = <&gp0_reserved>;
> + resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
> + reset-names = "sw_reset";
> + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
> + clock-frequency = <600000000>;
> + st,syscfg = <&syscfg_core 0x22c>;
> + #mbox-cells = <1>;
> + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
> + mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
> + };
> +
> + st231_delta: st231-delta {
> + compatible = "st,st231-rproc";
> + memory-region = <&delta_reserved>;
> + resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
> + reset-names = "sw_reset";
> + clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
> + clock-frequency = <600000000>;
> + st,syscfg = <&syscfg_core 0x224>;
> + #mbox-cells = <1>;
> + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
> + mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
> + };
> +
> + delta0 {
> + compatible = "st,st-delta";
> + clock-names = "delta",
> + "delta-st231",
> + "delta-flash-promip";
> + clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
> + <&clk_s_c0_flexgen CLK_ST231_DMU>,
> + <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&intc>;
> + ranges;
> + compatible = "simple-bus";
>
> syscfg_sbc: sbc-syscfg@9620000 {
> compatible = "st,stih407-sbc-syscfg", "syscon";
> @@ -189,16 +292,6 @@ syscfg_lpm: lpm-syscfg@94b5100 {
> reg = <0x94b5100 0x1000>;
> };
>
> - irq-syscfg@0 {
> - compatible = "st,stih407-irq-syscfg";
> - reg = <0 0>;
> - st,syscfg = <&syscfg_core>;
> - st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
> - <ST_IRQ_SYSCFG_PMU_1>;
> - st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
> - <ST_IRQ_SYSCFG_DISABLED>;
> - };
> -
> /* Display */
> vtg_main: sti-vtg-main@8d02800 {
> compatible = "st,vtg";
> @@ -389,70 +482,6 @@ i2c@9541000 {
> status = "disabled";
> };
>
> - usb2_picophy0: phy1@0 {
> - compatible = "st,stih407-usb2-phy";
> - reg = <0 0>;
> - #phy-cells = <0>;
> - st,syscfg = <&syscfg_core 0x100 0xf4>;
> - resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> - <&picophyreset STIH407_PICOPHY2_RESET>;
> - reset-names = "global", "port";
> - };
> -
> - miphy28lp_phy: miphy28lp@0 {
> - compatible = "st,miphy28lp-phy";
> - st,syscfg = <&syscfg_core>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> - reg = <0 0>;
> -
> - phy_port0: port@9b22000 {
> - reg = <0x9b22000 0xff>,
> - <0x9b09000 0xff>,
> - <0x9b04000 0xff>;
> - reg-names = "sata-up",
> - "pcie-up",
> - "pipew";
> -
> - st,syscfg = <0x114 0x818 0xe0 0xec>;
> - #phy-cells = <1>;
> -
> - reset-names = "miphy-sw-rst";
> - resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
> - };
> -
> - phy_port1: port@9b2a000 {
> - reg = <0x9b2a000 0xff>,
> - <0x9b19000 0xff>,
> - <0x9b14000 0xff>;
> - reg-names = "sata-up",
> - "pcie-up",
> - "pipew";
> -
> - st,syscfg = <0x118 0x81c 0xe4 0xf0>;
> -
> - #phy-cells = <1>;
> -
> - reset-names = "miphy-sw-rst";
> - resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
> - };
> -
> - phy_port2: port@8f95000 {
> - reg = <0x8f95000 0xff>,
> - <0x8f90000 0xff>;
> - reg-names = "pipew",
> - "usb3-up";
> -
> - st,syscfg = <0x11c 0x820>;
> -
> - #phy-cells = <1>;
> -
> - reset-names = "miphy-sw-rst";
> - resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
> - };
> - };
> -
> spi@9840000 {
> compatible = "st,comms-ssc4-spi";
> reg = <0x9840000 0x110>;
> @@ -815,34 +844,6 @@ mailbox3: mailbox@8f03000 {
> status = "okay";
> };
>
> - st231_gp0: st231-gp0@0 {
> - compatible = "st,st231-rproc";
> - reg = <0 0>;
> - memory-region = <&gp0_reserved>;
> - resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
> - reset-names = "sw_reset";
> - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
> - clock-frequency = <600000000>;
> - st,syscfg = <&syscfg_core 0x22c>;
> - #mbox-cells = <1>;
> - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
> - mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
> - };
> -
> - st231_delta: st231-delta@0 {
> - compatible = "st,st231-rproc";
> - reg = <0 0>;
> - memory-region = <&delta_reserved>;
> - resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
> - reset-names = "sw_reset";
> - clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
> - clock-frequency = <600000000>;
> - st,syscfg = <&syscfg_core 0x224>;
> - #mbox-cells = <1>;
> - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
> - mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
> - };
> -
> /* fdma audio */
> fdma0: dma-controller@8e20000 {
> compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
> @@ -986,16 +987,5 @@ sti_uni_reader1: sti-uni-reader@8d84000 {
>
> status = "disabled";
> };
> -
> - delta0@0 {
> - compatible = "st,st-delta";
> - reg = <0 0>;
> - clock-names = "delta",
> - "delta-st231",
> - "delta-flash-promip";
> - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
> - <&clk_s_c0_flexgen CLK_ST231_DMU>,
> - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
> - };
> };
> };
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:50, Alain Volmat wrote:
> Move quadfs and a9-mux clocks nodes into clockgen nodes so
> that they can get the reg property from the parent node and
> ensure only one node has the address.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih418-clock.dtsi | 101 +++++++++++++--------------
> 1 file changed, 48 insertions(+), 53 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
> index e84c476b83ed..e1749e92a2e7 100644
> --- a/arch/arm/boot/dts/stih418-clock.dtsi
> +++ b/arch/arm/boot/dts/stih418-clock.dtsi
> @@ -32,7 +32,7 @@ clocks {
> */
> clockgen-a9@92b0000 {
> compatible = "st,clkgen-c32";
> - reg = <0x92b0000 0xffff>;
> + reg = <0x92b0000 0x10000>;
>
> clockgen_a9_pll: clockgen-a9-pll {
> #clock-cells = <1>;
> @@ -40,30 +40,29 @@ clockgen_a9_pll: clockgen-a9-pll {
>
> clocks = <&clk_sysin>;
> };
> - };
> -
> - /*
> - * ARM CPU related clocks.
> - */
> - clk_m_a9: clk-m-a9@92b0000 {
> - #clock-cells = <0>;
> - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
> - reg = <0x92b0000 0x10000>;
> -
> - clocks = <&clockgen_a9_pll 0>,
> - <&clockgen_a9_pll 0>,
> - <&clk_s_c0_flexgen 13>,
> - <&clk_m_a9_ext2f_div2>;
>
> /*
> - * ARM Peripheral clock for timers
> + * ARM CPU related clocks.
> */
> - arm_periph_clk: clk-m-a9-periphs {
> + clk_m_a9: clk-m-a9 {
> #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> - clocks = <&clk_m_a9>;
> - clock-div = <2>;
> - clock-mult = <1>;
> + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
> +
> + clocks = <&clockgen_a9_pll 0>,
> + <&clockgen_a9_pll 0>,
> + <&clk_s_c0_flexgen 13>,
> + <&clk_m_a9_ext2f_div2>;
> +
> + /*
> + * ARM Peripheral clock for timers
> + */
> + arm_periph_clk: clk-m-a9-periphs {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clocks = <&clk_m_a9>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> };
> };
>
> @@ -88,14 +87,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
> };
> };
>
> - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-pll";
> - reg = <0x9103000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clk_s_c0: clockgen-c@9103000 {
> compatible = "st,clkgen-c32";
> reg = <0x9103000 0x1000>;
> @@ -114,6 +105,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 {
> clocks = <&clk_sysin>;
> };
>
> + clk_s_c0_quadfs: clk-s-c0-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-pll";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_c0_flexgen: clk-s-c0-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih418-c0";
> @@ -143,18 +141,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
> };
> };
>
> - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d0";
> - reg = <0x9104000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d0@9104000 {
> compatible = "st,clkgen-c32";
> reg = <0x9104000 0x1000>;
>
> + clk_s_d0_quadfs: clk-s-d0-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d0";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d0_flexgen: clk-s-d0-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih410-d0";
> @@ -167,18 +164,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
> };
> };
>
> - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d2";
> - reg = <0x9106000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d2@9106000 {
> compatible = "st,clkgen-c32";
> reg = <0x9106000 0x1000>;
>
> + clk_s_d2_quadfs: clk-s-d2-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d2";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d2_flexgen: clk-s-d2-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih418-d2";
> @@ -193,18 +189,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
> };
> };
>
> - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d3";
> - reg = <0x9107000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d3@9107000 {
> compatible = "st,clkgen-c32";
> reg = <0x9107000 0x1000>;
>
> + clk_s_d3_quadfs: clk-s-d3-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d3";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d3_flexgen: clk-s-d3-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih407-d3";
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:50, Alain Volmat wrote:
> Move quadfs and a9-mux clocks nodes into clockgen nodes so
> that they can get the reg property from the parent node and
> ensure only one node has the address.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih407-clock.dtsi | 101 ++++++++++++---------------
> 1 file changed, 46 insertions(+), 55 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
> index 9cce9541e26b..350bcfcf498b 100644
> --- a/arch/arm/boot/dts/stih407-clock.dtsi
> +++ b/arch/arm/boot/dts/stih407-clock.dtsi
> @@ -29,7 +29,7 @@ clocks {
> */
> clockgen-a9@92b0000 {
> compatible = "st,clkgen-c32";
> - reg = <0x92b0000 0xffff>;
> + reg = <0x92b0000 0x10000>;
>
> clockgen_a9_pll: clockgen-a9-pll {
> #clock-cells = <1>;
> @@ -37,32 +37,27 @@ clockgen_a9_pll: clockgen-a9-pll {
>
> clocks = <&clk_sysin>;
> };
> - };
>
> - /*
> - * ARM CPU related clocks.
> - */
> - clk_m_a9: clk-m-a9@92b0000 {
> - #clock-cells = <0>;
> - compatible = "st,stih407-clkgen-a9-mux";
> - reg = <0x92b0000 0x10000>;
> -
> - clocks = <&clockgen_a9_pll 0>,
> - <&clockgen_a9_pll 0>,
> - <&clk_s_c0_flexgen 13>,
> - <&clk_m_a9_ext2f_div2>;
> + clk_m_a9: clk-m-a9 {
> + #clock-cells = <0>;
> + compatible = "st,stih407-clkgen-a9-mux";
>
> + clocks = <&clockgen_a9_pll 0>,
> + <&clockgen_a9_pll 0>,
> + <&clk_s_c0_flexgen 13>,
> + <&clk_m_a9_ext2f_div2>;
>
> - /*
> - * ARM Peripheral clock for timers
> - */
> - arm_periph_clk: clk-m-a9-periphs {
> - #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> + /*
> + * ARM Peripheral clock for timers
> + */
> + arm_periph_clk: clk-m-a9-periphs {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
>
> - clocks = <&clk_m_a9>;
> - clock-div = <2>;
> - clock-mult = <1>;
> + clocks = <&clk_m_a9>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> };
> };
>
> @@ -87,14 +82,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
> };
> };
>
> - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-pll";
> - reg = <0x9103000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clk_s_c0: clockgen-c@9103000 {
> compatible = "st,clkgen-c32";
> reg = <0x9103000 0x1000>;
> @@ -113,6 +100,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 {
> clocks = <&clk_sysin>;
> };
>
> + clk_s_c0_quadfs: clk-s-c0-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-pll";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_c0_flexgen: clk-s-c0-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih407-c0";
> @@ -142,18 +136,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
> };
> };
>
> - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d0";
> - reg = <0x9104000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d0@9104000 {
> compatible = "st,clkgen-c32";
> reg = <0x9104000 0x1000>;
>
> + clk_s_d0_quadfs: clk-s-d0-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d0";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d0_flexgen: clk-s-d0-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih407-d0";
> @@ -166,18 +159,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
> };
> };
>
> - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d2";
> - reg = <0x9106000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d2@9106000 {
> compatible = "st,clkgen-c32";
> reg = <0x9106000 0x1000>;
>
> + clk_s_d2_quadfs: clk-s-d2-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d2";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d2_flexgen: clk-s-d2-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih407-d2";
> @@ -192,18 +184,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
> };
> };
>
> - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
> - #clock-cells = <1>;
> - compatible = "st,quadfs-d3";
> - reg = <0x9107000 0x1000>;
> -
> - clocks = <&clk_sysin>;
> - };
> -
> clockgen-d3@9107000 {
> compatible = "st,clkgen-c32";
> reg = <0x9107000 0x1000>;
>
> + clk_s_d3_quadfs: clk-s-d3-quadfs {
> + #clock-cells = <1>;
> + compatible = "st,quadfs-d3";
> +
> + clocks = <&clk_sysin>;
> + };
> +
> clk_s_d3_flexgen: clk-s-d3-flexgen {
> #clock-cells = <1>;
> compatible = "st,flexgen", "st,flexgen-stih407-d3";
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Alain
On 12/2/21 08:51, Alain Volmat wrote:
> Update usb picophy nodes out of the soc section following the
> related update within the stih410.dtsi file.
>
> Signed-off-by: Alain Volmat <[email protected]>
> ---
> arch/arm/boot/dts/stih410-b2260.dts | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
> index c2d3b6de55d0..26d93f26f6d0 100644
> --- a/arch/arm/boot/dts/stih410-b2260.dts
> +++ b/arch/arm/boot/dts/stih410-b2260.dts
> @@ -82,6 +82,14 @@ phy_port1: port@9b2a000 {
> };
> };
>
> + usb2_picophy1: phy2 {
> + status = "okay";
> + };
> +
> + usb2_picophy2: phy3 {
> + status = "okay";
> + };
> +
> soc {
> /* Low speed expansion connector */
> uart0: serial@9830000 {
> @@ -152,14 +160,6 @@ pwm1: pwm@9510000 {
> status = "okay";
> };
>
> - usb2_picophy1: phy2@0 {
> - status = "okay";
> - };
> -
> - usb2_picophy2: phy3@0 {
> - status = "okay";
> - };
> -
> ohci0: usb@9a03c00 {
> status = "okay";
> };
Reviewed-by: Patrice Chotard <[email protected]>
Thanks
Patrice
Hi Patrice,
oups, sorry about that. I send a v2 with several patches squashed
together to fix compilation issues.
Alain
On Thu, Feb 10, 2022 at 09:59:40AM +0100, Patrice CHOTARD wrote:
> Hi Alain
>
> Pleased resubmit this series by squashing PATCH 1/4/5/6/7 together, the
> compilation is broken and doesn't allow bisection.
>
> The same with patches 9/11/12.
>
> Thanks
> Patrice
>
> On 12/2/21 08:50, Alain Volmat wrote:
> > A first serie to correct a large amount of DT warnings seen when
> > building with the W=1 option and mainly due to having several time
> > the same reg property (clock) or having unnecessary reg value.
> >
> > The first 3 patches related to clocks require that recent serie [1] of
> > clock drivers improvements be first merged.
> >
> > [1] https://lore.kernel.org/linux-clk/[email protected]/T/#t
> >
> > Alain Volmat (12):
> > ARM: dts: sti: ensure unique unit-address in stih407-clock
> > ARM: dts: sti: ensure unique unit-address in stih410-clock
> > ARM: dts: sti: ensure unique unit-address in stih418-clock
> > ARM: dts: sti: move some nodes out of the soc section in
> > stih407-family.dtsi
> > ARM: dts: sti: update stih410-b2260 following stih407-family DT update
> > ARM: dts: sti: update stih418-b2199 following stih407-family DT update
> > ARM: dts: sti: update stihxxx-b2120 following stih407-family DT update
> > ARM: dts: sti: remove delta node from stih410.dtsi
> > ARM: dts: sti: move usb picophy nodes out of soc in stih410.dtsi
> > ARM: dts: sti: move usb picophy nodes out of soc in stih418.dtsi
> > ARM: dts: sti: move usb picophy nodes in stih410-b2120.dts
> > ARM: dts: sti: move usb picophy nodes in stih410-b2260.dts
> >
> > arch/arm/boot/dts/stih407-clock.dtsi | 101 +++++-----
> > arch/arm/boot/dts/stih407-family.dtsi | 262 +++++++++++++-------------
> > arch/arm/boot/dts/stih410-b2120.dts | 16 +-
> > arch/arm/boot/dts/stih410-b2260.dts | 30 +--
> > arch/arm/boot/dts/stih410-clock.dtsi | 100 +++++-----
> > arch/arm/boot/dts/stih410.dtsi | 52 ++---
> > arch/arm/boot/dts/stih418-b2199.dts | 22 +--
> > arch/arm/boot/dts/stih418-clock.dtsi | 101 +++++-----
> > arch/arm/boot/dts/stih418.dtsi | 38 ++--
> > arch/arm/boot/dts/stihxxx-b2120.dtsi | 22 +--
> > 10 files changed, 351 insertions(+), 393 deletions(-)
> >