2021-08-25 01:13:29

by Chun-Jie Chen

Subject: [v1 2/5] arm64: dts: mediatek: Correct UART clock of MT8192

update uart0 and uart1 bus clock to the real one.

Signed-off-by: Chun-Jie Chen <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 2b63d2ea6cb6..31d135e18784 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -327,7 +327,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
@@ -337,7 +337,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
clock-names = "baud", "bus";
status = "disabled";
};
--
2.18.0

2021-12-06 16:44:17

by Nícolas F. R. A. Prado

Subject: Re: [v1 2/5] arm64: dts: mediatek: Correct UART clock of MT8192

Hi,

On Wed, Aug 25, 2021 at 09:11:17AM +0800, Chun-Jie Chen wrote:
> update uart0 and uart1 bus clock to the real one.

With the same commit message improvement from patch 1:

Reviewed-by: N?colas F. R. A. Prado <[email protected]>

Thanks,
N?colas

>
> Signed-off-by: Chun-Jie Chen <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 2b63d2ea6cb6..31d135e18784 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -327,7 +327,7 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11002000 0 0x1000>;
> interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
> clock-names = "baud", "bus";
> status = "disabled";
> };
> @@ -337,7 +337,7 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11003000 0 0x1000>;
> interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
> clock-names = "baud", "bus";
> status = "disabled";
> };
> --
> 2.18.0
>
>