Some Ethernet improvement for i.MX8M serials.
Joakim Zhang (7):
arm64: dts: imx8mn-evk: add hardware reset for FEC PHY
arm64: dts: imx8mp-evk: add hardware reset for EQOS PHY
arm64: dts: imx8m: disable smart eee for FEC PHY
arm64: dts: imx8m: configure FEC PHY VDDIO voltage
arm64: dts: imx8mp-evk: disable CLKOUT clock for ENET PHY
arm64: dts: imx8m: remove unused "nvmem_macaddr_swap" property for FEC
arm64: dts: imx8mp: add mac address for EQOS
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 7 +++++++
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 -
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 9 +++++++++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 -
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 5 +++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 ++++++-
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 5 +++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 -
8 files changed, 32 insertions(+), 4 deletions(-)
--
2.17.1
Add hardware reset for FEC PHY.
Signed-off-by: Joakim Zhang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 85e65f8719ea..30e7c9d56090 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -97,6 +97,8 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
};
};
};
--
2.17.1
As commit 390b4cad8148 ("net: phy: at803x: add support for configuring SmartEEE")
described, disable PHY smart eee by default.
Signed-off-by: Joakim Zhang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index e033d0257b5a..50b3bbb662d5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -116,6 +116,7 @@
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
+ qca,disable-smarteee;
};
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 30e7c9d56090..342f57e8cf61 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -99,6 +99,7 @@
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
+ qca,disable-smarteee;
};
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index b83df77195ec..a9e33548a2f3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -169,6 +169,7 @@
reg = <0>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
+ qca,disable-smarteee;
};
};
};
--
2.17.1
As commit 798a1807ab13 ("arm64: dts: imx8mp-evk: Improve the Ethernet PHY
description") described, add hardware reset for EQOS PHY.
Signed-off-by: Joakim Zhang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 7b99fad6e4d6..a7dc0d160f79 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -97,6 +97,9 @@
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
};
};
};
--
2.17.1
As commit 2f664823a470 ("net: phy: at803x: add device tree binding")
described, configure FEC PHY VDDIO voltage according to board design.
Signed-off-by: Joakim Zhang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++
3 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 50b3bbb662d5..3bac87b7e142 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -117,6 +117,12 @@
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
qca,disable-smarteee;
+ vddio-supply = <&vddio>;
+
+ vddio: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
};
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 342f57e8cf61..c3f15192b76c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -100,6 +100,12 @@
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
qca,disable-smarteee;
+ vddio-supply = <&vddio>;
+
+ vddio: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
};
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index a9e33548a2f3..c96d23fe3010 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -170,6 +170,10 @@
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
qca,disable-smarteee;
+ vddio-supply = <&vddh>;
+
+ vddh: vddh-regulator {
+ };
};
};
};
--
2.17.1
According to commit 0a4355c2b7f8 ("net: phy: realtek: add dt property to
disable CLKOUT clock"), diable CLKOUT clock for FEC PHY to save power on
i.MX8MP EVK board.
Signed-off-by: Joakim Zhang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index a7dc0d160f79..cf03a82f9dcd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -100,6 +100,7 @@
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
+ realtek,clkout-disable;
};
};
};
@@ -123,6 +124,7 @@
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
+ realtek,clkout-disable;
};
};
};
--
2.17.1
Remove unused "nvmem_macaddr_swap" property for FEC, there is no info in both
dt-binding and driver, so it's safe to remove it.
Reviewed-by: Ahmad Fatoum <[email protected]>
Signed-off-by: Joakim Zhang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 -
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 -
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 -
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 -
4 files changed, 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index c2f3f118f82e..3de86e2e471c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1054,7 +1054,6 @@
fsl,num-rx-queues = <3>;
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
- nvmem_macaddr_swap;
fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index da6c942fb7f9..8cc69b26cfed 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -948,7 +948,6 @@
fsl,num-rx-queues = <3>;
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
- nvmem_macaddr_swap;
fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 04d259de5667..ec178c5fa99c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -832,7 +832,6 @@
nvmem-cells = <ð_mac1>;
nvmem-cell-names = "mac-address";
fsl,stop-mode = <&gpr 0x10 3>;
- nvmem_macaddr_swap;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 972766b67a15..cf3600b4fea6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1292,7 +1292,6 @@
fsl,num-rx-queues = <3>;
nvmem-cells = <&fec_mac_address>;
nvmem-cell-names = "mac-address";
- nvmem_macaddr_swap;
fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
status = "disabled";
};
--
2.17.1
Add mac address in efuse, so that EQOS driver can parse it from nvmem
cell.
Signed-off-by: Joakim Zhang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index ec178c5fa99c..cc8a063d856d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -369,6 +369,10 @@
eth_mac1: mac-address@90 {
reg = <0x90 6>;
};
+
+ eth_mac2: mac-address@96 {
+ reg = <0x96 6>;
+ };
};
anatop: anatop@30360000 {
@@ -853,6 +857,8 @@
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <100000000>, <125000000>;
+ nvmem-cells = <ð_mac2>;
+ nvmem-cell-names = "mac-address";
intf_mode = <&gpr 0x4>;
status = "disabled";
};
--
2.17.1
On 23.11.21 09:05, Joakim Zhang wrote:
> Add hardware reset for FEC PHY.
>
> Signed-off-by: Joakim Zhang <[email protected]>
Reviewed-by: Ahmad Fatoum <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> index 85e65f8719ea..30e7c9d56090 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> @@ -97,6 +97,8 @@
> ethphy0: ethernet-phy@0 {
> compatible = "ethernet-phy-ieee802.3-c22";
> reg = <0>;
> + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> };
> };
> };
>
--
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31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Tue, Nov 23, 2021 at 04:05:03PM +0800, Joakim Zhang wrote:
> As commit 2f664823a470 ("net: phy: at803x: add device tree binding")
> described, configure FEC PHY VDDIO voltage according to board design.
>
> Signed-off-by: Joakim Zhang <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 6 ++++++
> arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 6 ++++++
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++
> 3 files changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index 50b3bbb662d5..3bac87b7e142 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -117,6 +117,12 @@
> reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> reset-assert-us = <10000>;
> qca,disable-smarteee;
> + vddio-supply = <&vddio>;
> +
> + vddio: vddio-regulator {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> };
> };
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> index 342f57e8cf61..c3f15192b76c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> @@ -100,6 +100,12 @@
> reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> reset-assert-us = <10000>;
> qca,disable-smarteee;
> + vddio-supply = <&vddio>;
> +
> + vddio: vddio-regulator {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> };
> };
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index a9e33548a2f3..c96d23fe3010 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -170,6 +170,10 @@
> reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> reset-assert-us = <10000>;
> qca,disable-smarteee;
> + vddio-supply = <&vddh>;
> +
> + vddh: vddh-regulator {
> + };
Why does this need to be different from the one on imx8mm-evk and
imx8mn-evk?
Shawn
> };
> };
> };
> --
> 2.17.1
>
Hi Shawn,
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: 2021??12??6?? 9:16
> To: Joakim Zhang <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; dl-linux-imx <[email protected]>;
> [email protected]; [email protected]
> Subject: Re: [PATCH 4/7] arm64: dts: imx8m: configure FEC PHY VDDIO
> voltage
>
> On Tue, Nov 23, 2021 at 04:05:03PM +0800, Joakim Zhang wrote:
> > As commit 2f664823a470 ("net: phy: at803x: add device tree binding")
> > described, configure FEC PHY VDDIO voltage according to board design.
> >
> > Signed-off-by: Joakim Zhang <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 6 ++++++
> > arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 6 ++++++
> > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++
> > 3 files changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > index 50b3bbb662d5..3bac87b7e142 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > @@ -117,6 +117,12 @@
> > reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> > reset-assert-us = <10000>;
> > qca,disable-smarteee;
> > + vddio-supply = <&vddio>;
> > +
> > + vddio: vddio-regulator {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + };
> > };
> > };
> > };
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > index 342f57e8cf61..c3f15192b76c 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > @@ -100,6 +100,12 @@
> > reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> > reset-assert-us = <10000>;
> > qca,disable-smarteee;
> > + vddio-supply = <&vddio>;
> > +
> > + vddio: vddio-regulator {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + };
> > };
> > };
> > };
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > index a9e33548a2f3..c96d23fe3010 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > @@ -170,6 +170,10 @@
> > reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> > reset-assert-us = <10000>;
> > qca,disable-smarteee;
> > + vddio-supply = <&vddh>;
> > +
> > + vddh: vddh-regulator {
> > + };
>
> Why does this need to be different from the one on imx8mm-evk and
> imx8mn-evk?
It's depend on RGMII_IO voltage out from SoC and PHY reference design.
For 8MM/MN:
SoC RGMII_IO is 1.8V, and board design use "Reference Design, 1.5/1.8 V RGMII I/O", PHY default work on 1.5V, so we need configure PHY to work on 1.8V.
For 8MQ:
SoC RGMII_IO is 2.5V, and board design use "Reference Design, 2.5 V/ 3.3 V RGMII I/O", PHY default work on 2.5V.
Best Regards,
Joakim Zhang
> Shawn
>
> > };
> > };
> > };
> > --
> > 2.17.1
> >
On Mon, Dec 06, 2021 at 01:59:18AM +0000, Joakim Zhang wrote:
>
> Hi Shawn,
>
> > -----Original Message-----
> > From: Shawn Guo <[email protected]>
> > Sent: 2021年12月6日 9:16
> > To: Joakim Zhang <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected];
> > [email protected]; dl-linux-imx <[email protected]>;
> > [email protected]; [email protected]
> > Subject: Re: [PATCH 4/7] arm64: dts: imx8m: configure FEC PHY VDDIO
> > voltage
> >
> > On Tue, Nov 23, 2021 at 04:05:03PM +0800, Joakim Zhang wrote:
> > > As commit 2f664823a470 ("net: phy: at803x: add device tree binding")
> > > described, configure FEC PHY VDDIO voltage according to board design.
> > >
> > > Signed-off-by: Joakim Zhang <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 6 ++++++
> > > arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 6 ++++++
> > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++
> > > 3 files changed, 16 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > index 50b3bbb662d5..3bac87b7e142 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > @@ -117,6 +117,12 @@
> > > reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> > > reset-assert-us = <10000>;
> > > qca,disable-smarteee;
> > > + vddio-supply = <&vddio>;
> > > +
> > > + vddio: vddio-regulator {
> > > + regulator-min-microvolt = <1800000>;
> > > + regulator-max-microvolt = <1800000>;
> > > + };
> > > };
> > > };
> > > };
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > index 342f57e8cf61..c3f15192b76c 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > @@ -100,6 +100,12 @@
> > > reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> > > reset-assert-us = <10000>;
> > > qca,disable-smarteee;
> > > + vddio-supply = <&vddio>;
> > > +
> > > + vddio: vddio-regulator {
> > > + regulator-min-microvolt = <1800000>;
> > > + regulator-max-microvolt = <1800000>;
> > > + };
> > > };
> > > };
> > > };
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > index a9e33548a2f3..c96d23fe3010 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > @@ -170,6 +170,10 @@
> > > reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> > > reset-assert-us = <10000>;
> > > qca,disable-smarteee;
> > > + vddio-supply = <&vddh>;
> > > +
> > > + vddh: vddh-regulator {
> > > + };
> >
> > Why does this need to be different from the one on imx8mm-evk and
> > imx8mn-evk?
>
> It's depend on RGMII_IO voltage out from SoC and PHY reference design.
>
> For 8MM/MN:
> SoC RGMII_IO is 1.8V, and board design use "Reference Design, 1.5/1.8 V RGMII I/O", PHY default work on 1.5V, so we need configure PHY to work on 1.8V.
> For 8MQ:
> SoC RGMII_IO is 2.5V, and board design use "Reference Design, 2.5 V/ 3.3 V RGMII I/O", PHY default work on 2.5V.
Hmm, why do you not specify 2.5V with regulator-min[max]-microvolt then?
Also, why is the regulator named vddh instead of vddio?
Shawn
>
> Best Regards,
> Joakim Zhang
> > Shawn
> >
> > > };
> > > };
> > > };
> > > --
> > > 2.17.1
> > >
Hi Shawn,
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: 2021年12月6日 10:06
> To: Joakim Zhang <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; dl-linux-imx <[email protected]>;
> [email protected]; [email protected]
> Subject: Re: [PATCH 4/7] arm64: dts: imx8m: configure FEC PHY VDDIO
> voltage
>
> On Mon, Dec 06, 2021 at 01:59:18AM +0000, Joakim Zhang wrote:
> >
> > Hi Shawn,
> >
> > > -----Original Message-----
> > > From: Shawn Guo <[email protected]>
> > > Sent: 2021年12月6日 9:16
> > > To: Joakim Zhang <[email protected]>
> > > Cc: [email protected]; [email protected];
> > > [email protected]; [email protected]; dl-linux-imx
> > > <[email protected]>; [email protected];
> > > [email protected]
> > > Subject: Re: [PATCH 4/7] arm64: dts: imx8m: configure FEC PHY VDDIO
> > > voltage
> > >
> > > On Tue, Nov 23, 2021 at 04:05:03PM +0800, Joakim Zhang wrote:
> > > > As commit 2f664823a470 ("net: phy: at803x: add device tree
> > > > binding") described, configure FEC PHY VDDIO voltage according to
> board design.
> > > >
> > > > Signed-off-by: Joakim Zhang <[email protected]>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 6 ++++++
> > > > arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 6 ++++++
> > > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++
> > > > 3 files changed, 16 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > index 50b3bbb662d5..3bac87b7e142 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > @@ -117,6 +117,12 @@
> > > > reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> > > > reset-assert-us = <10000>;
> > > > qca,disable-smarteee;
> > > > + vddio-supply = <&vddio>;
> > > > +
> > > > + vddio: vddio-regulator {
> > > > + regulator-min-microvolt = <1800000>;
> > > > + regulator-max-microvolt = <1800000>;
> > > > + };
> > > > };
> > > > };
> > > > };
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > > index 342f57e8cf61..c3f15192b76c 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > > @@ -100,6 +100,12 @@
> > > > reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> > > > reset-assert-us = <10000>;
> > > > qca,disable-smarteee;
> > > > + vddio-supply = <&vddio>;
> > > > +
> > > > + vddio: vddio-regulator {
> > > > + regulator-min-microvolt = <1800000>;
> > > > + regulator-max-microvolt = <1800000>;
> > > > + };
> > > > };
> > > > };
> > > > };
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > > index a9e33548a2f3..c96d23fe3010 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > > @@ -170,6 +170,10 @@
> > > > reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> > > > reset-assert-us = <10000>;
> > > > qca,disable-smarteee;
> > > > + vddio-supply = <&vddh>;
> > > > +
> > > > + vddh: vddh-regulator {
> > > > + };
> > >
> > > Why does this need to be different from the one on imx8mm-evk and
> > > imx8mn-evk?
> >
> > It's depend on RGMII_IO voltage out from SoC and PHY reference design.
> >
> > For 8MM/MN:
> > SoC RGMII_IO is 1.8V, and board design use "Reference Design, 1.5/1.8
> V RGMII I/O", PHY default work on 1.5V, so we need configure PHY to work
> on 1.8V.
> > For 8MQ:
> > SoC RGMII_IO is 2.5V, and board design use "Reference Design, 2.5 V/
> 3.3 V RGMII I/O", PHY default work on 2.5V.
>
> Hmm, why do you not specify 2.5V with regulator-min[max]-microvolt then?
> Also, why is the regulator named vddh instead of vddio?
The RGMII I/O voltage at PHY side could from VDDIO_REG or VDDH_REG, it depends on
how the design of board according to AT8031 block guide.
And the phy driver implement this align to the phy guide.
Could you please have a look at the commit or the binding?
commit 2f664823a47021ae029fe91272adbf0a223e477f
Author: Michael Walle <[email protected]>
Date: Wed Nov 6 23:36:14 2019 +0100
net: phy: at803x: add device tree binding
Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Documentation/devicetree/bindings/net/qca,ar803x.yaml
vddio-regulator and vddh-regulator
Best Regards,
Joakim Zhang
> Shawn
>
> >
> > Best Regards,
> > Joakim Zhang
> > > Shawn
> > >
> > > > };
> > > > };
> > > > };
> > > > --
> > > > 2.17.1
> > > >
On Tue, Nov 23, 2021 at 04:05:00PM +0800, Joakim Zhang wrote:
> Add hardware reset for FEC PHY.
>
> Signed-off-by: Joakim Zhang <[email protected]>
Applied all, thanks!