Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins)
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.
This patch series contains a patch for fixing wrong hwirq base in
irq handler.
Please help to review.
Steven Lee (1):
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.17.1
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.
Signed-off-by: Steven Lee <[email protected]>
---
drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 3d6ef37a7702..b3a9b8488f11 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, ®, 32)
- generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
+ generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
}
chained_irq_exit(ic, desc);
--
2.17.1
On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <[email protected]> wrote:
>
> Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> The hwirq base for each sgpio bank should be multiples of 64 rather than
> multiples of 32.
>
> Signed-off-by: Steven Lee <[email protected]>
> ---
> drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> index 3d6ef37a7702..b3a9b8488f11 100644
> --- a/drivers/gpio/gpio-aspeed-sgpio.c
> +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> reg = ioread32(bank_reg(data, bank, reg_irq_status));
>
> for_each_set_bit(p, ®, 32)
> - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> }
>
> chained_irq_exit(ic, desc);
> --
> 2.17.1
>
Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
Bart
On Wed, Dec 22, 2021 at 10:18 AM Bartosz Golaszewski <[email protected]> wrote:
>
> On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <[email protected]> wrote:
> >
> > Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> > The hwirq base for each sgpio bank should be multiples of 64 rather than
> > multiples of 32.
> >
> > Signed-off-by: Steven Lee <[email protected]>
> > ---
> > drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > index 3d6ef37a7702..b3a9b8488f11 100644
> > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> > reg = ioread32(bank_reg(data, bank, reg_irq_status));
> >
> > for_each_set_bit(p, ®, 32)
> > - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> > + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> > }
> >
> > chained_irq_exit(ic, desc);
> > --
> > 2.17.1
> >
>
> Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
>
> Bart
I don't want to delay it anymore, it looks good so I queued it for fixes.
Bart
On Mon, 3 Jan 2022 at 09:50, Bartosz Golaszewski <[email protected]> wrote:
>
> On Wed, Dec 22, 2021 at 10:18 AM Bartosz Golaszewski <[email protected]> wrote:
> >
> > On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <[email protected]> wrote:
> > >
> > > Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> > > The hwirq base for each sgpio bank should be multiples of 64 rather than
> > > multiples of 32.
> > >
> > > Signed-off-by: Steven Lee <[email protected]>
> > > ---
> > > drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > > index 3d6ef37a7702..b3a9b8488f11 100644
> > > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > > @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> > > reg = ioread32(bank_reg(data, bank, reg_irq_status));
> > >
> > > for_each_set_bit(p, ®, 32)
> > > - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> > > + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> > > }
> > >
> > > chained_irq_exit(ic, desc);
> > > --
> > > 2.17.1
> > >
> >
> > Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
> >
> > Bart
>
> I don't want to delay it anymore, it looks good so I queued it for fixes.
Thanks for queuing. We were on leave over the holiday break, so no
time for reviewing kernel patches.
Cheers,
Joel