2022-01-24 19:47:58

by Taniya Das

Subject: [PATCH v1] clk qcom: clk-alpha-pll: Update to use determine rate ops for PLL

On 32 bit devices, where the PLL requires to support the frequency
beyond the range of the `long int` the round rate ops cannot support.
Thus update the clk_ops to use determine rate instead.

While at it also fix the code in RCG.

Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/clk-alpha-pll.c | 21 +++++++++++++++++----
drivers/clk/qcom/clk-rcg2.c | 10 +++++-----
2 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 4406cf609aae..4e2e93cd8c8b 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -812,12 +812,25 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}

-static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
+ struct clk_hw *parent_hw;
+ unsigned long rrate, prate;
u32 l, a;

- return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
+ parent_hw = clk_hw_get_parent(hw);
+ if (!parent_hw)
+ return -EINVAL;
+
+ prate = clk_hw_get_rate(parent_hw);
+ rrate = alpha_huayra_pll_round_rate(req->rate, prate, &l, &a);
+
+ req->best_parent_hw = parent_hw;
+ req->best_parent_rate = prate;
+ req->rate = rrate;
+
+ return 0;
}

static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
@@ -946,7 +959,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops = {
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = alpha_pll_huayra_recalc_rate,
- .round_rate = alpha_pll_huayra_round_rate,
+ .determine_rate = alpha_pll_huayra_determine_rate,
.set_rate = alpha_pll_huayra_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 036c8071c07a..19614ece4e9d 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -147,19 +147,19 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
static unsigned long
calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
{
+ u64 tmp = rate;
+
if (hid_div) {
- rate *= 2;
- rate /= hid_div + 1;
+ tmp *= 2;
+ do_div(tmp, hid_div + 1);
}

if (mode) {
- u64 tmp = rate;
tmp *= m;
do_div(tmp, n);
- rate = tmp;
}

- return rate;
+ return tmp;
}

static unsigned long
--
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of the Code Aurora Forum, hosted by the Linux Foundation.

2022-01-25 08:30:12

by Stephen Boyd

Subject: Re: [PATCH v1] clk qcom: clk-alpha-pll: Update to use determine rate ops for PLL

Quoting Taniya Das (2022-01-24 09:48:05)
> On 32 bit devices, where the PLL requires to support the frequency
> beyond the range of the `long int` the round rate ops cannot support.
> Thus update the clk_ops to use determine rate instead.
>
> While at it also fix the code in RCG.

Please split this into two patches, and tag with Fixes