In emulation of writing to cr8, one of the lowest four bits in TPR[3:0]
is kept.
According to Intel SDM 10.8.6.1(baremetal scenario):
"APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0";
and SDM 28.3(use TPR shadow):
"MOV to CR8. The instruction stores bits 3:0 of its source operand into
bits 7:4 of VTPR; the remainder of VTPR (bits 3:0 and bits 31:8) are
cleared.";
and AMD's APM 16.6.4:
"Task Priority Sub-class (TPS)-Bits 3 : 0. The TPS field indicates the
current sub-priority to be used when arbitrating lowest-priority messages.
This field is written with zero when TPR is written using the architectural
CR8 register.";
so in KVM emulated scenario, clear TPR[3:0] to make a consistent behavior
as in other scenarios.
This doesn't impact evaluation and delivery of pending virtual interrupts
because processor does not use the processor-priority sub-class to
determine which interrupts to delivery and which to inhibit.
Sub-class is used by hardware to arbitrate lowest priority interrupts,
but KVM just does a round-robin style delivery.
Fixes: b93463aa59d6 ("KVM: Accelerated apic support")
Signed-off-by: Zhenzhong Duan <[email protected]>
Reviewed-by: Sean Christopherson <[email protected]>
---
v2: Add Sean's comments and "Fixes:" to patch description
arch/x86/kvm/lapic.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index d7e6fde82d25..306025db9959 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2242,10 +2242,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
{
- struct kvm_lapic *apic = vcpu->arch.apic;
-
- apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
- | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
+ apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4);
}
u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
--
2.25.1
On 2/10/22 10:45, Zhenzhong Duan wrote:
> In emulation of writing to cr8, one of the lowest four bits in TPR[3:0]
> is kept.
>
> According to Intel SDM 10.8.6.1(baremetal scenario):
> "APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0";
>
> and SDM 28.3(use TPR shadow):
> "MOV to CR8. The instruction stores bits 3:0 of its source operand into
> bits 7:4 of VTPR; the remainder of VTPR (bits 3:0 and bits 31:8) are
> cleared.";
>
> and AMD's APM 16.6.4:
> "Task Priority Sub-class (TPS)-Bits 3 : 0. The TPS field indicates the
> current sub-priority to be used when arbitrating lowest-priority messages.
> This field is written with zero when TPR is written using the architectural
> CR8 register.";
>
> so in KVM emulated scenario, clear TPR[3:0] to make a consistent behavior
> as in other scenarios.
>
> This doesn't impact evaluation and delivery of pending virtual interrupts
> because processor does not use the processor-priority sub-class to
> determine which interrupts to delivery and which to inhibit.
>
> Sub-class is used by hardware to arbitrate lowest priority interrupts,
> but KVM just does a round-robin style delivery.
>
> Fixes: b93463aa59d6 ("KVM: Accelerated apic support")
> Signed-off-by: Zhenzhong Duan <[email protected]>
> Reviewed-by: Sean Christopherson <[email protected]>
> ---
> v2: Add Sean's comments and "Fixes:" to patch description
>
> arch/x86/kvm/lapic.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index d7e6fde82d25..306025db9959 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2242,10 +2242,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
>
> void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
> {
> - struct kvm_lapic *apic = vcpu->arch.apic;
> -
> - apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
> - | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
> + apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4);
> }
>
> u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
Queued, thanks.
Paolo