Hi,
This series was triggered by the discussion in [1], and we realized we
need to cleanup the definitions in K3 SoC. Usage of kvm with gic-v2
compatibility is a bit niche usecase, but valid and possible with A53
and A72 even though the GIC500 instantiation is done with no backward
compatibility.
Nishanth Menon (5):
arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
10 files changed, 25 insertions(+), 5 deletions(-)
[1] https://lore.kernel.org/all/[email protected]/
--
2.31.1
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/[email protected]/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Cc: [email protected]
Reported-by: Marc Zyngier <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
---
Testing: based on next-20220215
j7200-evm: https://gist.github.com/nmenon/23a7844a794a0123af9b211eee2b7d0b
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 05a627ad6cdc..16684a2f054d 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -54,7 +54,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 64fef4e67d76..b6da0454cc5b 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -129,6 +129,7 @@ cbass_main: bus@100000 {
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
--
2.31.1
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A53 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/[email protected]/
[3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map
Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC")
Cc: [email protected] # 5.10+
Reported-by: Marc Zyngier <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
---
Testing: based on next-20220215
am65xx-evm Log: https://gist.github.com/nmenon/7e086c4d96d928429b9cd987a6e16b82
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ce8bb4a61011..e749343acced 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -35,7 +35,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0x90000>; /* GICR */
+ <0x00 0x01880000 0x00 0x90000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index a58a39fa42db..c538a0bf3cdd 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -86,6 +86,7 @@ cbass_main: bus@100000 {
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
--
2.31.1
On Tue, 15 Feb 2022 20:10:03 +0000,
Nishanth Menon <[email protected]> wrote:
>
> Hi,
>
> This series was triggered by the discussion in [1], and we realized we
> need to cleanup the definitions in K3 SoC. Usage of kvm with gic-v2
> compatibility is a bit niche usecase, but valid and possible with A53
> and A72 even though the GIC500 instantiation is done with no backward
> compatibility.
>
> Nishanth Menon (5):
> arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
>
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
> 10 files changed, 25 insertions(+), 5 deletions(-)
>
> [1] https://lore.kernel.org/all/[email protected]/
For the series:
Acked-by: Marc Zyngier <[email protected]>
M.
--
Without deviation from the norm, progress is not possible.
Hi Nishanth Menon,
On Tue, 15 Feb 2022 14:10:03 -0600, Nishanth Menon wrote:
> This series was triggered by the discussion in [1], and we realized we
> need to cleanup the definitions in K3 SoC. Usage of kvm with gic-v2
> compatibility is a bit niche usecase, but valid and possible with A53
> and A72 even though the GIC500 instantiation is done with no backward
> compatibility.
>
> Nishanth Menon (5):
> arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/5] arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
commit: 8cae268b70f387ff9e697ccd62fb2384079124e7
[2/5] arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
commit: a06ed27f3bc63ab9e10007dc0118d910908eb045
[3/5] arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
commit: 1a307cc299430dd7139d351a3b8941f493dfa885
[4/5] arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
commit: de60edf1be3d42d4a1b303b41c7c53b2f865726e
[5/5] arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
commit: a966803781fc5e1875511db9392b0d16174c5dd2
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Regards,
Nishanth Menon
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