LinuxLists.cc - [PATCH v3 00/32] mtd: spi-nor: move vendor specific code into vendor modules

2022-02-21 10:14:22

Subject: [PATCH v3 00/32] mtd: spi-nor: move vendor specific code into vendor modules

It turns out that most of the special status register handling is
specific for a particular vendor. I.e. Xilinx has some different
opcodes for the status register read, Micron has an additional FSR
register and Spansion has these flags integrated into the SR.

Create a callback to ready() where a flash chip can register its
own function. This will let us move all the vendor specific stuff
out of the core into the vendor modules.

As a preparation step, unify all function and object names in the
vendor modules. For the sake of consistency and better readability
of the code flow, I also converted the setup() callback to be
optional.

Please note that this is only compile-time tested.

Changes since v2:
- use family_nor_ instead of just family_ prefix
- fix function doc

Changes since v1:
- rename/unify function names inside the vendor modules.
- make local functions static
- fix function doc typo
- use late_init hook to set fsr_ready op
- Use uppercase and period in comments
- Add comments for the vendor flags
- move coding style change in spi_nor_sr_ready() into own patch
- new patch to add missing parenthesis in S3AN_INFO()
- add missing function prefix rename patch for the spansion module

Michael Walle (32):
mtd: spi-nor: atmel: unify function names
mtd: spi-nor: catalyst: unify function names
mtd: spi-nor: eon: unify function names
mtd: spi-nor: esmt: unify function names
mtd: spi-nor: everspin: unify function names
mtd: spi-nor: fujitsu: unify function names
mtd: spi-nor: gigadevice: unify function names
mtd: spi-nor: intel: unify function names
mtd: spi-nor: issi: unify function names
mtd: spi-nor: macronix: unify function names
mtd: spi-nor: micron-st: unify function names
mtd: spi-nor: spansion: unify function names
mtd: spi-nor: sst: unify function names
mtd: spi-nor: winbond: unify function names
mtd: spi-nor: xilinx: unify function names
mtd: spi-nor: xmc: unify function names
mtd: spi-nor: slightly refactor the spi_nor_setup()
mtd: spi-nor: allow a flash to define its own ready() function
mtd: spi-nor: export more function to be used in vendor modules
mtd: spi-nor: guard _page_size parameter in S3AN_INFO()
mtd: spi-nor: move all xilinx specifics into xilinx.c
mtd: spi-nor: xilinx: rename vendor specific functions and defines
mtd: spi-nor: xilinx: correct the debug message
mtd: spi-nor: move all micron-st specifics into micron-st.c
mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag
mtd: spi-nor: micron-st: rename vendor specific functions and defines
mtd: spi-nor: spansion: slightly rework control flow in late_init()
mtd: spi-nor: move all spansion specifics into spansion.c
mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag
mtd: spi-nor: spansion: rename vendor specific functions and defines
mtd: spi-nor: slightly change code style in spi_nor_sr_ready()
mtd: spi-nor: renumber flags

drivers/mtd/spi-nor/atmel.c | 81 +++++-----
drivers/mtd/spi-nor/catalyst.c | 6 +-
drivers/mtd/spi-nor/core.c | 265 ++-----------------------------
drivers/mtd/spi-nor/core.h | 70 ++++----
drivers/mtd/spi-nor/eon.c | 6 +-
drivers/mtd/spi-nor/esmt.c | 6 +-
drivers/mtd/spi-nor/everspin.c | 6 +-
drivers/mtd/spi-nor/fujitsu.c | 6 +-
drivers/mtd/spi-nor/gigadevice.c | 6 +-
drivers/mtd/spi-nor/intel.c | 6 +-
drivers/mtd/spi-nor/issi.c | 10 +-
drivers/mtd/spi-nor/macronix.c | 14 +-
drivers/mtd/spi-nor/micron-st.c | 258 ++++++++++++++++++++++++------
drivers/mtd/spi-nor/spansion.c | 164 ++++++++++++++-----
drivers/mtd/spi-nor/sst.c | 44 ++---
drivers/mtd/spi-nor/winbond.c | 29 ++--
drivers/mtd/spi-nor/xilinx.c | 97 +++++++++--
drivers/mtd/spi-nor/xmc.c | 6 +-
include/linux/mtd/spi-nor.h | 18 ---
19 files changed, 576 insertions(+), 522 deletions(-)

--
2.30.2

2022-02-21 10:14:41

by Michael Walle

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Subject: [PATCH v3 04/32] mtd: spi-nor: esmt: unify function names

2022-02-21 10:16:39

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 01/32] mtd: spi-nor: atmel: unify function names

To avoid name clashes unify all the function and static object names and
use one of the following prefixes which should be sufficiently unique:
- <vendor>_nor_
- <flash_family>_nor_
- <flash_part>_

There are no functional changes.

Signed-off-by: Michael Walle <[email protected]>
---
drivers/mtd/spi-nor/atmel.c | 81 +++++++++++++++++++------------------
1 file changed, 42 insertions(+), 39 deletions(-)

diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
index d6d889ce8876..656dd80a0be7 100644
--- a/drivers/mtd/spi-nor/atmel.c
+++ b/drivers/mtd/spi-nor/atmel.c
@@ -16,12 +16,12 @@
* is to unlock the whole flash array on startup. Therefore, we have to support
* exactly this operation.
*/
-static int atmel_at25fs_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
+static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
return -EOPNOTSUPP;
}

-static int atmel_at25fs_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
+static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
int ret;

@@ -37,28 +37,28 @@ static int atmel_at25fs_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
return ret;
}

-static int atmel_at25fs_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
+static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
return -EOPNOTSUPP;
}

-static const struct spi_nor_locking_ops atmel_at25fs_locking_ops = {
- .lock = atmel_at25fs_lock,
- .unlock = atmel_at25fs_unlock,
- .is_locked = atmel_at25fs_is_locked,
+static const struct spi_nor_locking_ops at25fs_nor_locking_ops = {
+ .lock = at25fs_nor_lock,
+ .unlock = at25fs_nor_unlock,
+ .is_locked = at25fs_nor_is_locked,
};

-static void atmel_at25fs_late_init(struct spi_nor *nor)
+static void at25fs_nor_late_init(struct spi_nor *nor)
{
- nor->params->locking_ops = &atmel_at25fs_locking_ops;
+ nor->params->locking_ops = &at25fs_nor_locking_ops;
}

-static const struct spi_nor_fixups atmel_at25fs_fixups = {
- .late_init = atmel_at25fs_late_init,
+static const struct spi_nor_fixups at25fs_nor_fixups = {
+ .late_init = at25fs_nor_late_init,
};

/**
- * atmel_set_global_protection - Do a Global Protect or Unprotect command
+ * atmel_nor_set_global_protection - Do a Global Protect or Unprotect command
* @nor: pointer to 'struct spi_nor'
* @ofs: offset in bytes
* @len: len in bytes
@@ -66,8 +66,8 @@ static const struct spi_nor_fixups atmel_at25fs_fixups = {
*
* Return: 0 on success, -error otherwise.
*/
-static int atmel_set_global_protection(struct spi_nor *nor, loff_t ofs,
- uint64_t len, bool is_protect)
+static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
+ uint64_t len, bool is_protect)
{
int ret;
u8 sr;
@@ -116,17 +116,20 @@ static int atmel_set_global_protection(struct spi_nor *nor, loff_t ofs,
return spi_nor_write_sr(nor, nor->bouncebuf, 1);
}

-static int atmel_global_protect(struct spi_nor *nor, loff_t ofs, uint64_t len)
+static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs,
+ uint64_t len)
{
- return atmel_set_global_protection(nor, ofs, len, true);
+ return atmel_nor_set_global_protection(nor, ofs, len, true);
}

-static int atmel_global_unprotect(struct spi_nor *nor, loff_t ofs, uint64_t len)
+static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs,
+ uint64_t len)
{
- return atmel_set_global_protection(nor, ofs, len, false);
+ return atmel_nor_set_global_protection(nor, ofs, len, false);
}

-static int atmel_is_global_protected(struct spi_nor *nor, loff_t ofs, uint64_t len)
+static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,
+ uint64_t len)
{
int ret;

@@ -140,47 +143,47 @@ static int atmel_is_global_protected(struct spi_nor *nor, loff_t ofs, uint64_t l
return ((nor->bouncebuf[0] & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
}

-static const struct spi_nor_locking_ops atmel_global_protection_ops = {
- .lock = atmel_global_protect,
- .unlock = atmel_global_unprotect,
- .is_locked = atmel_is_global_protected,
+static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
+ .lock = atmel_nor_global_protect,
+ .unlock = atmel_nor_global_unprotect,
+ .is_locked = atmel_nor_is_global_protected,
};

-static void atmel_global_protection_late_init(struct spi_nor *nor)
+static void atmel_nor_global_protection_late_init(struct spi_nor *nor)
{
- nor->params->locking_ops = &atmel_global_protection_ops;
+ nor->params->locking_ops = &atmel_nor_global_protection_ops;
}

-static const struct spi_nor_fixups atmel_global_protection_fixups = {
- .late_init = atmel_global_protection_late_init,
+static const struct spi_nor_fixups atmel_nor_global_protection_fixups = {
+ .late_init = atmel_nor_global_protection_late_init,
};

-static const struct flash_info atmel_parts[] = {
+static const struct flash_info atmel_nor_parts[] = {
/* Atmel -- some are (confusingly) marketed as "DataFlash" */
{ "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4)
FLAGS(SPI_NOR_HAS_LOCK)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_at25fs_fixups },
+ .fixups = &at25fs_nor_fixups },
{ "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8)
FLAGS(SPI_NOR_HAS_LOCK)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_at25fs_fixups },
+ .fixups = &at25fs_nor_fixups },
{ "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_global_protection_fixups },
+ .fixups = &atmel_nor_global_protection_fixups },
{ "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_global_protection_fixups },
+ .fixups = &atmel_nor_global_protection_fixups },
{ "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_global_protection_fixups },
+ .fixups = &atmel_nor_global_protection_fixups },
{ "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_global_protection_fixups },
+ .fixups = &atmel_nor_global_protection_fixups },
{ "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8)
@@ -188,21 +191,21 @@ static const struct flash_info atmel_parts[] = {
{ "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_global_protection_fixups },
+ .fixups = &atmel_nor_global_protection_fixups },
{ "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_global_protection_fixups },
+ .fixups = &atmel_nor_global_protection_fixups },
{ "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
NO_SFDP_FLAGS(SECT_4K)
- .fixups = &atmel_global_protection_fixups },
+ .fixups = &atmel_nor_global_protection_fixups },
{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16)
NO_SFDP_FLAGS(SECT_4K) },
};

const struct spi_nor_manufacturer spi_nor_atmel = {
.name = "atmel",
- .parts = atmel_parts,
- .nparts = ARRAY_SIZE(atmel_parts),
+ .parts = atmel_nor_parts,
+ .nparts = ARRAY_SIZE(atmel_nor_parts),
};
--
2.30.2

2022-02-21 10:17:04

by Michael Walle

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Subject: [PATCH v3 05/32] mtd: spi-nor: everspin: unify function names

2022-02-21 10:17:41

by Michael Walle

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Subject: [PATCH v3 07/32] mtd: spi-nor: gigadevice: unify function names

2022-02-21 10:17:56

by Michael Walle

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Subject: [PATCH v3 08/32] mtd: spi-nor: intel: unify function names

2022-02-21 10:18:42

by Michael Walle

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Subject: [PATCH v3 06/32] mtd: spi-nor: fujitsu: unify function names

2022-02-21 10:18:56

by Michael Walle

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Subject: [PATCH v3 10/32] mtd: spi-nor: macronix: unify function names

2022-02-21 10:19:10

by Michael Walle

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Subject: [PATCH v3 12/32] mtd: spi-nor: spansion: unify function names

2022-02-21 10:30:34

by Michael Walle

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Subject: [PATCH v3 26/32] mtd: spi-nor: micron-st: rename vendor specific functions and defines

Drop the generic spi_nor prefix for all the micron-st functions.

Signed-off-by: Michael Walle <[email protected]>
---
drivers/mtd/spi-nor/micron-st.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index f693f8720541..de450495e1ab 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -309,7 +309,7 @@ static int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
}

/**
- * spi_nor_read_fsr() - Read the Flag Status Register.
+ * micron_st_nor_read_fsr() - Read the Flag Status Register.
* @nor: pointer to 'struct spi_nor'
* @fsr: pointer to a DMA-able buffer where the value of the
* Flag Status Register will be written. Should be at least 2
@@ -317,7 +317,7 @@ static int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
*
* Return: 0 on success, -errno otherwise.
*/
-static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
+static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
{
int ret;

@@ -353,10 +353,10 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
}

/**
- * spi_nor_clear_fsr() - Clear the Flag Status Register.
+ * micron_st_nor_clear_fsr() - Clear the Flag Status Register.
* @nor: pointer to 'struct spi_nor'.
*/
-static void spi_nor_clear_fsr(struct spi_nor *nor)
+static void micron_st_nor_clear_fsr(struct spi_nor *nor)
{
int ret;

@@ -380,13 +380,13 @@ static void spi_nor_clear_fsr(struct spi_nor *nor)
}

/**
- * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
- * ready for new commands.
+ * micron_st_nor_fsr_ready() - Query the Flag Status Register to see if the
+ * flash is ready for new commands.
* @nor: pointer to 'struct spi_nor'.
*
* Return: 1 if ready, 0 if not ready, -errno on errors.
*/
-static int spi_nor_fsr_ready(struct spi_nor *nor)
+static int micron_st_nor_fsr_ready(struct spi_nor *nor)
{
int sr_ready, ret;

@@ -394,7 +394,7 @@ static int spi_nor_fsr_ready(struct spi_nor *nor)
if (sr_ready < 0)
return sr_ready;

- ret = spi_nor_read_fsr(nor, nor->bouncebuf);
+ ret = micron_st_nor_read_fsr(nor, nor->bouncebuf);
if (ret)
return ret;

@@ -408,7 +408,7 @@ static int spi_nor_fsr_ready(struct spi_nor *nor)
dev_err(nor->dev,
"Attempted to modify a protected sector.\n");

- spi_nor_clear_fsr(nor);
+ micron_st_nor_clear_fsr(nor);

/*
* WEL bit remains set to one when an erase or page program
@@ -437,7 +437,7 @@ static void micron_st_nor_default_init(struct spi_nor *nor)
static void micron_st_nor_late_init(struct spi_nor *nor)
{
if (nor->info->mfr_flags & USE_FSR)
- nor->params->ready = spi_nor_fsr_ready;
+ nor->params->ready = micron_st_nor_fsr_ready;
}

static const struct spi_nor_fixups micron_st_nor_fixups = {
--
2.30.2

2022-02-21 10:37:09

by Michael Walle

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Subject: [PATCH v3 16/32] mtd: spi-nor: xmc: unify function names

2022-02-21 10:42:54

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 20/32] mtd: spi-nor: guard _page_size parameter in S3AN_INFO()

The _page_size marco parameter was missing parentheses around it. Add
them.

Signed-off-by: Michael Walle <[email protected]>
---
drivers/mtd/spi-nor/core.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 446218b0e017..3c37b46d60d5 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -469,9 +469,9 @@ struct flash_info {
(_jedec_id) & 0xff \
}, \
.id_len = 3, \
- .sector_size = (8*_page_size), \
+ .sector_size = (8 * (_page_size)), \
.n_sectors = (_n_sectors), \
- .page_size = _page_size, \
+ .page_size = (_page_size), \
.addr_width = 3, \
.flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,

--
2.30.2

2022-02-21 10:43:02

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 19/32] mtd: spi-nor: export more function to be used in vendor modules

We will move vendor specific code into the vendor modules and thus we
will have to export these functions so they can be called.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/core.c | 10 +++++-----
drivers/mtd/spi-nor/core.h | 6 ++++++
2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 390a9ab413b7..8481272533a3 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -157,8 +157,8 @@ static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
return spi_mem_exec_op(nor->spimem, op);
}

-static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
- u8 *buf, size_t len)
+int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
+ u8 *buf, size_t len)
{
if (spi_nor_protocol_is_dtr(nor->reg_proto))
return -EOPNOTSUPP;
@@ -166,8 +166,8 @@ static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
return nor->controller_ops->read_reg(nor, opcode, buf, len);
}

-static int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
- const u8 *buf, size_t len)
+int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
+ const u8 *buf, size_t len)
{
if (spi_nor_protocol_is_dtr(nor->reg_proto))
return -EOPNOTSUPP;
@@ -683,7 +683,7 @@ static void spi_nor_clear_sr(struct spi_nor *nor)
*
* Return: 1 if ready, 0 if not ready, -errno on errors.
*/
-static int spi_nor_sr_ready(struct spi_nor *nor)
+int spi_nor_sr_ready(struct spi_nor *nor)
{
int ret = spi_nor_read_sr(nor, nor->bouncebuf);

diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index fdc8c0f31f5c..446218b0e017 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -558,6 +558,7 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
+int spi_nor_sr_ready(struct spi_nor *nor);
int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
@@ -603,6 +604,11 @@ void spi_nor_try_unlock_all(struct spi_nor *nor);
void spi_nor_set_mtd_locking_ops(struct spi_nor *nor);
void spi_nor_set_mtd_otp_ops(struct spi_nor *nor);

+int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
+ u8 *buf, size_t len);
+int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
+ const u8 *buf, size_t len);
+
static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
{
return container_of(mtd, struct spi_nor, mtd);
--
2.30.2

2022-02-21 11:20:07

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 27/32] mtd: spi-nor: spansion: slightly rework control flow in late_init()

Don't return early when the flash is smaller than or equal to 16MiB. We
need to be able to register hooks for all sizes of flashes. This also has
the benefit that it increases the readability of the code because the
action, i.e. registering the fixups, is connected to the condition, i.e.
flashes larger than 16MiB.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/spansion.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index dea021a8c9e4..22dedd199531 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -296,13 +296,12 @@ static const struct flash_info spansion_nor_parts[] = {

static void spansion_nor_late_init(struct spi_nor *nor)
{
- if (nor->params->size <= SZ_16M)
- return;
-
- nor->flags |= SNOR_F_4B_OPCODES;
- /* No small sector erase for 4-byte command set */
- nor->erase_opcode = SPINOR_OP_SE;
- nor->mtd.erasesize = nor->info->sector_size;
+ if (nor->params->size > SZ_16M) {
+ nor->flags |= SNOR_F_4B_OPCODES;
+ /* No small sector erase for 4-byte command set */
+ nor->erase_opcode = SPINOR_OP_SE;
+ nor->mtd.erasesize = nor->info->sector_size;
+ }
}

static const struct spi_nor_fixups spansion_nor_fixups = {
--
2.30.2

2022-02-21 11:53:28

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 13/32] mtd: spi-nor: sst: unify function names

2022-02-21 12:09:51

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 14/32] mtd: spi-nor: winbond: unify function names

2022-02-21 13:45:41

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 32/32] mtd: spi-nor: renumber flags

As we have deleted some flag, lets renumber them so there are no holes.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/core.h | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 2130a96e2044..b7fd760e3b47 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -12,20 +12,20 @@
#define SPI_NOR_MAX_ID_LEN 6

enum spi_nor_option_flags {
- SNOR_F_HAS_SR_TB = BIT(1),
- SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
- SNOR_F_BROKEN_RESET = BIT(5),
- SNOR_F_4B_OPCODES = BIT(6),
- SNOR_F_HAS_4BAIT = BIT(7),
- SNOR_F_HAS_LOCK = BIT(8),
- SNOR_F_HAS_16BIT_SR = BIT(9),
- SNOR_F_NO_READ_CR = BIT(10),
- SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
- SNOR_F_HAS_4BIT_BP = BIT(12),
- SNOR_F_HAS_SR_BP3_BIT6 = BIT(13),
- SNOR_F_IO_MODE_EN_VOLATILE = BIT(14),
- SNOR_F_SOFT_RESET = BIT(15),
- SNOR_F_SWP_IS_VOLATILE = BIT(16),
+ SNOR_F_HAS_SR_TB = BIT(0),
+ SNOR_F_NO_OP_CHIP_ERASE = BIT(1),
+ SNOR_F_BROKEN_RESET = BIT(2),
+ SNOR_F_4B_OPCODES = BIT(3),
+ SNOR_F_HAS_4BAIT = BIT(4),
+ SNOR_F_HAS_LOCK = BIT(5),
+ SNOR_F_HAS_16BIT_SR = BIT(6),
+ SNOR_F_NO_READ_CR = BIT(7),
+ SNOR_F_HAS_SR_TB_BIT6 = BIT(8),
+ SNOR_F_HAS_4BIT_BP = BIT(9),
+ SNOR_F_HAS_SR_BP3_BIT6 = BIT(10),
+ SNOR_F_IO_MODE_EN_VOLATILE = BIT(11),
+ SNOR_F_SOFT_RESET = BIT(12),
+ SNOR_F_SWP_IS_VOLATILE = BIT(13),
};

struct spi_nor_read_command {
--
2.30.2

2022-02-21 15:45:23

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH v3 12/32] mtd: spi-nor: spansion: unify function names

Hi Michael,

I love your patch! Yet something to improve:

[auto build test ERROR on mtd/spi-nor/next]
[also build test ERROR on tip/master linux/master linus/master v5.17-rc5 next-20220217]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Michael-Walle/mtd-spi-nor-move-vendor-specific-code-into-vendor-modules/20220221-165728
base: https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-nor/next
config: x86_64-randconfig-a003-20220221 (https://download.01.org/0day-ci/archive/20220221/[email protected]/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/f8aeae6008aa9a304aacb1914911dcb3a895da53
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Michael-Walle/mtd-spi-nor-move-vendor-specific-code-into-vendor-modules/20220221-165728
git checkout f8aeae6008aa9a304aacb1914911dcb3a895da53
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/mtd/spi-nor/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>

All errors (new ones prefixed by >>):

>> drivers/mtd/spi-nor/spansion.c:232:14: error: 's25fs_s_fixups' undeclared here (not in a function); did you mean 's25fs_s_nor_fixups'?
232 | .fixups = &s25fs_s_fixups, },
| ^~~~~~~~~~~~~~
| s25fs_s_nor_fixups
drivers/mtd/spi-nor/spansion.c:201:36: warning: 's25fs_s_nor_fixups' defined but not used [-Wunused-const-variable=]
201 | static const struct spi_nor_fixups s25fs_s_nor_fixups = {
| ^~~~~~~~~~~~~~~~~~

vim +232 drivers/mtd/spi-nor/spansion.c

5587fa489747a8 Sergei Shtylyov 2020-04-20 204
f8aeae6008aa9a Michael Walle 2022-02-21 205 static const struct flash_info spansion_nor_parts[] = {
0173c32a0ebd42 Boris Brezillon 2020-03-13 206 /* Spansion/Cypress -- single (large) sector size only, at least
0173c32a0ebd42 Boris Brezillon 2020-03-13 207 * for the chips listed here (without boot sectors).
0173c32a0ebd42 Boris Brezillon 2020-03-13 208 */
ec1c0e996035c8 Tudor Ambarus 2021-12-07 209 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 210 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 211 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 212 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 213 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 214 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 215 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 216 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 217 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 218 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 219 { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 220 FLAGS(USE_CLSR)
5eefc2dc03192c Tudor Ambarus 2021-12-07 221 NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ |
5eefc2dc03192c Tudor Ambarus 2021-12-07 222 SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 223 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 224 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 225 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 226 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 227 FLAGS(SPI_NOR_HAS_LOCK | USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 228 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 229 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 230 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 231 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
c26d0d87f175b8 Yicong Yang 2020-04-22 @232 .fixups = &s25fs_s_fixups, },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 233 { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 234 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 235 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 236 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 237 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 238 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 239 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 240 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 241 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
5587fa489747a8 Sergei Shtylyov 2020-04-20 242 .fixups = &s25fs_s_fixups, },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 243 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 244 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 245 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 246 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 247 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 248 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 249 FLAGS(USE_CLSR)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 250 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 251 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 252 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 253 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 254 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 255 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 256 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 257 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
ec1c0e996035c8 Tudor Ambarus 2021-12-07 258 SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 259 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 260 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
ec1c0e996035c8 Tudor Ambarus 2021-12-07 261 SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 262 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 263 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
ec1c0e996035c8 Tudor Ambarus 2021-12-07 264 SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 265 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 266 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
ec1c0e996035c8 Tudor Ambarus 2021-12-07 267 SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 268 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 269 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
ec1c0e996035c8 Tudor Ambarus 2021-12-07 270 SPI_NOR_QUAD_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 271 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 272 NO_SFDP_FLAGS(SECT_4K) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 273 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 274 NO_SFDP_FLAGS(SECT_4K) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 275 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 276 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 277 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 278 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 279 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 280 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 281 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 282 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 283 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 284 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 285 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 286 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 287 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 288 { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 289 FLAGS(SPI_NOR_NO_ERASE) },
ec1c0e996035c8 Tudor Ambarus 2021-12-07 290 { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256)
ec1c0e996035c8 Tudor Ambarus 2021-12-07 291 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
c3266af101f28e Pratyush Yadav 2020-10-05 292 SPI_NOR_OCTAL_DTR_PP)
c3266af101f28e Pratyush Yadav 2020-10-05 293 .fixups = &s28hs512t_fixups,
c3266af101f28e Pratyush Yadav 2020-10-05 294 },
0173c32a0ebd42 Boris Brezillon 2020-03-13 295 };
0173c32a0ebd42 Boris Brezillon 2020-03-13 296

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]

2022-02-21 15:49:50

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 23/32] mtd: spi-nor: xilinx: correct the debug message

XRDSR is a combination of xilinx and the RDSR opcode, but the register
is just the status register. Correct the debug message.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/xilinx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c
index ffd5579d45cb..9459ac2609dc 100644
--- a/drivers/mtd/spi-nor/xilinx.c
+++ b/drivers/mtd/spi-nor/xilinx.c
@@ -87,7 +87,7 @@ static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr)
}

if (ret)
- dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
+ dev_dbg(nor->dev, "error %d reading SR\n", ret);

return ret;
}
--
2.30.2

2022-02-21 15:58:12

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 28/32] mtd: spi-nor: move all spansion specifics into spansion.c

The clear status register flags is only available on spansion flashes.
Move all the functions around that into the spanion module.

Signed-off-by: Michael Walle <[email protected]>
---
drivers/mtd/spi-nor/core.c | 49 ------------------------
drivers/mtd/spi-nor/spansion.c | 70 ++++++++++++++++++++++++++++++++++
include/linux/mtd/spi-nor.h | 1 -
3 files changed, 70 insertions(+), 50 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index ac0faedebafe..e2b8b0a438ce 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -554,33 +554,6 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
return ret;
}

-/**
- * spi_nor_clear_sr() - Clear the Status Register.
- * @nor: pointer to 'struct spi_nor'.
- */
-static void spi_nor_clear_sr(struct spi_nor *nor)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
- NULL, 0);
- }
-
- if (ret)
- dev_dbg(nor->dev, "error %d clearing SR\n", ret);
-}
-
/**
* spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
* for new commands.
@@ -595,28 +568,6 @@ int spi_nor_sr_ready(struct spi_nor *nor)
if (ret)
return ret;

- if (nor->flags & SNOR_F_USE_CLSR &&
- nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
- if (nor->bouncebuf[0] & SR_E_ERR)
- dev_err(nor->dev, "Erase Error occurred\n");
- else
- dev_err(nor->dev, "Programming Error occurred\n");
-
- spi_nor_clear_sr(nor);
-
- /*
- * WEL bit remains set to one when an erase or page program
- * error occurs. Issue a Write Disable command to protect
- * against inadvertent writes that can possibly corrupt the
- * contents of the memory.
- */
- ret = spi_nor_write_disable(nor);
- if (ret)
- return ret;
-
- return -EIO;
- }
-
return !(nor->bouncebuf[0] & SR_WIP);
}

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 22dedd199531..88ecf117016f 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -8,6 +8,7 @@

#include "core.h"

+#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
#define SPINOR_REG_CYPRESS_CFR2V 0x00800003
@@ -294,6 +295,72 @@ static const struct flash_info spansion_nor_parts[] = {
},
};

+/**
+ * spi_nor_clear_sr() - Clear the Status Register.
+ * @nor: pointer to 'struct spi_nor'.
+ */
+static void spi_nor_clear_sr(struct spi_nor *nor)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
+ NULL, 0);
+ }
+
+ if (ret)
+ dev_dbg(nor->dev, "error %d clearing SR\n", ret);
+}
+
+/**
+ * spi_nor_sr_ready_and_clear() - Query the Status Register to see if the flash
+ * is ready for new commands and clear it.
+ * @nor: pointer to 'struct spi_nor'.
+ *
+ * Return: 1 if ready, 0 if not ready, -errno on errors.
+ */
+static int spi_nor_sr_ready_and_clear(struct spi_nor *nor)
+{
+ int ret;
+
+ ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ if (ret)
+ return ret;
+
+ if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
+ if (nor->bouncebuf[0] & SR_E_ERR)
+ dev_err(nor->dev, "Erase Error occurred\n");
+ else
+ dev_err(nor->dev, "Programming Error occurred\n");
+
+ spi_nor_clear_sr(nor);
+
+ /*
+ * WEL bit remains set to one when an erase or page program
+ * error occurs. Issue a Write Disable command to protect
+ * against inadvertent writes that can possibly corrupt the
+ * contents of the memory.
+ */
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ return ret;
+
+ return -EIO;
+ }
+
+ return !(nor->bouncebuf[0] & SR_WIP);
+}
+
static void spansion_nor_late_init(struct spi_nor *nor)
{
if (nor->params->size > SZ_16M) {
@@ -302,6 +369,9 @@ static void spansion_nor_late_init(struct spi_nor *nor)
nor->erase_opcode = SPINOR_OP_SE;
nor->mtd.erasesize = nor->info->sector_size;
}
+
+ if (nor->flags & SNOR_F_USE_CLSR)
+ nor->params->ready = spi_nor_sr_ready_and_clear;
}

static const struct spi_nor_fixups spansion_nor_fixups = {
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4622251a79ff..5e25a7b75ae2 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -90,7 +90,6 @@

/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
-#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */

/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
--
2.30.2

2022-02-21 16:24:08

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 31/32] mtd: spi-nor: slightly change code style in spi_nor_sr_ready()

Now that there is almost no special case code left in
spi_nor_sr_ready(), the return check looks odd. Move the function call
closer to the return code checking.

Signed-off-by: Michael Walle <[email protected]>
---
drivers/mtd/spi-nor/core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index f5a2f37d140e..9014008e60b3 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -563,8 +563,9 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
*/
int spi_nor_sr_ready(struct spi_nor *nor)
{
- int ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ int ret;

+ ret = spi_nor_read_sr(nor, nor->bouncebuf);
if (ret)
return ret;

--
2.30.2

2022-02-21 16:49:43

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 22/32] mtd: spi-nor: xilinx: rename vendor specific functions and defines

Drop the generic spi_nor prefix for all the xilinx functions.

Signed-off-by: Michael Walle <[email protected]>
---
drivers/mtd/spi-nor/xilinx.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c
index 05c7fe843a7d..ffd5579d45cb 100644
--- a/drivers/mtd/spi-nor/xilinx.c
+++ b/drivers/mtd/spi-nor/xilinx.c
@@ -8,9 +8,9 @@

#include "core.h"

-#define SPINOR_OP_XSE 0x50 /* Sector erase */
-#define SPINOR_OP_XPP 0x82 /* Page program */
-#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
+#define XILINX_OP_SE 0x50 /* Sector erase */
+#define XILINX_OP_PP 0x82 /* Page program */
+#define XILINX_OP_RDSR 0xd7 /* Read status register */

#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
#define XSR_RDY BIT(7) /* Ready */
@@ -60,20 +60,20 @@ static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
}

/**
- * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
+ * xilinx_nor_read_sr() - Read the Status Register on S3AN flashes.
* @nor: pointer to 'struct spi_nor'.
* @sr: pointer to a DMA-able buffer where the value of the
* Status Register will be written.
*
* Return: 0 on success, -errno otherwise.
*/
-static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
+static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr)
{
int ret;

if (nor->spimem) {
struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0),
+ SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_IN(1, sr, 0));
@@ -82,7 +82,7 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)

ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr,
+ ret = spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr,
1);
}

@@ -93,17 +93,17 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
}

/**
- * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
- * the flash is ready for new commands.
+ * xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to see
+ * if the flash is ready for new commands.
* @nor: pointer to 'struct spi_nor'.
*
* Return: 1 if ready, 0 if not ready, -errno on errors.
*/
-static int spi_nor_xsr_ready(struct spi_nor *nor)
+static int xilinx_nor_sr_ready(struct spi_nor *nor)
{
int ret;

- ret = spi_nor_xread_sr(nor, nor->bouncebuf);
+ ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
if (ret)
return ret;

@@ -116,12 +116,12 @@ static int xilinx_nor_setup(struct spi_nor *nor,
u32 page_size;
int ret;

- ret = spi_nor_xread_sr(nor, nor->bouncebuf);
+ ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
if (ret)
return ret;

- nor->erase_opcode = SPINOR_OP_XSE;
- nor->program_opcode = SPINOR_OP_XPP;
+ nor->erase_opcode = XILINX_OP_SE;
+ nor->program_opcode = XILINX_OP_PP;
nor->read_opcode = SPINOR_OP_READ;
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;

@@ -155,7 +155,7 @@ static int xilinx_nor_setup(struct spi_nor *nor,
static void xilinx_nor_late_init(struct spi_nor *nor)
{
nor->params->setup = xilinx_nor_setup;
- nor->params->ready = spi_nor_xsr_ready;
+ nor->params->ready = xilinx_nor_sr_ready;
}

static const struct spi_nor_fixups xilinx_nor_fixups = {
--
2.30.2

2022-02-21 18:51:49

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 21/32] mtd: spi-nor: move all xilinx specifics into xilinx.c

Mechanically move all the xilinx functions to its own module.

Then register the new flash specific ready() function.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/core.c | 64 +------------------------------
drivers/mtd/spi-nor/core.h | 18 ---------
drivers/mtd/spi-nor/xilinx.c | 73 ++++++++++++++++++++++++++++++++++++
include/linux/mtd/spi-nor.h | 9 -----
4 files changed, 74 insertions(+), 90 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 8481272533a3..ae1560250c48 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -598,57 +598,6 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
return ret;
}

-/**
- * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
- * @nor: pointer to 'struct spi_nor'.
- * @sr: pointer to a DMA-able buffer where the value of the
- * Status Register will be written.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, sr, 0));
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr,
- 1);
- }
-
- if (ret)
- dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
-
- return ret;
-}
-
-/**
- * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
- * the flash is ready for new commands.
- * @nor: pointer to 'struct spi_nor'.
- *
- * Return: 1 if ready, 0 if not ready, -errno on errors.
- */
-static int spi_nor_xsr_ready(struct spi_nor *nor)
-{
- int ret;
-
- ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- return !!(nor->bouncebuf[0] & XSR_RDY);
-}
-
/**
* spi_nor_clear_sr() - Clear the Status Register.
* @nor: pointer to 'struct spi_nor'.
@@ -798,10 +747,7 @@ static int spi_nor_ready(struct spi_nor *nor)
if (nor->params->ready)
return nor->params->ready(nor);

- if (nor->flags & SNOR_F_READY_XSR_RDY)
- sr = spi_nor_xsr_ready(nor);
- else
- sr = spi_nor_sr_ready(nor);
+ sr = spi_nor_sr_ready(nor);
if (sr < 0)
return sr;
fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
@@ -2677,14 +2623,6 @@ static void spi_nor_init_flags(struct spi_nor *nor)

if (flags & USE_FSR)
nor->flags |= SNOR_F_USE_FSR;
-
- /*
- * Make sure the XSR_RDY flag is set before calling
- * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
- * with Atmel SPI NOR.
- */
- if (flags & SPI_NOR_XSR_RDY)
- nor->flags |= SNOR_F_READY_XSR_RDY;
}

/**
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 3c37b46d60d5..fabc01ae9a81 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -15,7 +15,6 @@ enum spi_nor_option_flags {
SNOR_F_USE_FSR = BIT(0),
SNOR_F_HAS_SR_TB = BIT(1),
SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
- SNOR_F_READY_XSR_RDY = BIT(3),
SNOR_F_USE_CLSR = BIT(4),
SNOR_F_BROKEN_RESET = BIT(5),
SNOR_F_4B_OPCODES = BIT(6),
@@ -351,8 +350,6 @@ struct spi_nor_fixups {
* SPI_NOR_NO_FR: can't do fastread.
* USE_CLSR: use CLSR command.
* USE_FSR: use flag status register
- * SPI_NOR_XSR_RDY: S3AN flashes have specific opcode to read the
- * status register.
*
* @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
* Used when SFDP tables are not defined in the flash. These
@@ -405,7 +402,6 @@ struct flash_info {
#define SPI_NOR_NO_FR BIT(8)
#define USE_CLSR BIT(9)
#define USE_FSR BIT(10)
-#define SPI_NOR_XSR_RDY BIT(11)

u8 no_sfdp_flags;
#define SPI_NOR_SKIP_SFDP BIT(0)
@@ -462,19 +458,6 @@ struct flash_info {
.addr_width = (_addr_width), \
.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, \

-#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
- .id = { \
- ((_jedec_id) >> 16) & 0xff, \
- ((_jedec_id) >> 8) & 0xff, \
- (_jedec_id) & 0xff \
- }, \
- .id_len = 3, \
- .sector_size = (8 * (_page_size)), \
- .n_sectors = (_n_sectors), \
- .page_size = (_page_size), \
- .addr_width = 3, \
- .flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,
-
#define OTP_INFO(_len, _n_regions, _base, _offset) \
.otp_org = { \
.len = (_len), \
@@ -564,7 +547,6 @@ int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);

-int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
u8 *buf);
ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c
index 07dd11788df5..05c7fe843a7d 100644
--- a/drivers/mtd/spi-nor/xilinx.c
+++ b/drivers/mtd/spi-nor/xilinx.c
@@ -8,6 +8,27 @@

#include "core.h"

+#define SPINOR_OP_XSE 0x50 /* Sector erase */
+#define SPINOR_OP_XPP 0x82 /* Page program */
+#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
+
+#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
+#define XSR_RDY BIT(7) /* Ready */
+
+#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
+ .id = { \
+ ((_jedec_id) >> 16) & 0xff, \
+ ((_jedec_id) >> 8) & 0xff, \
+ (_jedec_id) & 0xff \
+ }, \
+ .id_len = 3, \
+ .sector_size = (8 * (_page_size)), \
+ .n_sectors = (_n_sectors), \
+ .page_size = (_page_size), \
+ .addr_width = 3, \
+ .flags = SPI_NOR_NO_FR
+
+/* Xilinx S3AN share MFR with Atmel SPI NOR */
static const struct flash_info xilinx_nor_parts[] = {
/* Xilinx S3AN Internal Flash */
{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
@@ -38,6 +59,57 @@ static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
return page | offset;
}

+/**
+ * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
+ * @nor: pointer to 'struct spi_nor'.
+ * @sr: pointer to a DMA-able buffer where the value of the
+ * Status Register will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(1, sr, 0));
+
+ spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr,
+ 1);
+ }
+
+ if (ret)
+ dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
+
+ return ret;
+}
+
+/**
+ * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
+ * the flash is ready for new commands.
+ * @nor: pointer to 'struct spi_nor'.
+ *
+ * Return: 1 if ready, 0 if not ready, -errno on errors.
+ */
+static int spi_nor_xsr_ready(struct spi_nor *nor)
+{
+ int ret;
+
+ ret = spi_nor_xread_sr(nor, nor->bouncebuf);
+ if (ret)
+ return ret;
+
+ return !!(nor->bouncebuf[0] & XSR_RDY);
+}
+
static int xilinx_nor_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
@@ -83,6 +155,7 @@ static int xilinx_nor_setup(struct spi_nor *nor,
static void xilinx_nor_late_init(struct spi_nor *nor)
{
nor->params->setup = xilinx_nor_setup;
+ nor->params->ready = spi_nor_xsr_ready;
}

static const struct spi_nor_fixups xilinx_nor_fixups = {
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fc90fce26e33..b44b05a6f934 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -86,15 +86,6 @@
#define SPINOR_OP_BP 0x02 /* Byte program */
#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */

-/* Used for S3AN flashes only */
-#define SPINOR_OP_XSE 0x50 /* Sector erase */
-#define SPINOR_OP_XPP 0x82 /* Page program */
-#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
-
-#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
-#define XSR_RDY BIT(7) /* Ready */
-
-
/* Used for Macronix and Winbond flashes. */
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
--
2.30.2

2022-02-21 21:57:35

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 18/32] mtd: spi-nor: allow a flash to define its own ready() function

Xilinx and Micron flashes have their own implementation of the
spi_nor_ready() function. At the moment, the core will figure out
which one to call according to some flags. Lay the foundation to
make it possible that a flash can register its own ready()
function.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/core.c | 4 ++++
drivers/mtd/spi-nor/core.h | 4 ++++
2 files changed, 8 insertions(+)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 4d2036cdce42..390a9ab413b7 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -794,6 +794,10 @@ static int spi_nor_ready(struct spi_nor *nor)
{
int sr, fsr;

+ /* Flashes might override the standard routine. */
+ if (nor->params->ready)
+ return nor->params->ready(nor);
+
if (nor->flags & SNOR_F_READY_XSR_RDY)
sr = spi_nor_xsr_ready(nor);
else
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 4fe16b5aa3f5..fdc8c0f31f5c 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -261,6 +261,9 @@ struct spi_nor_otp {
* SPI NOR flashes that have peculiarities to the SPI NOR
* standard e.g. different opcodes, specific address
* calculation, page size, etc.
+ * @ready: (optional) flashes might use a different mechanism
+ * than reading the status register to indicate they
+ * are ready for a new command
* @locking_ops: SPI NOR locking methods.
*/
struct spi_nor_flash_parameter {
@@ -282,6 +285,7 @@ struct spi_nor_flash_parameter {
int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
+ int (*ready)(struct spi_nor *nor);

const struct spi_nor_locking_ops *locking_ops;
};
--
2.30.2

2022-02-22 03:42:26

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 11/32] mtd: spi-nor: micron-st: unify function names

2022-02-22 04:35:23

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 25/32] mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag

Now that all functions using that flag are local to the micron module,
we can convert the flag to a manufacturer one.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/core.c | 3 --
drivers/mtd/spi-nor/core.h | 3 --
drivers/mtd/spi-nor/micron-st.c | 93 +++++++++++++++++++++------------
3 files changed, 60 insertions(+), 39 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 5b56d718692b..ac0faedebafe 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2499,9 +2499,6 @@ static void spi_nor_init_flags(struct spi_nor *nor)

if (flags & USE_CLSR)
nor->flags |= SNOR_F_USE_CLSR;
-
- if (flags & USE_FSR)
- nor->flags |= SNOR_F_USE_FSR;
}

/**
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index fabc01ae9a81..a02bf54289fb 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -12,7 +12,6 @@
#define SPI_NOR_MAX_ID_LEN 6

enum spi_nor_option_flags {
- SNOR_F_USE_FSR = BIT(0),
SNOR_F_HAS_SR_TB = BIT(1),
SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
SNOR_F_USE_CLSR = BIT(4),
@@ -349,7 +348,6 @@ struct spi_nor_fixups {
* NO_CHIP_ERASE: chip does not support chip erase.
* SPI_NOR_NO_FR: can't do fastread.
* USE_CLSR: use CLSR command.
- * USE_FSR: use flag status register
*
* @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
* Used when SFDP tables are not defined in the flash. These
@@ -401,7 +399,6 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(7)
#define SPI_NOR_NO_FR BIT(8)
#define USE_CLSR BIT(9)
-#define USE_FSR BIT(10)

u8 no_sfdp_flags;
#define SPI_NOR_SKIP_SFDP BIT(0)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 8877b122cf42..f693f8720541 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -8,6 +8,9 @@

#include "core.h"

+/* flash_info mfr_flag. Used to read proprietary FSR register. */
+#define USE_FSR BIT(0)
+
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
@@ -140,15 +143,17 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = {

static const struct flash_info micron_nor_parts[] = {
{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512)
- FLAGS(USE_FSR)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ |
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP)
FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE)
- .fixups = &mt35xu512aba_fixups},
+ MFR_FLAGS(USE_FSR)
+ .fixups = &mt35xu512aba_fixups
+ },
{ "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048)
- FLAGS(USE_FSR)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
+ MFR_FLAGS(USE_FSR)
+ },
};

static const struct flash_info st_nor_parts[] = {
@@ -164,57 +169,79 @@ static const struct flash_info st_nor_parts[] = {
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6 | USE_FSR)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
+ SPI_NOR_BP3_SR_BIT6)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6 | USE_FSR)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
+ SPI_NOR_BP3_SR_BIT6)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512)
- FLAGS(USE_FSR)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
+ MFR_FLAGS(USE_FSR)
+ },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512)
- FLAGS(USE_FSR)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
+ SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
- FLAGS(USE_FSR)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
+ MFR_FLAGS(USE_FSR)
+ },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
- FLAGS(USE_FSR)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024)
- FLAGS(USE_FSR)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
+ MFR_FLAGS(USE_FSR)
+ },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6 | USE_FSR)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
+ SPI_NOR_BP3_SR_BIT6)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024)
- FLAGS(USE_FSR)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
+ MFR_FLAGS(USE_FSR)
+ },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6 | USE_FSR)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
+ SPI_NOR_BP3_SR_BIT6)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
- SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE | USE_FSR)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
+ SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048)
- FLAGS(NO_CHIP_ERASE | USE_FSR)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
+ FLAGS(NO_CHIP_ERASE)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
- FLAGS(NO_CHIP_ERASE | USE_FSR)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
+ FLAGS(NO_CHIP_ERASE)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
- FLAGS(NO_CHIP_ERASE | USE_FSR)
+ FLAGS(NO_CHIP_ERASE)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
+ SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_FSR)
+ },

{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2) },
{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4) },
@@ -409,7 +436,7 @@ static void micron_st_nor_default_init(struct spi_nor *nor)

static void micron_st_nor_late_init(struct spi_nor *nor)
{
- if (nor->flags & SNOR_F_USE_FSR)
+ if (nor->info->mfr_flags & USE_FSR)
nor->params->ready = spi_nor_fsr_ready;
}

--
2.30.2

2022-02-22 04:53:31

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 17/32] mtd: spi-nor: slightly refactor the spi_nor_setup()

Instead of always using a function pointer (and initializing it to our
default), just call the default function if the flash didn't set its own
one. That will make the call flow easier to follow.

Also mark the parameter as optional now.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/core.c | 10 +++++-----
drivers/mtd/spi-nor/core.h | 8 ++++----
2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 04ea180118e3..4d2036cdce42 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2532,11 +2532,12 @@ static int spi_nor_setup(struct spi_nor *nor,
{
int ret;

- if (nor->params->setup) {
+ if (nor->params->setup)
ret = nor->params->setup(nor, hwcaps);
- if (ret)
- return ret;
- }
+ else
+ ret = spi_nor_default_setup(nor, hwcaps);
+ if (ret)
+ return ret;

return spi_nor_set_addr_width(nor);
}
@@ -2786,7 +2787,6 @@ static void spi_nor_init_default_params(struct spi_nor *nor)

params->quad_enable = spi_nor_sr2_bit1_quad_enable;
params->set_4byte_addr_mode = spansion_set_4byte_addr_mode;
- params->setup = spi_nor_default_setup;
params->otp.org = &info->otp_org;

/* Default to 16-bit Write Status (01h) Command */
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 2afb610853a9..4fe16b5aa3f5 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -257,10 +257,10 @@ struct spi_nor_otp {
* @convert_addr: converts an absolute address into something the flash
* will understand. Particularly useful when pagesize is
* not a power-of-2.
- * @setup: configures the SPI NOR memory. Useful for SPI NOR
- * flashes that have peculiarities to the SPI NOR standard
- * e.g. different opcodes, specific address calculation,
- * page size, etc.
+ * @setup: (optional) configures the SPI NOR memory. Useful for
+ * SPI NOR flashes that have peculiarities to the SPI NOR
+ * standard e.g. different opcodes, specific address
+ * calculation, page size, etc.
* @locking_ops: SPI NOR locking methods.
*/
struct spi_nor_flash_parameter {
--
2.30.2

2022-02-22 04:57:50

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 24/32] mtd: spi-nor: move all micron-st specifics into micron-st.c

The flag status register is only available on micron flashes. Move all
the functions around that into the micron module.

This is almost a mechanical move except for the spi_nor_fsr_ready()
which now also checks the normal status register. Previously, this was
done in spi_nor_ready().

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/core.c | 123 +----------------------------
drivers/mtd/spi-nor/micron-st.c | 133 ++++++++++++++++++++++++++++++++
include/linux/mtd/spi-nor.h | 8 --
3 files changed, 134 insertions(+), 130 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index ae1560250c48..5b56d718692b 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -412,50 +412,6 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
return ret;
}

-/**
- * spi_nor_read_fsr() - Read the Flag Status Register.
- * @nor: pointer to 'struct spi_nor'
- * @fsr: pointer to a DMA-able buffer where the value of the
- * Flag Status Register will be written. Should be at least 2
- * bytes.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, fsr, 0));
-
- if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
- op.addr.nbytes = nor->params->rdsr_addr_nbytes;
- op.dummy.nbytes = nor->params->rdsr_dummy;
- /*
- * We don't want to read only one byte in DTR mode. So,
- * read 2 and then discard the second byte.
- */
- op.data.nbytes = 2;
- }
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
- 1);
- }
-
- if (ret)
- dev_dbg(nor->dev, "error %d reading FSR\n", ret);
-
- return ret;
-}
-
/**
* spi_nor_read_cr() - Read the Configuration Register using the
* SPINOR_OP_RDCR (35h) command.
@@ -664,75 +620,6 @@ int spi_nor_sr_ready(struct spi_nor *nor)
return !(nor->bouncebuf[0] & SR_WIP);
}

-/**
- * spi_nor_clear_fsr() - Clear the Flag Status Register.
- * @nor: pointer to 'struct spi_nor'.
- */
-static void spi_nor_clear_fsr(struct spi_nor *nor)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
- NULL, 0);
- }
-
- if (ret)
- dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
-}
-
-/**
- * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
- * ready for new commands.
- * @nor: pointer to 'struct spi_nor'.
- *
- * Return: 1 if ready, 0 if not ready, -errno on errors.
- */
-static int spi_nor_fsr_ready(struct spi_nor *nor)
-{
- int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
-
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
- if (nor->bouncebuf[0] & FSR_E_ERR)
- dev_err(nor->dev, "Erase operation failed.\n");
- else
- dev_err(nor->dev, "Program operation failed.\n");
-
- if (nor->bouncebuf[0] & FSR_PT_ERR)
- dev_err(nor->dev,
- "Attempted to modify a protected sector.\n");
-
- spi_nor_clear_fsr(nor);
-
- /*
- * WEL bit remains set to one when an erase or page program
- * error occurs. Issue a Write Disable command to protect
- * against inadvertent writes that can possibly corrupt the
- * contents of the memory.
- */
- ret = spi_nor_write_disable(nor);
- if (ret)
- return ret;
-
- return -EIO;
- }
-
- return !!(nor->bouncebuf[0] & FSR_READY);
-}
-
/**
* spi_nor_ready() - Query the flash to see if it is ready for new commands.
* @nor: pointer to 'struct spi_nor'.
@@ -741,19 +628,11 @@ static int spi_nor_fsr_ready(struct spi_nor *nor)
*/
static int spi_nor_ready(struct spi_nor *nor)
{
- int sr, fsr;
-
/* Flashes might override the standard routine. */
if (nor->params->ready)
return nor->params->ready(nor);

- sr = spi_nor_sr_ready(nor);
- if (sr < 0)
- return sr;
- fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
- if (fsr < 0)
- return fsr;
- return sr && fsr;
+ return spi_nor_sr_ready(nor);
}

/**
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 7a68f2ad3ea1..8877b122cf42 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -8,6 +8,8 @@

#include "core.h"

+#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
+#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
@@ -17,6 +19,12 @@
#define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */
#define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */

+/* Flag Status Register bits */
+#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
+#define FSR_E_ERR BIT(5) /* Erase operation status */
+#define FSR_P_ERR BIT(4) /* Program operation status */
+#define FSR_PT_ERR BIT(1) /* Protection error bit */
+
static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
{
struct spi_mem_op op;
@@ -273,6 +281,124 @@ static int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
return spi_nor_write_disable(nor);
}

+/**
+ * spi_nor_read_fsr() - Read the Flag Status Register.
+ * @nor: pointer to 'struct spi_nor'
+ * @fsr: pointer to a DMA-able buffer where the value of the
+ * Flag Status Register will be written. Should be at least 2
+ * bytes.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(1, fsr, 0));
+
+ if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+ op.addr.nbytes = nor->params->rdsr_addr_nbytes;
+ op.dummy.nbytes = nor->params->rdsr_dummy;
+ /*
+ * We don't want to read only one byte in DTR mode. So,
+ * read 2 and then discard the second byte.
+ */
+ op.data.nbytes = 2;
+ }
+
+ spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
+ 1);
+ }
+
+ if (ret)
+ dev_dbg(nor->dev, "error %d reading FSR\n", ret);
+
+ return ret;
+}
+
+/**
+ * spi_nor_clear_fsr() - Clear the Flag Status Register.
+ * @nor: pointer to 'struct spi_nor'.
+ */
+static void spi_nor_clear_fsr(struct spi_nor *nor)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
+ NULL, 0);
+ }
+
+ if (ret)
+ dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
+}
+
+/**
+ * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
+ * ready for new commands.
+ * @nor: pointer to 'struct spi_nor'.
+ *
+ * Return: 1 if ready, 0 if not ready, -errno on errors.
+ */
+static int spi_nor_fsr_ready(struct spi_nor *nor)
+{
+ int sr_ready, ret;
+
+ sr_ready = spi_nor_sr_ready(nor);
+ if (sr_ready < 0)
+ return sr_ready;
+
+ ret = spi_nor_read_fsr(nor, nor->bouncebuf);
+ if (ret)
+ return ret;
+
+ if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
+ if (nor->bouncebuf[0] & FSR_E_ERR)
+ dev_err(nor->dev, "Erase operation failed.\n");
+ else
+ dev_err(nor->dev, "Program operation failed.\n");
+
+ if (nor->bouncebuf[0] & FSR_PT_ERR)
+ dev_err(nor->dev,
+ "Attempted to modify a protected sector.\n");
+
+ spi_nor_clear_fsr(nor);
+
+ /*
+ * WEL bit remains set to one when an erase or page program
+ * error occurs. Issue a Write Disable command to protect
+ * against inadvertent writes that can possibly corrupt the
+ * contents of the memory.
+ */
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ return ret;
+
+ return -EIO;
+ }
+
+ return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);
+}
+
static void micron_st_nor_default_init(struct spi_nor *nor)
{
nor->flags |= SNOR_F_HAS_LOCK;
@@ -281,8 +407,15 @@ static void micron_st_nor_default_init(struct spi_nor *nor)
nor->params->set_4byte_addr_mode = micron_st_nor_set_4byte_addr_mode;
}

+static void micron_st_nor_late_init(struct spi_nor *nor)
+{
+ if (nor->flags & SNOR_F_USE_FSR)
+ nor->params->ready = spi_nor_fsr_ready;
+}
+
static const struct spi_nor_fixups micron_st_nor_fixups = {
.default_init = micron_st_nor_default_init,
+ .late_init = micron_st_nor_late_init,
};

const struct spi_nor_manufacturer spi_nor_micron = {
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index b44b05a6f934..4622251a79ff 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -47,8 +47,6 @@
#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
-#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
-#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
@@ -126,12 +124,6 @@
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */

-/* Flag Status Register bits */
-#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
-#define FSR_E_ERR BIT(5) /* Erase operation status */
-#define FSR_P_ERR BIT(4) /* Program operation status */
-#define FSR_PT_ERR BIT(1) /* Protection error bit */
-
/* Status Register 2 bits. */
#define SR2_QUAD_EN_BIT1 BIT(1)
#define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
--
2.30.2

2022-02-22 05:24:51

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 30/32] mtd: spi-nor: spansion: rename vendor specific functions and defines

Drop the generic spi_nor prefix for all the spansion functions.

Signed-off-by: Michael Walle <[email protected]>
---
drivers/mtd/spi-nor/spansion.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 33ebecbcc3c7..b5bc33dab5ed 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -309,10 +309,10 @@ static const struct flash_info spansion_nor_parts[] = {
};

/**
- * spi_nor_clear_sr() - Clear the Status Register.
+ * spansion_nor_clear_sr() - Clear the Status Register.
* @nor: pointer to 'struct spi_nor'.
*/
-static void spi_nor_clear_sr(struct spi_nor *nor)
+static void spansion_nor_clear_sr(struct spi_nor *nor)
{
int ret;

@@ -336,13 +336,13 @@ static void spi_nor_clear_sr(struct spi_nor *nor)
}

/**
- * spi_nor_sr_ready_and_clear() - Query the Status Register to see if the flash
- * is ready for new commands and clear it.
+ * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
+ * flash is ready for new commands and clear it.
* @nor: pointer to 'struct spi_nor'.
*
* Return: 1 if ready, 0 if not ready, -errno on errors.
*/
-static int spi_nor_sr_ready_and_clear(struct spi_nor *nor)
+static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
{
int ret;

@@ -356,7 +356,7 @@ static int spi_nor_sr_ready_and_clear(struct spi_nor *nor)
else
dev_err(nor->dev, "Programming Error occurred\n");

- spi_nor_clear_sr(nor);
+ spansion_nor_clear_sr(nor);

/*
* WEL bit remains set to one when an erase or page program
@@ -384,7 +384,7 @@ static void spansion_nor_late_init(struct spi_nor *nor)
}

if (nor->info->mfr_flags & USE_CLSR)
- nor->params->ready = spi_nor_sr_ready_and_clear;
+ nor->params->ready = spansion_nor_sr_ready_and_clear;
}

static const struct spi_nor_fixups spansion_nor_fixups = {
--
2.30.2

2022-02-22 05:34:06

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 09/32] mtd: spi-nor: issi: unify function names

2022-02-22 05:36:28

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 15/32] mtd: spi-nor: xilinx: unify function names

2022-02-22 05:41:21

by Michael Walle

[permalink] [raw]

Subject: [PATCH v3 29/32] mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag

Now that all functions using that flag are local to the spansion module,
we can convert the flag to a manufacturer one.

Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
---
drivers/mtd/spi-nor/core.c | 3 --
drivers/mtd/spi-nor/core.h | 3 --
drivers/mtd/spi-nor/spansion.c | 55 +++++++++++++++++++++-------------
3 files changed, 34 insertions(+), 27 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index e2b8b0a438ce..f5a2f37d140e 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2447,9 +2447,6 @@ static void spi_nor_init_flags(struct spi_nor *nor)

if (flags & NO_CHIP_ERASE)
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
-
- if (flags & USE_CLSR)
- nor->flags |= SNOR_F_USE_CLSR;
}

/**
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index a02bf54289fb..2130a96e2044 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -14,7 +14,6 @@
enum spi_nor_option_flags {
SNOR_F_HAS_SR_TB = BIT(1),
SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
- SNOR_F_USE_CLSR = BIT(4),
SNOR_F_BROKEN_RESET = BIT(5),
SNOR_F_4B_OPCODES = BIT(6),
SNOR_F_HAS_4BAIT = BIT(7),
@@ -347,7 +346,6 @@ struct spi_nor_fixups {
* SPI_NOR_NO_ERASE: no erase command needed.
* NO_CHIP_ERASE: chip does not support chip erase.
* SPI_NOR_NO_FR: can't do fastread.
- * USE_CLSR: use CLSR command.
*
* @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
* Used when SFDP tables are not defined in the flash. These
@@ -398,7 +396,6 @@ struct flash_info {
#define SPI_NOR_NO_ERASE BIT(6)
#define NO_CHIP_ERASE BIT(7)
#define SPI_NOR_NO_FR BIT(8)
-#define USE_CLSR BIT(9)

u8 no_sfdp_flags;
#define SPI_NOR_SKIP_SFDP BIT(0)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 88ecf117016f..33ebecbcc3c7 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -8,6 +8,9 @@

#include "core.h"

+/* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */
+#define USE_CLSR BIT(0)
+
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
@@ -212,43 +215,53 @@ static const struct flash_info spansion_nor_parts[] = {
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128)
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
- FLAGS(USE_CLSR)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
- FLAGS(USE_CLSR)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
- FLAGS(USE_CLSR)
NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ) },
+ SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
- FLAGS(USE_CLSR)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
- FLAGS(SPI_NOR_HAS_LOCK | USE_CLSR)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ FLAGS(SPI_NOR_HAS_LOCK)
+ NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
- FLAGS(USE_CLSR)
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
.fixups = &s25fs_s_fixups, },
{ "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
- FLAGS(USE_CLSR)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
- FLAGS(USE_CLSR)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
- FLAGS(USE_CLSR)
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
.fixups = &s25fs_s_fixups, },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
- FLAGS(USE_CLSR)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
- FLAGS(USE_CLSR)
- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
+ },
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) },
{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) },
{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) },
@@ -370,7 +383,7 @@ static void spansion_nor_late_init(struct spi_nor *nor)
nor->mtd.erasesize = nor->info->sector_size;
}

- if (nor->flags & SNOR_F_USE_CLSR)
+ if (nor->info->mfr_flags & USE_CLSR)
nor->params->ready = spi_nor_sr_ready_and_clear;
}

--
2.30.2