Hi All,
This patch series adds support for below IP blocks to Renesas RZ/V2L SoC:
* SDHI
* CANFD
* I2C
* OSTM
* WDT
* SSI
* USB2
* RPC-IF (SBC)
* RSPI
The above peripherals can now be operational on Renesas RZ/V2L SMARC EVK
with this series.
Note:
* Im just sending the DTS/I changes as separate series and shall post the
binding doc changes individually to the corresponding subsystems.
* Patch 05/12 depends on [0]
* For OSTM/SSI/USB to work on RZ/V2L SoC ARCH_R9A07G044 needs to be
enabled as the corresponding drivers have ARCH_R9A07G044 as dependency
which I intend to change it to ARCH_RZG2L. This will be updated once patch
[1] is part of -rc* cycle.
* Patch series applies on top of [2].
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
[email protected]/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
[email protected]/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
[email protected]/
Cheers,
Prabhakar
Lad Prabhakar (12):
arm64: dts: renesas: r9a07g054: Fillup the SDHI{0,1} stub nodes
arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting gpio-hog pins
related to SDHI
arm64: dts: renesas: r9a07g054: Fillup the CANFD stub node
arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting can{0,1}-stb-hog
nodes
arm64: dts: renesas: r9a07g054: Fillup the I2C{0,1,2,3} stub nodes
arm64: dts: renesas: r9a07g054: Fillup the sbc stub node
arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodes
arm64: dts: renesas: r9a07g054: Fillup the WDT{0,1,2} stub nodes
arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the
SSI0 stub node
arm64: dts: renesas: r9a07g054: Add USB2.0 phy and host support
arm64: dts: renesas: r9a07g054: Add USB2.0 device support
arm64: dts: renesas: r9a07g054: Add SPI{0,2} nodes and fillup SPI1
stub node
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 413 +++++++++++++++++-
.../boot/dts/renesas/r9a07g054l2-smarc.dts | 8 -
2 files changed, 390 insertions(+), 31 deletions(-)
--
2.17.1
Add USB2.0 phy and host support to RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 74 ++++++++++++++++++++--
1 file changed, 67 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index e3a9f78b7fb8..7d9ea17352a4 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -652,38 +652,98 @@
};
phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g054-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
reg = <0 0x11c40000 0 0x10000>;
- /* place holder */
+ clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
+ resets = <&cpg R9A07G054_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ status = "disabled";
};
ohci0: usb@11c50000 {
+ compatible = "generic-ohci";
reg = <0 0x11c50000 0 0x100>;
- /* place holder */
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G054_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
};
ohci1: usb@11c70000 {
+ compatible = "generic-ohci";
reg = <0 0x11c70000 0 0x100>;
- /* place holder */
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G054_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
};
ehci0: usb@11c50100 {
+ compatible = "generic-ehci";
reg = <0 0x11c50100 0 0x100>;
- /* place holder */
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G054_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
ehci1: usb@11c70100 {
+ compatible = "generic-ehci";
reg = <0 0x11c70100 0 0x100>;
- /* place holder */
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G054_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
usb2_phy0: usb-phy@11c50200 {
+ compatible = "renesas,usb2-phy-r9a07g054",
+ "renesas,rzg2l-usb2-phy";
reg = <0 0x11c50200 0 0x700>;
- /* place holder */
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
usb2_phy1: usb-phy@11c70200 {
+ compatible = "renesas,usb2-phy-r9a07g054",
+ "renesas,rzg2l-usb2-phy";
reg = <0 0x11c70200 0 0x700>;
- /* place holder */
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
hsusb: usb@11c60000 {
--
2.17.1
Fillup the CANFD stub node in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 31 +++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 0b0e924e28ae..6e89bd126788 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -234,8 +234,37 @@
};
canfd: can@10050000 {
+ compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
reg = <0 0x10050000 0 0x8000>;
- /* place holder */
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g_err", "g_recc",
+ "ch0_err", "ch0_rec", "ch0_trx",
+ "ch1_err", "ch1_rec", "ch1_trx";
+ clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
+ <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
+ assigned-clock-rates = <50000000>;
+ resets = <&cpg R9A07G054_CANFD_RSTP_N>,
+ <&cpg R9A07G054_CANFD_RSTC_N>;
+ reset-names = "rstp_n", "rstc_n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+ channel1 {
+ status = "disabled";
+ };
};
i2c0: i2c@10058000 {
--
2.17.1
Fillup the I2C{0,1,2,3} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 73 +++++++++++++++++++++-
1 file changed, 70 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 6e89bd126788..fafb986fe3bc 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -270,22 +270,89 @@
i2c0: i2c@10058000 {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
reg = <0 0x10058000 0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G054_I2C0_MRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
i2c1: i2c@10058400 {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
reg = <0 0x10058400 0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G054_I2C1_MRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10058800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
+ reg = <0 0x10058800 0 0x400>;
+ interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G054_I2C2_MRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
i2c3: i2c@10058c00 {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
reg = <0 0x10058c00 0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
+ clock-frequency = <100000>;
+ resets = <&cpg R9A07G054_I2C3_MRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
adc: adc@10059000 {
--
2.17.1
Hi Prabhakar,
CC Wolfram
On Sun, Feb 27, 2022 at 9:38 PM Lad Prabhakar
<[email protected]> wrote:
> This patch series adds support for below IP blocks to Renesas RZ/V2L SoC:
> * SDHI
> * CANFD
> * I2C
> * OSTM
> * WDT
> * SSI
> * USB2
> * RPC-IF (SBC)
> * RSPI
>
> The above peripherals can now be operational on Renesas RZ/V2L SMARC EVK
> with this series.
Thanks for your series!
> Note:
> * Im just sending the DTS/I changes as separate series and shall post the
> binding doc changes individually to the corresponding subsystems.
> * Patch 05/12 depends on [0]
Good to know. So I think it would be great if that patch would make
v5.18-rc1, through the i2c tree.
> * For OSTM/SSI/USB to work on RZ/V2L SoC ARCH_R9A07G044 needs to be
> enabled as the corresponding drivers have ARCH_R9A07G044 as dependency
> which I intend to change it to ARCH_RZG2L. This will be updated once patch
> [1] is part of -rc* cycle.
> * Patch series applies on top of [2].
>
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> [email protected]/
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> [email protected]/
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
> [email protected]/
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (12):
> arm64: dts: renesas: r9a07g054: Fillup the SDHI{0,1} stub nodes
> arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting gpio-hog pins
> related to SDHI
> arm64: dts: renesas: r9a07g054: Fillup the CANFD stub node
> arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting can{0,1}-stb-hog
> nodes
> arm64: dts: renesas: r9a07g054: Fillup the I2C{0,1,2,3} stub nodes
> arm64: dts: renesas: r9a07g054: Fillup the sbc stub node
> arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodes
> arm64: dts: renesas: r9a07g054: Fillup the WDT{0,1,2} stub nodes
> arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the
> SSI0 stub node
> arm64: dts: renesas: r9a07g054: Add USB2.0 phy and host support
> arm64: dts: renesas: r9a07g054: Add USB2.0 device support
> arm64: dts: renesas: r9a07g054: Add SPI{0,2} nodes and fillup SPI1
> stub node
>
> arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 413 +++++++++++++++++-
> .../boot/dts/renesas/r9a07g054l2-smarc.dts | 8 -
> 2 files changed, 390 insertions(+), 31 deletions(-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Sun, Feb 27, 2022 at 9:38 PM Lad Prabhakar
<[email protected]> wrote:
> Add USB2.0 phy and host support to RZ/V2L (R9A07G054) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Sun, Feb 27, 2022 at 9:38 PM Lad Prabhakar
<[email protected]> wrote:
> Fillup the CANFD stub node in RZ/V2L (R9A07G054) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Sun, Feb 27, 2022 at 9:38 PM Lad Prabhakar
<[email protected]> wrote:
> Fillup the I2C{0,1,2,3} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds