Add missing nodes for the flexcom blocks and a node for the SGPIO
block. Then add basic support for the Kontron KSwitch D10.
Microchip, please take a closer look at the compatible strings of
the newly added nodes.
changes since v1:
- fixed indendation
- keep compatible, reg first, move #address-cells and #size-cells
towards the end
Michael Walle (7):
ARM: dts: lan966x: swap dma channels for crypto node
ARM: dts: lan966x: add sgpio node
ARM: dts: lan966x: add missing uart DMA channel
ARM: dts: lan966x: add all flexcom usart nodes
ARM: dts: lan966x: add flexcom SPI nodes
ARM: dts: lan966x: add flexcom I2C nodes
ARM: dts: lan966x: add basic Kontron KSwitch D10 support
arch/arm/boot/dts/Makefile | 3 +-
...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 159 ++++++++++++
arch/arm/boot/dts/lan966x.dtsi | 227 +++++++++++++++++-
3 files changed, 385 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
--
2.30.2
Add all the SPI nodes for the flexcom IP block. Keep them
disabled by default.
Signed-off-by: Michael Walle <[email protected]>
---
arch/arm/boot/dts/lan966x.dtsi | 75 ++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index d7eacb0144f5..a61d394ad04d 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -105,6 +105,21 @@ usart0: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi0: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx1: flexcom@e0044000 {
@@ -128,6 +143,21 @@ usart1: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi1: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
trng: rng@e0048000 {
@@ -168,6 +198,21 @@ usart2: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi2: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx3: flexcom@e0064000 {
@@ -191,6 +236,21 @@ usart3: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi3: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+ <&dma0 AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
dma0: dma-controller@e0068000 {
@@ -233,6 +293,21 @@ usart4: serial@200 {
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi4: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
timer0: timer@e008c000 {
--
2.30.2
Add all I2C nodes of the flexcom IP blocks. The driver supports
FIFO, DMA or both combined. But the latter isn't working correctly.
Thus, skip the fifo-size property for now. DMA is doing single byte
reads in this case.
Keep the nodes disabled by default.
Signed-off-by: Michael Walle <[email protected]>
---
arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index a61d394ad04d..95d58bdca3f0 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -120,6 +120,19 @@ spi0: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c0: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx1: flexcom@e0044000 {
@@ -158,6 +171,19 @@ spi1: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c1: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
trng: rng@e0048000 {
@@ -213,6 +239,19 @@ spi2: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c2: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx3: flexcom@e0064000 {
@@ -251,6 +290,19 @@ spi3: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c3: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+ <&dma0 AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
dma0: dma-controller@e0068000 {
@@ -308,6 +360,19 @@ spi4: spi@400 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c4: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
timer0: timer@e008c000 {
--
2.30.2
Add all the remaining usart nodes for the flexcom block. Although the
DMA channels are specified, DMA is not enabled by default because break
detection doesn't work with DMA.
Keep the nodes disabled by default.
Signed-off-by: Michael Walle <[email protected]>
---
arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 230de3bdd5f1..d7eacb0144f5 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -92,6 +92,19 @@ flx0: flexcom@e0040000 {
#size-cells = <1>;
ranges = <0x0 0xe0040000 0x800>;
status = "disabled";
+
+ usart0: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
flx1: flexcom@e0044000 {
@@ -102,6 +115,19 @@ flx1: flexcom@e0044000 {
#size-cells = <1>;
ranges = <0x0 0xe0044000 0x800>;
status = "disabled";
+
+ usart1: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
trng: rng@e0048000 {
@@ -129,6 +155,19 @@ flx2: flexcom@e0060000 {
#size-cells = <1>;
ranges = <0x0 0xe0060000 0x800>;
status = "disabled";
+
+ usart2: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
flx3: flexcom@e0064000 {
@@ -181,6 +220,19 @@ flx4: flexcom@e0070000 {
#size-cells = <1>;
ranges = <0x0 0xe0070000 0x800>;
status = "disabled";
+
+ usart4: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
timer0: timer@e008c000 {
--
2.30.2
Add the device tree node for the SGPIO IP block reused from the
SparX-5. Keep the node disabled by default.
Signed-off-by: Michael Walle <[email protected]>
---
arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 5e9cbc8cdcbc..39dfdb8e29ed 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 {
#interrupt-cells = <2>;
};
+ sgpio: gpio@e2004190 {
+ compatible = "microchip,sparx5-sgpio";
+ reg = <0xe2004190 0x118>;
+ clocks = <&sys_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgpio_in: gpio@0 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ sgpio_out: gpio@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ };
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
--
2.30.2
The YAML binding (crypto/atmel,at91sam9g46-aes.yaml) mandates the order
of the channels. Swap them to pass devicetree validation.
Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291")
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
---
arch/arm/boot/dts/lan966x.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 7d2869648050..5e9cbc8cdcbc 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -114,9 +114,9 @@ aes: crypto@e004c000 {
compatible = "atmel,at91sam9g46-aes";
reg = <0xe004c000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
- <&dma0 AT91_XDMAC_DT_PERID(12)>;
- dma-names = "rx", "tx";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
+ <&dma0 AT91_XDMAC_DT_PERID(13)>;
+ dma-names = "tx", "rx";
clocks = <&nic_clk>;
clock-names = "aes_clk";
};
--
2.30.2
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add the device tree node for the SGPIO IP block reused from the
> SparX-5. Keep the node disabled by default.
>
> Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 5e9cbc8cdcbc..39dfdb8e29ed 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 {
> #interrupt-cells = <2>;
> };
>
> + sgpio: gpio@e2004190 {
> + compatible = "microchip,sparx5-sgpio";
> + reg = <0xe2004190 0x118>;
> + clocks = <&sys_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sgpio_in: gpio@0 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <0>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + sgpio_out: gpio@1 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <1>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + };
> + };
> +
> gic: interrupt-controller@e8c11000 {
> compatible = "arm,gic-400", "arm,cortex-a7-gic";
> #interrupt-cells = <3>;
> --
> 2.30.2
>
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add all the SPI nodes for the flexcom IP block. Keep them
> disabled by default.
>
> Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 75 ++++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index d7eacb0144f5..a61d394ad04d 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -105,6 +105,21 @@ usart0: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi0: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
> + <&dma0 AT91_XDMAC_DT_PERID(2)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx1: flexcom@e0044000 {
> @@ -128,6 +143,21 @@ usart1: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi1: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
> + <&dma0 AT91_XDMAC_DT_PERID(4)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> trng: rng@e0048000 {
> @@ -168,6 +198,21 @@ usart2: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi2: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
> + <&dma0 AT91_XDMAC_DT_PERID(6)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx3: flexcom@e0064000 {
> @@ -191,6 +236,21 @@ usart3: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi3: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
> + <&dma0 AT91_XDMAC_DT_PERID(8)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> dma0: dma-controller@e0068000 {
> @@ -233,6 +293,21 @@ usart4: serial@200 {
> atmel,fifo-size = <32>;
> status = "disabled";
> };
> +
> + spi4: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
> + <&dma0 AT91_XDMAC_DT_PERID(10)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> timer0: timer@e008c000 {
> --
> 2.30.2
>
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add all I2C nodes of the flexcom IP blocks. The driver supports
> FIFO, DMA or both combined. But the latter isn't working correctly.
> Thus, skip the fifo-size property for now. DMA is doing single byte
> reads in this case.
>
> Keep the nodes disabled by default.
>
> Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index a61d394ad04d..95d58bdca3f0 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -120,6 +120,19 @@ spi0: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c0: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
> + <&dma0 AT91_XDMAC_DT_PERID(2)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx1: flexcom@e0044000 {
> @@ -158,6 +171,19 @@ spi1: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c1: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
> + <&dma0 AT91_XDMAC_DT_PERID(4)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> trng: rng@e0048000 {
> @@ -213,6 +239,19 @@ spi2: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c2: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
> + <&dma0 AT91_XDMAC_DT_PERID(6)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx3: flexcom@e0064000 {
> @@ -251,6 +290,19 @@ spi3: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c3: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
> + <&dma0 AT91_XDMAC_DT_PERID(8)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> dma0: dma-controller@e0068000 {
> @@ -308,6 +360,19 @@ spi4: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c4: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
> + <&dma0 AT91_XDMAC_DT_PERID(10)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> timer0: timer@e008c000 {
> --
> 2.30.2
>
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add all the remaining usart nodes for the flexcom block. Although the
> DMA channels are specified, DMA is not enabled by default because break
> detection doesn't work with DMA.
>
> Keep the nodes disabled by default.
>
> Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 230de3bdd5f1..d7eacb0144f5 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -92,6 +92,19 @@ flx0: flexcom@e0040000 {
> #size-cells = <1>;
> ranges = <0x0 0xe0040000 0x800>;
> status = "disabled";
> +
> + usart0: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
> + <&dma0 AT91_XDMAC_DT_PERID(2)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> };
>
> flx1: flexcom@e0044000 {
> @@ -102,6 +115,19 @@ flx1: flexcom@e0044000 {
> #size-cells = <1>;
> ranges = <0x0 0xe0044000 0x800>;
> status = "disabled";
> +
> + usart1: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
> + <&dma0 AT91_XDMAC_DT_PERID(4)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> };
>
> trng: rng@e0048000 {
> @@ -129,6 +155,19 @@ flx2: flexcom@e0060000 {
> #size-cells = <1>;
> ranges = <0x0 0xe0060000 0x800>;
> status = "disabled";
> +
> + usart2: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
> + <&dma0 AT91_XDMAC_DT_PERID(6)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> };
>
> flx3: flexcom@e0064000 {
> @@ -181,6 +220,19 @@ flx4: flexcom@e0070000 {
> #size-cells = <1>;
> ranges = <0x0 0xe0070000 0x800>;
> status = "disabled";
> +
> + usart4: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
> + <&dma0 AT91_XDMAC_DT_PERID(10)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> };
>
> timer0: timer@e008c000 {
> --
> 2.30.2
>