Hi,
Not tested on hardware, so please kindly test.
Bindings maintainers might need checking - taken from git log.
Changes since v2
================
1. Do not deprecate freq-table-hz, but instead update dtschema to accept
uint32-matrix. See:
https://github.com/devicetree-org/dt-schema/pull/69
2. Drop patches and changes related to freq-table-hz -> freq-table conversion.
3. Add tags.
4. Change maintainer of qcom,ufs.
Changes since v1
================
1. Make freq-table as matrix of tuples (Nishanth).
2. New patches: convert all bindings and fix up DTS files.
3. Several minor fixes in UFS bindings.
Dependencies
============
None dependencies. The DTS patches can go independently via respective
maintainers. The dt-bindings patches could go via UFS tree.
Best regards,
Krzysztof
Krzysztof Kozlowski (12):
dt-bindings: ufs: add common platform bindings
dt-bindings: ufs: samsung,exynos-ufs: use common bindings
dt-bindings: ufs: cdns,ufshc: convert to dtschema
dt-bindings: ufs: drop unused/old ufs-qcom PHY bindings
dt-bindings: ufs: qcom,ufs: convert to dtschema
dt-bindings: ufs: hisilicon,ufs: convert to dtschema
dt-bindings: ufs: mediatek,ufs: convert to dtschema
dt-bindings: ufs: snps,tc-dwc-g210: convert to dtschema
arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS
arm64: dts: qcom: msm8996: drop unsupported UFS
vddp-ref-clk-max-microamp
arm64: dts: qcom: msm8996: correct UFS compatible
arm64: dts: qcom: sm8350: drop duplicated ref_clk in UFS
.../devicetree/bindings/ufs/cdns,ufshc.txt | 32 ---
.../devicetree/bindings/ufs/cdns,ufshc.yaml | 68 +++++
.../bindings/ufs/hisilicon,ufs.yaml | 90 +++++++
.../devicetree/bindings/ufs/mediatek,ufs.yaml | 67 +++++
.../devicetree/bindings/ufs/qcom,ufs.yaml | 242 ++++++++++++++++++
.../bindings/ufs/samsung,exynos-ufs.yaml | 13 +-
.../bindings/ufs/snps,tc-dwc-g210.yaml | 51 ++++
.../bindings/ufs/tc-dwc-g210-pltfrm.txt | 26 --
.../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 7 +-
.../devicetree/bindings/ufs/ufs-common.yaml | 82 ++++++
.../devicetree/bindings/ufs/ufs-hisi.txt | 42 ---
.../devicetree/bindings/ufs/ufs-mediatek.txt | 45 ----
.../devicetree/bindings/ufs/ufs-qcom.txt | 63 -----
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 90 -------
MAINTAINERS | 1 +
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 +-
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 +-
.../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 1 -
arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 -
20 files changed, 614 insertions(+), 320 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/hisilicon,ufs.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/snps,tc-dwc-g210.yaml
delete mode 100644 Documentation/devicetree/bindings/ufs/tc-dwc-g210-pltfrm.txt
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-common.yaml
delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-qcom.txt
delete mode 100644 Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
--
2.32.0
Convert the Qualcomm Universal Flash Storage (UFS) Controller to DT
schema format.
Except the conversion, add also properties already present in DTS:
iommus, interconnects and power-domains.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/ufs/qcom,ufs.yaml | 242 ++++++++++++++++++
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 90 -------
2 files changed, 242 insertions(+), 90 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
delete mode 100644 Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
new file mode 100644
index 000000000000..5b3a2157f7e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -0,0 +1,242 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Universal Flash Storage (UFS) Controller
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Andy Gross <[email protected]>
+
+# Select only our matches, not all jedec,ufs-2.0
+select:
+ properties:
+ compatible:
+ contains:
+ const: qcom,ufshc
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,msm8994-ufshc
+ - qcom,msm8996-ufshc
+ - qcom,msm8998-ufshc
+ - qcom,sdm845-ufshc
+ - qcom,sm8150-ufshc
+ - qcom,sm8250-ufshc
+ - qcom,sm8350-ufshc
+ - qcom,sm8450-ufshc
+ - const: qcom,ufshc
+ - const: jedec,ufs-2.0
+
+ clocks:
+ minItems: 8
+ maxItems: 11
+
+ clock-names:
+ minItems: 8
+ maxItems: 11
+
+ interconnects:
+ minItems: 2
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ufs-ddr
+ - const: cpu-ufs
+
+ iommus:
+ minItems: 1
+ maxItems: 2
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: ufsphy
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+ reset-names:
+ items:
+ - const: rst
+
+ reset-gpios:
+ maxItems: 1
+ description:
+ GPIO connected to the RESET pin of the UFS memory device.
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: ufs-common.yaml
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-ufshc
+ - qcom,sm8250-ufshc
+ - qcom,sm8350-ufshc
+ - qcom,sm8450-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ - const: rx_lane1_sync_clk
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-ufshc
+ - qcom,sm8150-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 9
+ maxItems: 9
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ - const: rx_lane1_sync_clk
+ - const: ice_core_clk
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 11
+ maxItems: 11
+ clock-names:
+ items:
+ - const: core_clk_src
+ - const: core_clk
+ - const: bus_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro_src
+ - const: core_clk_unipro
+ - const: core_clk_ice
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ # TODO: define clock bindings for qcom,msm8994-ufshc
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8450.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ufs@1d84000 {
+ compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l7b_2p5>;
+ vcc-max-microamp = <1100000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ iommus = <&apps_smmu 0xe0 0x0>;
+ interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz = <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
deleted file mode 100644
index d0fee78e6203..000000000000
--- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-* Universal Flash Storage (UFS) Host Controller
-
-UFSHC nodes are defined to describe on-chip UFS host controllers.
-Each UFS controller instance should have its own node.
-
-Required properties:
-- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
-
- For Qualcomm SoCs must contain, as below, an
- SoC-specific compatible along with "qcom,ufshc" and
- the appropriate jedec string:
- "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
-- interrupts : <interrupt mapping for UFS host controller IRQ>
-- reg : <registers mapping>
-
-Optional properties:
-- phys : phandle to UFS PHY node
-- phy-names : the string "ufsphy" when is found in a node, along
- with "phys" attribute, provides phandle to UFS PHY node
-- vdd-hba-supply : phandle to UFS host controller supply regulator node
-- vcc-supply : phandle to VCC supply regulator node
-- vccq-supply : phandle to VCCQ supply regulator node
-- vccq2-supply : phandle to VCCQ2 supply regulator node
-- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
- or 2.7-3.6V. This boolean property when set, specifies
- to use low voltage range of 1.7-1.95V. Note for external
- UFS cards this property is invalid and valid VCC range is
- always 2.7-3.6V.
-- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
-- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
-- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
-
-- clocks : List of phandle and clock specifier pairs
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property.
- "ref_clk" indicates reference clock frequency.
- UFS host supplies reference clock to UFS device and UFS device
- specification allows host to provide one of the 4 frequencies (19.2 MHz,
- 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
- parsed and used to update the reference clock setting in device.
- Defaults to 26 MHz(as per specification) if not specified by host.
-- freq-table-hz : Array of <min max> operating frequencies stored in the same
- order as the clocks property. If this property is not
- defined or a value in the array is "0" then it is assumed
- that the frequency is set by the parent clock or a
- fixed rate clock source.
--lanes-per-direction : number of lanes available per direction - either 1 or 2.
- Note that it is assume same number of lanes is used both
- directions at once. If not specified, default is 2 lanes per direction.
-- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose
- PHY reset from the UFS controller.
-- resets : reset node register
-- reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
-- reset-gpios : A phandle and gpio specifier denoting the GPIO connected
- to the RESET pin of the UFS memory device.
-
-Note: If above properties are not defined it can be assumed that the supply
-regulators or clocks are always on.
-
-Example:
- ufshc@fc598000 {
- compatible = "jedec,ufs-1.1";
- reg = <0xfc598000 0x800>;
- interrupts = <0 28 0>;
-
- vdd-hba-supply = <&xxx_reg0>;
- vcc-supply = <&xxx_reg1>;
- vcc-supply-1p8;
- vccq-supply = <&xxx_reg2>;
- vccq2-supply = <&xxx_reg3>;
- vcc-max-microamp = 500000;
- vccq-max-microamp = 200000;
- vccq2-max-microamp = 200000;
-
- clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
- clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
- freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
- resets = <&reset 0 1>;
- reset-names = "rst";
- phys = <&ufsphy1>;
- phy-names = "ufsphy";
- #reset-cells = <1>;
- };
--
2.32.0
The Qualcomm UFS bindings require to use specific (qcom,msm8996-ufshc)
and generic (jedec,ufs-2.0) compatibles.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index f0f81c23c16f..fa491f2271ff 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1730,7 +1730,8 @@ pcie2: pcie@610000 {
};
ufshc: ufshc@624000 {
- compatible = "qcom,ufshc";
+ compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
--
2.32.0
Convert the Cadence Universal Flash Storage (UFS) Controlle to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/ufs/cdns,ufshc.txt | 32 ---------
.../devicetree/bindings/ufs/cdns,ufshc.yaml | 68 +++++++++++++++++++
.../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 7 +-
3 files changed, 71 insertions(+), 36 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
deleted file mode 100644
index 02347b017abd..000000000000
--- a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-* Cadence Universal Flash Storage (UFS) Controller
-
-UFS nodes are defined to describe on-chip UFS host controllers.
-Each UFS controller instance should have its own node.
-Please see the ufshcd-pltfrm.txt for a list of all available properties.
-
-Required properties:
-- compatible : Compatible list, contains one of the following controllers:
- "cdns,ufshc" - Generic CDNS HCI,
- "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY
- complemented with the JEDEC version:
- "jedec,ufs-2.0"
-
-- reg : Address and length of the UFS register set.
-- interrupts : One interrupt mapping.
-- freq-table-hz : Clock frequency table.
- See the ufshcd-pltfrm.txt for details.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property. "core_clk" is mandatory.
- Depending on a type of a PHY,
- the "phy_clk" clock can also be added, if needed.
-
-Example:
- ufs@fd030000 {
- compatible = "cdns,ufshc", "jedec,ufs-2.0";
- reg = <0xfd030000 0x10000>;
- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
- freq-table-hz = <0 0>, <0 0>;
- clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
- clock-names = "core_clk", "phy_clk";
- };
diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml b/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
new file mode 100644
index 000000000000..d227dea368be
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence Universal Flash Storage (UFS) Controller
+
+maintainers:
+ - Jan Kotas <[email protected]>
+
+# Select only our matches, not all jedec,ufs-2.0
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - cdns,ufshc
+ - cdns,ufshc-m31-16nm
+ required:
+ - compatible
+
+allOf:
+ - $ref: ufs-common.yaml
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - cdns,ufshc
+ # CDNS UFS HC + M31 16nm PHY
+ - cdns,ufshc-m31-16nm
+ - const: jedec,ufs-2.0
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: core_clk
+ - const: phy_clk
+ - const: ref_clk
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ufs@fd030000 {
+ compatible = "cdns,ufshc", "jedec,ufs-2.0";
+ reg = <0xfd030000 0x10000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ freq-table-hz = <0 0>, <0 0>;
+ clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
+ clock-names = "core_clk", "phy_clk";
+ };
diff --git a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
index 4d13e6bc1c50..c5eca7735f76 100644
--- a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
@@ -47,11 +47,10 @@ required:
patternProperties:
"^ufs@[0-9a-f]+$":
- type: object
+ $ref: cdns,ufshc.yaml
description: |
- Cadence UFS controller node must be the child node. Refer
- Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding
- documentation of child node
+ Cadence UFS controller node must be the child node.
+ unevaluatedProperties: false
additionalProperties: false
--
2.32.0
On Sun, 06 Mar 2022 12:11:16 +0100, Krzysztof Kozlowski wrote:
> Convert the Cadence Universal Flash Storage (UFS) Controlle to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> .../devicetree/bindings/ufs/cdns,ufshc.txt | 32 ---------
> .../devicetree/bindings/ufs/cdns,ufshc.yaml | 68 +++++++++++++++++++
> .../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 7 +-
> 3 files changed, 71 insertions(+), 36 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
> create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/ufs/cdns,ufshc.example.dt.yaml: ufs@fd030000: freq-table-hz: 'anyOf' conditional failed, one must be fixed:
[[0, 0], [0, 0]] is too long
[0, 0] is too long
From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/property-units.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1601674
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
Use common UFS bindings in Samsung Exynos UFS to cover generic/common
properties in DTS.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index 95ac1c18334d..c949eb617313 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -11,12 +11,11 @@ maintainers:
description: |
Each Samsung UFS host controller instance should have its own node.
- This binding define Samsung specific binding other then what is used
- in the common ufshcd bindings
- [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
-properties:
+allOf:
+ - $ref: ufs-common.yaml
+properties:
compatible:
enum:
- samsung,exynos7-ufs
@@ -47,9 +46,6 @@ properties:
- const: core_clk
- const: sclk_unipro_main
- interrupts:
- maxItems: 1
-
phys:
maxItems: 1
@@ -67,13 +63,12 @@ properties:
required:
- compatible
- reg
- - interrupts
- phys
- phy-names
- clocks
- clock-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
--
2.32.0
ref_clk clock in UFS node is already there with a <0 0> frequency, which
matches other DTSI files.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index d242bab69c2e..02589b3beb7c 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1916,7 +1916,6 @@ ufs_mem_hc: ufshc@1d84000 {
iommus = <&apps_smmu 0xe0 0x0>;
clock-names =
- "ref_clk",
"core_clk",
"bus_aggr_clk",
"iface_clk",
@@ -1926,7 +1925,6 @@ ufs_mem_hc: ufshc@1d84000 {
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -1936,7 +1934,6 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
- <75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
--
2.32.0
The property vddp-ref-clk-max-microamp (for VDDP ref clk supply which is
l25 regulator) is not documented in MSM8996 UFS PHY bindings
(qcom,msm8996-qmp-ufs-phy). It is mentioned in the other UFS PHY
bindings for qcom,msm8996-ufs-phy-qmp-14nm.
The MSM8996-based Xiaomi devices configure l25 regulator in a
conflicting way:
1. with maximum 100 uAmp for VDDP ref clk supply of UFS PHY,
2. with maximum 450 mAmp for VCCQ supply of UFS.
Since the vddp-ref-clk-max-microamp property is basically not
documented for that UFS PHY and has a conflicting values, drop it
entirely as it looks like not tested and not used ever.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
index 7a9fcbe9bb31..3ade756e1cd9 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
@@ -341,7 +341,6 @@ &ufsphy {
vdda-pll-max-microamp = <9440>;
vddp-ref-clk-supply = <&vreg_l25a_1p2>;
- vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
};
--
2.32.0
On 07/03/2022 04:24, Rob Herring wrote:
> On Sun, 06 Mar 2022 12:11:16 +0100, Krzysztof Kozlowski wrote:
>> Convert the Cadence Universal Flash Storage (UFS) Controlle to DT schema
>> format.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> Reviewed-by: Rob Herring <[email protected]>
>> ---
>> .../devicetree/bindings/ufs/cdns,ufshc.txt | 32 ---------
>> .../devicetree/bindings/ufs/cdns,ufshc.yaml | 68 +++++++++++++++++++
>> .../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 7 +-
>> 3 files changed, 71 insertions(+), 36 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
>> create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
>>
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/ufs/cdns,ufshc.example.dt.yaml: ufs@fd030000: freq-table-hz: 'anyOf' conditional failed, one must be fixed:
> [[0, 0], [0, 0]] is too long
> [0, 0] is too long
> From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/property-units.yaml
>
This will be fixed with my dtschema patch:
https://github.com/devicetree-org/dt-schema/pull/69
Best regards,
Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Sunday, March 6, 2022 4:41 PM
>To: Alim Akhtar <[email protected]>; Avri Altman
><[email protected]>; Rob Herring <[email protected]>; Krzysztof
>Kozlowski <[email protected]>; Andy Gross
><[email protected]>; Bjorn Andersson <[email protected]>; Wei
>Xu <[email protected]>; Matthias Brugger <[email protected]>;
>Jan Kotas <[email protected]>; Li Wei <[email protected]>; Stanley Chu
><[email protected]>; Vignesh Raghavendra <[email protected]>;
>[email protected]; [email protected]; linux-
>[email protected]; [email protected]; linux-arm-
>[email protected]; [email protected]; linux-
>[email protected]
>Cc: Rob Herring <[email protected]>
>Subject: [PATCH v3 02/12] dt-bindings: ufs: samsung,exynos-ufs: use common
>bindings
>
>Use common UFS bindings in Samsung Exynos UFS to cover generic/common
>properties in DTS.
>
>Signed-off-by: Krzysztof Kozlowski <[email protected]>
>Reviewed-by: Rob Herring <[email protected]>
>---
Reviewed-by: Alim Akhtar <[email protected]>
> .../devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
>diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-
>ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-
>ufs.yaml
>index 95ac1c18334d..c949eb617313 100644
>--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
>+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
>@@ -11,12 +11,11 @@ maintainers:
>
> description: |
> Each Samsung UFS host controller instance should have its own node.
>- This binding define Samsung specific binding other then what is used
>- in the common ufshcd bindings
>- [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
>
>-properties:
>+allOf:
>+ - $ref: ufs-common.yaml
>
>+properties:
> compatible:
> enum:
> - samsung,exynos7-ufs
>@@ -47,9 +46,6 @@ properties:
> - const: core_clk
> - const: sclk_unipro_main
>
>- interrupts:
>- maxItems: 1
>-
> phys:
> maxItems: 1
>
>@@ -67,13 +63,12 @@ properties:
> required:
> - compatible
> - reg
>- - interrupts
> - phys
> - phy-names
> - clocks
> - clock-names
>
>-additionalProperties: false
>+unevaluatedProperties: false
>
> examples:
> - |
>--
>2.32.0
On Sun, Mar 06, 2022 at 12:11:13PM +0100, Krzysztof Kozlowski wrote:
> Hi,
>
> Not tested on hardware, so please kindly test.
> Bindings maintainers might need checking - taken from git log.
>
> Changes since v2
> ================
> 1. Do not deprecate freq-table-hz, but instead update dtschema to accept
> uint32-matrix. See:
> https://github.com/devicetree-org/dt-schema/pull/69
> 2. Drop patches and changes related to freq-table-hz -> freq-table conversion.
> 3. Add tags.
> 4. Change maintainer of qcom,ufs.
>
> Changes since v1
> ================
> 1. Make freq-table as matrix of tuples (Nishanth).
> 2. New patches: convert all bindings and fix up DTS files.
> 3. Several minor fixes in UFS bindings.
>
> Dependencies
> ============
> None dependencies. The DTS patches can go independently via respective
> maintainers. The dt-bindings patches could go via UFS tree.
>
> Best regards,
> Krzysztof
>
> Krzysztof Kozlowski (12):
> dt-bindings: ufs: add common platform bindings
> dt-bindings: ufs: samsung,exynos-ufs: use common bindings
> dt-bindings: ufs: cdns,ufshc: convert to dtschema
> dt-bindings: ufs: drop unused/old ufs-qcom PHY bindings
> dt-bindings: ufs: qcom,ufs: convert to dtschema
> dt-bindings: ufs: hisilicon,ufs: convert to dtschema
> dt-bindings: ufs: mediatek,ufs: convert to dtschema
> dt-bindings: ufs: snps,tc-dwc-g210: convert to dtschema
Patches 1-8 applied.
Rob
> arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS
> arm64: dts: qcom: msm8996: drop unsupported UFS
> vddp-ref-clk-max-microamp
> arm64: dts: qcom: msm8996: correct UFS compatible
> arm64: dts: qcom: sm8350: drop duplicated ref_clk in UFS
>
> .../devicetree/bindings/ufs/cdns,ufshc.txt | 32 ---
> .../devicetree/bindings/ufs/cdns,ufshc.yaml | 68 +++++
> .../bindings/ufs/hisilicon,ufs.yaml | 90 +++++++
> .../devicetree/bindings/ufs/mediatek,ufs.yaml | 67 +++++
> .../devicetree/bindings/ufs/qcom,ufs.yaml | 242 ++++++++++++++++++
> .../bindings/ufs/samsung,exynos-ufs.yaml | 13 +-
> .../bindings/ufs/snps,tc-dwc-g210.yaml | 51 ++++
> .../bindings/ufs/tc-dwc-g210-pltfrm.txt | 26 --
> .../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 7 +-
> .../devicetree/bindings/ufs/ufs-common.yaml | 82 ++++++
> .../devicetree/bindings/ufs/ufs-hisi.txt | 42 ---
> .../devicetree/bindings/ufs/ufs-mediatek.txt | 45 ----
> .../devicetree/bindings/ufs/ufs-qcom.txt | 63 -----
> .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 90 -------
> MAINTAINERS | 1 +
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 +-
> arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 +-
> .../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 1 -
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 +-
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 -
> 20 files changed, 614 insertions(+), 320 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
> create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
> create mode 100644 Documentation/devicetree/bindings/ufs/hisilicon,ufs.yaml
> create mode 100644 Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> create mode 100644 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> create mode 100644 Documentation/devicetree/bindings/ufs/snps,tc-dwc-g210.yaml
> delete mode 100644 Documentation/devicetree/bindings/ufs/tc-dwc-g210-pltfrm.txt
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-common.yaml
> delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
> delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
> delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-qcom.txt
> delete mode 100644 Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
>
> --
> 2.32.0
>
>