From: Frank Wunderlich <[email protected]>
This Series converts the binding for ahci-platform to yaml and adds
sata nodes to rockchip rk356x device trees.
---
v6:
- add fix for spear1340
- fix indentation of examples
- add compatible marvell,berlin2-ahci
- change maximum of ports-implemented
- add select to exclude qcom compatibles
- drop marvell,armada-380-ahci
it is not handled in the ahci-platform.c but ahci_mvebu.c
and incompatible due to missing phys/target-supply
v5:
DTS:
- drop broadcom-patch as it is already applied
- add fix for marvell
YAML:
- change subject
- drop brcm,iproc-ahci from standalone enum
- fix reg address in example 2
- move clocknames next to clocks, regnames to reg
- drop interrupts description
- drop newline from dma-coherent
- drop max-items from ports-implemented
- min2max in child phys
- fix identation for compatible and sata-common
- add additionalProperties=false for subnodes
- pipe for paragraphs and newline after title
- add maximum for ports-implemented (found only 0x1 as its value)
- add phy-names to sata-ports
v4:
YAML binding:
- fix min vs. max
- fix indention of examples
- move up sata-common.yaml
- reorder compatible
- add descriptions/maxitems
- fix compatible-structure
- fix typo in example achi vs. ahci
- add clock-names and reg-names
DTS-Patches:
- drop newline in dts
- re-add clock-names
- add soc specific compatible
- fix sata nodename in arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
v3:
- add conversion to sata-series
- fix some errors in dt_binding_check and dtbs_check
- move to unevaluated properties = false
- add power-domain to yaml
- move sata0 to rk3568.dtsi
- drop clock-names and interrupt-names
Frank Wunderlich (6):
dt-bindings: ata: ahci-platform: Convert DT bindings to yaml
arm64: dts: marvell: Fix anyOf conditional failed
ARM: dts: spear13xx: Fix sata node name
dt-bindings: ata: ahci-platform: Add power-domains property
dt-bindings: ata: ahci-platform: Add rk3568-dwc-ahci compatible
arm64: dts: rockchip: Add sata nodes to rk356x
.../devicetree/bindings/ata/ahci-platform.txt | 79 --------
.../bindings/ata/ahci-platform.yaml | 189 ++++++++++++++++++
arch/arm/boot/dts/spear1310.dtsi | 6 +-
arch/arm/boot/dts/spear1340-evb.dts | 2 +-
arch/arm/boot/dts/spear1340.dtsi | 2 +-
.../arm64/boot/dts/marvell/armada-7040-db.dts | 1 +
.../boot/dts/marvell/armada-7040-mochabin.dts | 2 +
.../marvell/armada-8040-clearfog-gt-8k.dts | 1 +
.../arm64/boot/dts/marvell/armada-8040-db.dts | 2 +
.../boot/dts/marvell/armada-8040-mcbin.dtsi | 1 +
.../dts/marvell/armada-8040-puzzle-m801.dts | 2 +
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +
arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 1 +
arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 1 +
arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 +++
17 files changed, 250 insertions(+), 84 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/ahci-platform.txt
create mode 100644 Documentation/devicetree/bindings/ata/ahci-platform.yaml
--
2.25.1
From: Frank Wunderlich <[email protected]>
Add SoC specific compatible for rk3568 ahci controller
Signed-off-by: Frank Wunderlich <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
v6:
change subject to dwc instead of dwc3
---
Documentation/devicetree/bindings/ata/ahci-platform.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
index a02f6d12773e..c146ab8e14e5 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
@@ -49,6 +49,10 @@ properties:
- marvell,berlin2-ahci
- marvell,berlin2q-ahci
- const: generic-ahci
+ - items:
+ - enum:
+ - rockchip,rk3568-dwc-ahci
+ - const: snps,dwc-ahci
- enum:
- cavium,octeon-7130-ahci
- hisilicon,hisi-ahci
--
2.25.1
From: Frank Wunderlich <[email protected]>
Create a yaml file for dtbs_check from the old txt binding.
Signed-off-by: Frank Wunderlich <[email protected]>
---
v6:
- fix indentation of examples
- add compatible marvell,berlin2-ahci
- change maximum of ports-implemented
- add select to exclude qcom compatibles
- drop marvell,armada-380-ahci
it is not handled in the ahci-platform.c but ahci_mvebu.c
and incompatible due to missing phys/target-supply
v5:
- change subject
- drop brcm,iproc-ahci from standalone enum
- fix reg address in example 2
- move clocknames next to clocks, regnames to reg
- drop interrupts description
- drop newline from dma-coherent
- drop max-items from ports-implemented
- min2max in child phys
- fix identation for compatible and sata-common
- add additionalProperties=false for subnodes
- pipe for paragraphs and newline after title
- add maximum for ports-implemented (found only 0x1 as its value)
- add phy-names to sata-ports
v4:
- fix min vs. max
- fix indention of examples
- move up sata-common.yaml
- reorder compatible
- add descriptions/maxitems
- fix compatible-structure
- fix typo in example achi vs. ahci
- add clock-names and reg-names
- fix ns2 errors in separate patch
v3:
- add conversion to sata-series
- fix some errors in dt_binding_check and dtbs_check
- move to unevaluated properties = false
arch/arm/boot/dts/qcom-apq8064.dtsi had caused errors for clock-count
---
have not added reviewed-by from v5 because i have changed patch too much
---
.../devicetree/bindings/ata/ahci-platform.txt | 79 --------
.../bindings/ata/ahci-platform.yaml | 182 ++++++++++++++++++
2 files changed, 182 insertions(+), 79 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/ahci-platform.txt
create mode 100644 Documentation/devicetree/bindings/ata/ahci-platform.yaml
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
deleted file mode 100644
index 77091a277642..000000000000
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ /dev/null
@@ -1,79 +0,0 @@
-* AHCI SATA Controller
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA controller should have its own node.
-
-It is possible, but not required, to represent each port as a sub-node.
-It allows to enable each port independently when dealing with multiple
-PHYs.
-
-Required properties:
-- compatible : compatible string, one of:
- - "brcm,iproc-ahci"
- - "hisilicon,hisi-ahci"
- - "cavium,octeon-7130-ahci"
- - "ibm,476gtr-ahci"
- - "marvell,armada-380-ahci"
- - "marvell,armada-3700-ahci"
- - "snps,dwc-ahci"
- - "snps,spear-ahci"
- - "generic-ahci"
-- interrupts : <interrupt mapping for SATA IRQ>
-- reg : <registers mapping>
-
-Please note that when using "generic-ahci" you must also specify a SoC specific
-compatible:
- compatible = "manufacturer,soc-model-ahci", "generic-ahci";
-
-Optional properties:
-- dma-coherent : Present if dma operations are coherent
-- clocks : a list of phandle + clock specifier pairs
-- resets : a list of phandle + reset specifier pairs
-- target-supply : regulator for SATA target power
-- phy-supply : regulator for PHY power
-- phys : reference to the SATA PHY node
-- phy-names : must be "sata-phy"
-- ahci-supply : regulator for AHCI controller
-- ports-implemented : Mask that indicates which ports that the HBA supports
- are available for software to use. Useful if PORTS_IMPL
- is not programmed by the BIOS, which is true with
- some embedded SOC's.
-
-Required properties when using sub-nodes:
-- #address-cells : number of cells to encode an address
-- #size-cells : number of cells representing the size of an address
-
-Sub-nodes required properties:
-- reg : the port number
-And at least one of the following properties:
-- phys : reference to the SATA PHY node
-- target-supply : regulator for SATA target power
-
-Examples:
- sata@ffe08000 {
- compatible = "snps,spear-ahci";
- reg = <0xffe08000 0x1000>;
- interrupts = <115>;
- };
-
-With sub-nodes:
- sata@f7e90000 {
- compatible = "marvell,berlin2q-achi", "generic-ahci";
- reg = <0xe90000 0x1000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_SATA>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata0: sata-port@0 {
- reg = <0>;
- phys = <&sata_phy 0>;
- target-supply = <®_sata0>;
- };
-
- sata1: sata-port@1 {
- reg = <1>;
- phys = <&sata_phy 1>;
- target-supply = <®_sata1>;;
- };
- };
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
new file mode 100644
index 000000000000..e71bfb04d7f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AHCI SATA Controller
+
+description: |
+ SATA nodes are defined to describe on-chip Serial ATA controllers.
+ Each SATA controller should have its own node.
+
+ It is possible, but not required, to represent each port as a sub-node.
+ It allows to enable each port independently when dealing with multiple
+ PHYs.
+
+maintainers:
+ - Hans de Goede <[email protected]>
+ - Jens Axboe <[email protected]>
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,iproc-ahci
+ - cavium,octeon-7130-ahci
+ - hisilicon,hisi-ahci
+ - ibm,476gtr-ahci
+ - marvell,armada-3700-ahci
+ - marvell,armada-8k-ahci
+ - marvell,berlin2q-ahci
+ - snps,dwc-ahci
+ - snps,spear-ahci
+ required:
+ - compatible
+
+allOf:
+ - $ref: "sata-common.yaml#"
+
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,iproc-ahci
+ - marvell,armada-8k-ahci
+ - marvell,berlin2-ahci
+ - marvell,berlin2q-ahci
+ - const: generic-ahci
+ - enum:
+ - cavium,octeon-7130-ahci
+ - hisilicon,hisi-ahci
+ - ibm,476gtr-ahci
+ - marvell,armada-3700-ahci
+ - snps,dwc-ahci
+ - snps,spear-ahci
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ maxItems: 1
+
+ clocks:
+ description:
+ Clock IDs array as required by the controller.
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ description:
+ Names of clocks corresponding to IDs in the clock property.
+ minItems: 1
+ maxItems: 3
+
+ interrupts:
+ maxItems: 1
+
+ ahci-supply:
+ description:
+ regulator for AHCI controller
+
+ dma-coherent: true
+
+ phy-supply:
+ description:
+ regulator for PHY power
+
+ phys:
+ description:
+ List of all PHYs on this controller
+ maxItems: 1
+
+ phy-names:
+ description:
+ Name specifier for the PHYs
+ maxItems: 1
+
+ ports-implemented:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: |
+ Mask that indicates which ports that the HBA supports
+ are available for software to use. Useful if PORTS_IMPL
+ is not programmed by the BIOS, which is true with
+ some embedded SoCs.
+ maximum: 0x1f
+
+ resets:
+ maxItems: 1
+
+ target-supply:
+ description:
+ regulator for SATA target power
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+patternProperties:
+ "^sata-port@[0-9a-f]+$":
+ type: object
+ additionalProperties: false
+ description:
+ Subnode with configuration of the Ports.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ maxItems: 1
+
+ target-supply:
+ description:
+ regulator for SATA target power
+
+ required:
+ - reg
+
+ anyOf:
+ - required: [ phys ]
+ - required: [ target-supply ]
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sata@ffe08000 {
+ compatible = "snps,spear-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/berlin2q.h>
+ sata@f7e90000 {
+ compatible = "marvell,berlin2q-ahci", "generic-ahci";
+ reg = <0xf7e90000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&chip CLKID_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ target-supply = <®_sata0>;
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ target-supply = <®_sata1>;
+ };
+ };
--
2.25.1
From: Frank Wunderlich <[email protected]>
Some SoC using power-domains property so add it here
Signed-off-by: Frank Wunderlich <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
changes in v5: added reviewed by
changes in v4: none
changes in v3:
- new patch
---
Documentation/devicetree/bindings/ata/ahci-platform.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
index e71bfb04d7f1..a02f6d12773e 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
@@ -108,6 +108,9 @@ properties:
some embedded SoCs.
maximum: 0x1f
+ power-domains:
+ maxItems: 1
+
resets:
maxItems: 1
--
2.25.1
From: Frank Wunderlich <[email protected]>
after converting the ahci-platform binding to yaml the following files
reporting "'anyOf' conditional failed" on
sata@540000: sata-port@0
armada-7040-db.dts
armada-8040-clearfog-gt-8k.dts
armada-8040-mcbin.dts
armada-8040-mcbin-singleshot.dts
cn9130-db.dts
cn9130-db-B.dts
cn9131-db.dts
cn9131-db-B.dts
cn9132-db.dts
cn9132-db-B.dts
the following files reporting 'anyOf' conditional failed on
sata@540000: sata-port@1
cn9132-db.dts
cn9132-db-B.dts
cn9130-crb-B.dts
'phys' is a required property
'target-supply' is a required property
From schema: Documentation/devicetree/bindings/ata/ahci-platform.yaml
This is caused by defining sata-ports incomplete in armada-cp11x.dtsi
and overriding only a subset of ports with the needed
phys/target-supply property.
Fix this by disabling the node-templates and enabling the needed nodes.
Fixes: 47cf40af64c3 ("arm64: dts: marvell: Prepare the introduction of CP115")
Signed-off-by: Frank Wunderlich <[email protected]>
---
v5: add fixes-tag
the dtsi uses a macro for the node-label defined in armada-common.dtsi
CP11X_LABEL(sata0): sata@540000 {
so i hope i catched all right nodes to be enabled...
have enabled all cpX_sata0 sata-portY childs
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 1 +
arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 1 +
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 ++
arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 1 +
arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 1 +
arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 1 +
10 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index cd326fe224ce..f8b1b46a03b3 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -215,6 +215,7 @@ &cp0_sata0 {
sata-port@1 {
phys = <&cp0_comphy3 1>;
phy-names = "cp0-sata0-1-phy";
+ status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
index f3b0d57a24a3..7529018f9b72 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
@@ -436,12 +436,14 @@ &cp0_sata0 {
sata-port@0 {
phys = <&cp0_comphy2 0>;
phy-names = "cp0-sata0-0-phy";
+ status = "okay";
};
/* M.2-2250 B-key (J39) */
sata-port@1 {
phys = <&cp0_comphy3 1>;
phy-names = "cp0-sata0-1-phy";
+ status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 8729c6467303..5bb429abb1de 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -476,6 +476,7 @@ &cp1_sata0 {
sata-port@1 {
phys = <&cp1_comphy0 1>;
phy-names = "cp1-sata0-1-phy";
+ status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index f2e8e0df8865..b33d64babcd9 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -146,10 +146,12 @@ &cp0_sata0 {
sata-port@0 {
phys = <&cp0_comphy1 0>;
phy-names = "cp0-sata0-0-phy";
+ status = "okay";
};
sata-port@1 {
phys = <&cp0_comphy3 1>;
phy-names = "cp0-sata0-1-phy";
+ status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index adbfecc678b5..2be4d67cbf16 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -246,6 +246,7 @@ &cp0_sata0 {
sata-port@1 {
phys = <&cp0_comphy5 1>;
phy-names = "cp0-sata0-1-phy";
+ status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
index dac85fa748de..03f9cc3a895f 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
@@ -409,11 +409,13 @@ &cp0_sata0 {
sata-port@0 {
phys = <&cp0_comphy2 0>;
phy-names = "cp0-sata0-0-phy";
+ status = "okay";
};
sata-port@1 {
phys = <&cp0_comphy5 1>;
phy-names = "cp0-sata0-1-phy";
+ status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 3bd2182817fb..a2cc85d2adce 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -342,10 +342,12 @@ CP11X_LABEL(sata0): sata@540000 {
sata-port@0 {
reg = <0>;
+ status = "disabled";
};
sata-port@1 {
reg = <1>;
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
index 0904cb0309ae..34194745f79e 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
@@ -28,6 +28,7 @@ sata-port@0 {
status = "okay";
/* Generic PHY, providing serdes lanes */
phys = <&cp0_comphy2 0>;
+ status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
index f995b1bcda01..e6566dac885e 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
@@ -127,6 +127,7 @@ &cp1_sata0 {
sata-port@1 {
/* Generic PHY, providing serdes lanes */
phys = <&cp1_comphy5 1>;
+ status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
index 3f1795fb4fe7..5f9614bf2a0f 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
@@ -175,6 +175,7 @@ &cp2_sata0 {
sata-port@0 {
/* Generic PHY, providing serdes lanes */
phys = <&cp2_comphy2 0>;
+ status = "okay";
};
};
--
2.25.1
From: Frank Wunderlich <[email protected]>
RK356x supports up to 3 sata controllers which were compatible with the
existing snps,dwc-ahci binding.
Signed-off-by: Frank Wunderlich <[email protected]>
---
changes in v4:
- drop newline in dts
- re-add clock-names
- add soc specific compatible
changes in v3:
- fix combphy error by moving sata0 to rk3568.dtsi
- remove clock-names and interrupt-names
changes in v2:
- added sata0 + 1, but have only tested sata2
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++++++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 ++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 5b0f528d6818..3e07d9f6a2d1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,20 @@
/ {
compatible = "rockchip,rk3568";
+ sata0: sata@fc000000 {
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfc000000 0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
+ <&cru CLK_SATA0_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&combphy0 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
pipe_phy_grf0: syscon@fdc70000 {
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0x0 0xfdc70000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..264dd030e703 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,34 @@ scmi_shmem: sram@0 {
};
};
+ sata1: sata@fc400000 {
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfc400000 0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
+ <&cru CLK_SATA1_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&combphy1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ sata2: sata@fc800000 {
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfc800000 0 0x1000>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
+ <&cru CLK_SATA2_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&combphy2 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
--
2.25.1
On Fri, 11 Mar 2022 22:03:56 +0100, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> Add SoC specific compatible for rk3568 ahci controller
>
> Signed-off-by: Frank Wunderlich <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> v6:
> change subject to dwc instead of dwc3
> ---
> Documentation/devicetree/bindings/ata/ahci-platform.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Applied, thanks!
On Fri, 11 Mar 2022 22:03:52 +0100, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> Create a yaml file for dtbs_check from the old txt binding.
>
> Signed-off-by: Frank Wunderlich <[email protected]>
> ---
>
> v6:
> - fix indentation of examples
> - add compatible marvell,berlin2-ahci
> - change maximum of ports-implemented
> - add select to exclude qcom compatibles
> - drop marvell,armada-380-ahci
> it is not handled in the ahci-platform.c but ahci_mvebu.c
> and incompatible due to missing phys/target-supply
>
> v5:
> - change subject
> - drop brcm,iproc-ahci from standalone enum
> - fix reg address in example 2
> - move clocknames next to clocks, regnames to reg
> - drop interrupts description
> - drop newline from dma-coherent
> - drop max-items from ports-implemented
> - min2max in child phys
> - fix identation for compatible and sata-common
> - add additionalProperties=false for subnodes
> - pipe for paragraphs and newline after title
> - add maximum for ports-implemented (found only 0x1 as its value)
> - add phy-names to sata-ports
>
> v4:
> - fix min vs. max
> - fix indention of examples
> - move up sata-common.yaml
> - reorder compatible
> - add descriptions/maxitems
> - fix compatible-structure
> - fix typo in example achi vs. ahci
> - add clock-names and reg-names
> - fix ns2 errors in separate patch
> v3:
> - add conversion to sata-series
> - fix some errors in dt_binding_check and dtbs_check
> - move to unevaluated properties = false
>
> arch/arm/boot/dts/qcom-apq8064.dtsi had caused errors for clock-count
> ---
>
> have not added reviewed-by from v5 because i have changed patch too much
>
> ---
> .../devicetree/bindings/ata/ahci-platform.txt | 79 --------
> .../bindings/ata/ahci-platform.yaml | 182 ++++++++++++++++++
> 2 files changed, 182 insertions(+), 79 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/ata/ahci-platform.txt
> create mode 100644 Documentation/devicetree/bindings/ata/ahci-platform.yaml
>
Applied, thanks!
On Fri, 11 Mar 2022 22:03:55 +0100, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> Some SoC using power-domains property so add it here
>
> Signed-off-by: Frank Wunderlich <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> changes in v5: added reviewed by
> changes in v4: none
> changes in v3:
> - new patch
> ---
> Documentation/devicetree/bindings/ata/ahci-platform.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Applied, thanks!
Hi Damien,
Am 12. März 2022 09:00:53 MEZ schrieb Damien Le Moal <[email protected]>:
>On 3/12/22 06:03, Frank Wunderlich wrote:
>> From: Frank Wunderlich <[email protected]>
>>
>> This Series converts the binding for ahci-platform to yaml and adds
>> sata nodes to rockchip rk356x device trees.
>
>Rob,
>
>I saw you took patches 1, 4 and 5. What about the others ? Are you
>taking them or should I take them through the ATA tree ?
Imho the dts "fixes" should be tested by someone having such board or at least be reviewed.
I only fixed the binding warnings,but i'm not sure it breaks hardware as i cannot test function.
Afaik last part should go through Heikos tree.
regards Frank
On 3/12/22 06:03, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> This Series converts the binding for ahci-platform to yaml and adds
> sata nodes to rockchip rk356x device trees.
Rob,
I saw you took patches 1, 4 and 5. What about the others ? Are you
taking them or should I take them through the ATA tree ?
--
Damien Le Moal
Western Digital Research
On Sat, Mar 12, 2022 at 05:00:53PM +0900, Damien Le Moal wrote:
> On 3/12/22 06:03, Frank Wunderlich wrote:
> > From: Frank Wunderlich <[email protected]>
> >
> > This Series converts the binding for ahci-platform to yaml and adds
> > sata nodes to rockchip rk356x device trees.
>
> Rob,
>
> I saw you took patches 1, 4 and 5. What about the others ? Are you
> taking them or should I take them through the ATA tree ?
It's all dts changes, so they should go via the sub-arch trees.
Rob
On Fri, 11 Mar 2022 22:03:51 +0100, Frank Wunderlich wrote:
> This Series converts the binding for ahci-platform to yaml and adds
> sata nodes to rockchip rk356x device trees.
Applied, thanks!
[6/6] arm64: dts: rockchip: Add sata nodes to rk356x
commit: b2e5612f6ea23c87397e50f8d976cd8c95e3ed17
Best regards,
--
Heiko Stuebner <[email protected]>