Convert the pinctrl ocelot binding to the new YAML format. Pin
configuration nodes should have a "-pins" postfix. But unfortunately,
there are many device trees which don't follow this. First rename
all these nodes and then convert the binding to the YAML format so
that the validation will pass.
Because there were no maintainers before and there is none in
MAINTAINERS I added Alexandre Belloni and Lars Povlsen, juding by
the commits - to the binding as maintainers. Please tell me if you
disagree.
Michael Walle (8):
MIPS: mscc: jaguar2: fix pinctrl nodes
MIPS: mscc: ocelot: fix MIIM1 pinctrl node name
MIPS: mscc: ocelot: fix PHY interrupt pinctrl node name
MIPS: mscc: ocelot: fix load/save GPIO pinctrl name
MIPS: mscc: serval: fix pinctrl node names
arm64: dts: sparx5: fix pinctrl node names
ARM: dts: lan9662-pcb8291: fix pinctrl node name
dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format
.../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ---------
.../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 94 +++++++++++++++++++
arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
.../dts/microchip/sparx5_pcb134_board.dtsi | 26 ++---
.../dts/microchip/sparx5_pcb135_board.dtsi | 10 +-
arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 10 +-
arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 10 +-
arch/mips/boot/dts/mscc/jaguar2_pcb118.dts | 6 +-
arch/mips/boot/dts/mscc/ocelot.dtsi | 4 +-
arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 6 +-
arch/mips/boot/dts/mscc/serval_common.dtsi | 14 +--
11 files changed, 138 insertions(+), 86 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
--
2.30.2
The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.
Fixes: f84778f7d8c3 ("MIPS: mscc: Add jaguar2 support")
Signed-off-by: Michael Walle <[email protected]>
---
arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 10 +++++-----
arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 10 +++++-----
arch/mips/boot/dts/mscc/jaguar2_pcb118.dts | 6 +++---
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
index d80cd6842b2a..0ea7bc5b5746 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
@@ -180,27 +180,27 @@ synce_builtin_pins: synce-builtin-pins {
pins = "GPIO_49";
function = "si";
};
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
- i2cmux_2: i2cmux-2 {
+ i2cmux_2: i2cmux-2-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
- i2cmux_3: i2cmux-3 {
+ i2cmux_3: i2cmux-3-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
index 813c5e16013c..05d8c6a96dc4 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
@@ -79,27 +79,27 @@ cpld_fifo_pins: synce-builtin-pins {
};
&gpio {
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_18";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
- i2cmux_2: i2cmux-2 {
+ i2cmux_2: i2cmux-2-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
- i2cmux_3: i2cmux-3 {
+ i2cmux_3: i2cmux-3-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
index 27c644f2d17f..cf2cf591a211 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
@@ -39,17 +39,17 @@ i2c151: i2c@1 {
};
&gpio {
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_16";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_16";
function = "twi_scl_m";
output-high;
--
2.30.2
The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.
Fixes: ("arm64: dts: sparx5: Add i2c devices, i2c muxes")
Signed-off-by: Michael Walle <[email protected]>
---
.../dts/microchip/sparx5_pcb134_board.dtsi | 26 +++++++++----------
.../dts/microchip/sparx5_pcb135_board.dtsi | 10 +++----
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 33faf1f3264f..6f488e774215 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -325,69 +325,69 @@ &sgpio2 {
};
&gpio {
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
"GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
"GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_16";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
- i2cmux_2: i2cmux-2 {
+ i2cmux_2: i2cmux-2-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
- i2cmux_3: i2cmux-3 {
+ i2cmux_3: i2cmux-3-pins {
pins = "GPIO_19";
function = "twi_scl_m";
output-high;
};
- i2cmux_4: i2cmux-4 {
+ i2cmux_4: i2cmux-4-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
- i2cmux_5: i2cmux-5 {
+ i2cmux_5: i2cmux-5-pins {
pins = "GPIO_22";
function = "twi_scl_m";
output-high;
};
- i2cmux_6: i2cmux-6 {
+ i2cmux_6: i2cmux-6-pins {
pins = "GPIO_36";
function = "twi_scl_m";
output-high;
};
- i2cmux_7: i2cmux-7 {
+ i2cmux_7: i2cmux-7-pins {
pins = "GPIO_35";
function = "twi_scl_m";
output-high;
};
- i2cmux_8: i2cmux-8 {
+ i2cmux_8: i2cmux-8-pins {
pins = "GPIO_50";
function = "twi_scl_m";
output-high;
};
- i2cmux_9: i2cmux-9 {
+ i2cmux_9: i2cmux-9-pins {
pins = "GPIO_51";
function = "twi_scl_m";
output-high;
};
- i2cmux_10: i2cmux-10 {
+ i2cmux_10: i2cmux-10-pins {
pins = "GPIO_56";
function = "twi_scl_m";
output-high;
};
- i2cmux_11: i2cmux-11 {
+ i2cmux_11: i2cmux-11-pins {
pins = "GPIO_57";
function = "twi_scl_m";
output-high;
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index ef96e6d8c6b3..d9e519bfbf68 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -59,28 +59,28 @@ led@7 {
};
&gpio {
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_35", "GPIO_36",
"GPIO_50", "GPIO_51";
function = "twi_scl_m";
output-low;
};
- i2cmux_s29: i2cmux-0 {
+ i2cmux_s29: i2cmux-0-pins {
pins = "GPIO_35";
function = "twi_scl_m";
output-high;
};
- i2cmux_s30: i2cmux-1 {
+ i2cmux_s30: i2cmux-1-pins {
pins = "GPIO_36";
function = "twi_scl_m";
output-high;
};
- i2cmux_s31: i2cmux-2 {
+ i2cmux_s31: i2cmux-2-pins {
pins = "GPIO_50";
function = "twi_scl_m";
output-high;
};
- i2cmux_s32: i2cmux-3 {
+ i2cmux_s32: i2cmux-3-pins {
pins = "GPIO_51";
function = "twi_scl_m";
output-high;
--
2.30.2
The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.
Fixes: a0553e01f85b ("MIPS: mscc: ocelot: add MIIM1 bus")
Signed-off-by: Michael Walle <[email protected]>
---
arch/mips/boot/dts/mscc/ocelot.dtsi | 4 ++--
arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index e51db651af13..cfc219a72bdd 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -225,7 +225,7 @@ uart2_pins: uart2-pins {
function = "uart2";
};
- miim1: miim1 {
+ miim1_pins: miim1-pins {
pins = "GPIO_14", "GPIO_15";
function = "miim";
};
@@ -261,7 +261,7 @@ mdio1: mdio@10700c0 {
reg = <0x10700c0 0x24>;
interrupts = <15>;
pinctrl-names = "default";
- pinctrl-0 = <&miim1>;
+ pinctrl-0 = <&miim1_pins>;
status = "disabled";
};
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index bd240690cb37..9d6b5717befb 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -40,7 +40,7 @@ &mdio0 {
&mdio1 {
status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
+ pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
phy7: ethernet-phy@0 {
reg = <0>;
--
2.30.2