This series adds support for UFS on SM6350 which is used for internal
storage.
Luca Weiss (6):
scsi: ufs: dt-bindings: Add SM6350 compatible string
dt-bindings: phy: qcom,qmp: Add SM6350 UFS PHY bindings
phy: qcom-qmp: Add SM6350 UFS PHY support
pinctrl: qcom: sm6350: fix order of UFS & SDC pins
arm64: dts: qcom: sm6350: Add UFS nodes
arm64: dts: qcom: sm7225-fairphone-fp4: Enable UFS
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
.../devicetree/bindings/ufs/qcom,ufs.yaml | 1 +
arch/arm64/boot/dts/qcom/sm6350.dtsi | 79 +++++++++++++++++++
.../boot/dts/qcom/sm7225-fairphone-fp4.dts | 18 +++++
drivers/phy/qualcomm/phy-qcom-qmp.c | 3 +
drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++--
6 files changed, 110 insertions(+), 8 deletions(-)
--
2.35.1
Document the compatible for the UFS found on SM6350.
Signed-off-by: Luca Weiss <[email protected]>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 5b3a2157f7e5..d17db2cdf3c2 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,msm8996-ufshc
- qcom,msm8998-ufshc
- qcom,sdm845-ufshc
+ - qcom,sm6350-ufshc
- qcom,sm8150-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
--
2.35.1
Document the compatible string for the UFS PHY found in SM6350.
Signed-off-by: Luca Weiss <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index e20d9b087bb8..934aa9101ddd 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -39,6 +39,7 @@ properties:
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sm6115-qmp-ufs-phy
+ - qcom,sm6350-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
--
2.35.1
On 18/03/2022 19:30, Luca Weiss wrote:
> Document the compatible string for the UFS PHY found in SM6350.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> index e20d9b087bb8..934aa9101ddd 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> @@ -39,6 +39,7 @@ properties:
> - qcom,sdm845-qmp-usb3-phy
> - qcom,sdm845-qmp-usb3-uni-phy
> - qcom,sm6115-qmp-ufs-phy
> + - qcom,sm6350-qmp-ufs-phy
Please also add constraints to clocks, resets and any other necessary
properties in allOf:if:then section.
Best regards,
Krzysztof
The SM6350 UFS PHY is compatible with the one from SDM845. Add a
compatible for that.
Signed-off-by: Luca Weiss <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index b144ae1f729a..1628275265b5 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -6007,6 +6007,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
}, {
.compatible = "qcom,sm6115-qmp-ufs-phy",
.data = &sm6115_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sm6350-qmp-ufs-phy",
+ .data = &sdm845_ufsphy_cfg,
}, {
.compatible = "qcom,sm8150-qmp-ufs-phy",
.data = &sm8150_ufsphy_cfg,
--
2.35.1
On 19/03/2022 15:38, Krzysztof Kozlowski wrote:
> On 18/03/2022 19:29, Luca Weiss wrote:
>> Document the compatible for the UFS found on SM6350.
>>
>> Signed-off-by: Luca Weiss <[email protected]>
>> ---
>> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
No, I revoke it. You also missed the constraints in if:then.
Best regards,
Krzysztof
In other places the SDC and UFS pins have been swapped but this was
missed in the PINCTRL_PIN definitions. Fix that.
Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver")
Signed-off-by: Luca Weiss <[email protected]>
---
drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c
index 4d37b817b232..a91a86628f2f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6350.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c
@@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = {
PINCTRL_PIN(153, "GPIO_153"),
PINCTRL_PIN(154, "GPIO_154"),
PINCTRL_PIN(155, "GPIO_155"),
- PINCTRL_PIN(156, "SDC1_RCLK"),
- PINCTRL_PIN(157, "SDC1_CLK"),
- PINCTRL_PIN(158, "SDC1_CMD"),
- PINCTRL_PIN(159, "SDC1_DATA"),
- PINCTRL_PIN(160, "SDC2_CLK"),
- PINCTRL_PIN(161, "SDC2_CMD"),
- PINCTRL_PIN(162, "SDC2_DATA"),
- PINCTRL_PIN(163, "UFS_RESET"),
+ PINCTRL_PIN(156, "UFS_RESET"),
+ PINCTRL_PIN(157, "SDC1_RCLK"),
+ PINCTRL_PIN(158, "SDC1_CLK"),
+ PINCTRL_PIN(159, "SDC1_CMD"),
+ PINCTRL_PIN(160, "SDC1_DATA"),
+ PINCTRL_PIN(161, "SDC2_CLK"),
+ PINCTRL_PIN(162, "SDC2_CMD"),
+ PINCTRL_PIN(163, "SDC2_DATA"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \
--
2.35.1
Add the necessary nodes for UFS and its PHY.
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 79 ++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index d7c9edff19f7..c5c93b6bcd2a 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -541,6 +541,85 @@ uart2: serial@98c000 {
};
};
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>,
+ <0 0x01d90000 0 0x8000>;
+ reg-names = "std", "ice";
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ iommus = <&apps_smmu 0x80 0x0>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&rpmhcc RPMH_QLINK_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sm6350-qmp-ufs-phy";
+ reg = <0 0x01d87000 0 0x18c>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clock-names = "ref",
+ "ref_aux";
+ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ status = "disabled";
+
+ ufs_mem_phy_lanes: phy@1d87400 {
+ reg = <0 0x01d87400 0 0x128>,
+ <0 0x01d87600 0 0x1fc>,
+ <0 0x01d87c00 0 0x1dc>,
+ <0 0x01d87800 0 0x128>,
+ <0 0x01d87a00 0 0x1fc>;
+ #phy-cells = <0>;
+ };
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
--
2.35.1
>-----Original Message-----
>From: Luca Weiss [mailto:[email protected]]
>Sent: Saturday, March 19, 2022 12:00 AM
>To: [email protected]
>Cc: ~postmarketos/[email protected]; [email protected];
>Luca Weiss <[email protected]>; Andy Gross <[email protected]>;
>Bjorn Andersson <[email protected]>; Alim Akhtar
><[email protected]>; Avri Altman <[email protected]>; Rob
>Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>;
>[email protected]; [email protected]; linux-
>[email protected]
>Subject: [PATCH 1/6] scsi: ufs: dt-bindings: Add SM6350 compatible string
>
>Document the compatible for the UFS found on SM6350.
>
>Signed-off-by: Luca Weiss <[email protected]>
>---
> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>index 5b3a2157f7e5..d17db2cdf3c2 100644
>--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>@@ -27,6 +27,7 @@ properties:
> - qcom,msm8996-ufshc
> - qcom,msm8998-ufshc
> - qcom,sdm845-ufshc
>+ - qcom,sm6350-ufshc
You need to update "if:then" below as well, as this SoC is different than
other in the series
> - qcom,sm8150-ufshc
> - qcom,sm8250-ufshc
> - qcom,sm8350-ufshc
>--
>2.35.1
On 18/03/2022 19:29, Luca Weiss wrote:
> Document the compatible for the UFS found on SM6350.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Fri, Mar 18, 2022 at 7:30 PM Luca Weiss <[email protected]> wrote:
> In other places the SDC and UFS pins have been swapped but this was
> missed in the PINCTRL_PIN definitions. Fix that.
>
> Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver")
> Signed-off-by: Luca Weiss <[email protected]>
Patch applied for fixes.
Yours,
Linus Walleij