2022-03-19 15:31:09

by Mike Travis

Subject: [PATCH v3 2/3] x86/platform/uv: Update TSC sync state for UV5

Update TSC to not check TSC sync state for uv5+ as it is not available.
It is assumed that TSC will always be in sync for multiple chassis and
will pass the tests for the kernel to accept it as the clocksource.
To disable this check use the kernel start options tsc=reliable
clocksource=tsc.

Signed-off-by: Mike Travis <[email protected]>
Reviewed-by: Dimitri Sivanich <[email protected]>
Reviewed-by: Steve Wahl <[email protected]>
---
v2: Update patch description to be more explanatory.
---
arch/x86/kernel/apic/x2apic_uv_x.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index f5a48e66e4f5..387d6533549a 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -199,10 +199,16 @@ static void __init uv_tsc_check_sync(void)
int mmr_shift;
char *state;

- /* Different returns from different UV BIOS versions */
+ /* UV5+, sync state from bios not available, assumed valid */
+ if (!is_uv(UV2|UV3|UV4)) {
+ pr_debug("UV: TSC sync state for UV5+ assumed valid\n");
+ mark_tsc_async_resets("UV5+");
+ return;
+ }
+
+ /* UV2,3,4, UV BIOS TSC sync state available */
mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
- mmr_shift =
- is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
+ mmr_shift = is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;

/* Check if TSC is valid for all sockets */
--
2.26.2

2022-04-05 03:01:00

by tip-bot2 for Dhananjay Ugwekar

Subject: [tip: x86/platform] x86/platform/uv: Update TSC sync state for UV5

The following commit has been merged into the x86/platform branch of tip:

Commit-ID: 4395de040d24b40fb3cd7fb4f0b013748abe0a72
Gitweb: https://git.kernel.org/tip/4395de040d24b40fb3cd7fb4f0b013748abe0a72
Author: Mike Travis <[email protected]>
AuthorDate: Fri, 18 Mar 2022 17:43:03 -05:00
Committer: Borislav Petkov <[email protected]>
CommitterDate: Mon, 04 Apr 2022 20:21:44 +02:00

x86/platform/uv: Update TSC sync state for UV5

Update TSC to not check TSC sync state for uv5+ as it is not available.
It is assumed that TSC will always be in sync for multiple chassis and
will pass the tests for the kernel to accept it as the clocksource.
To disable this check use the kernel start options tsc=reliable
clocksource=tsc.

Signed-off-by: Mike Travis <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
Reviewed-by: Dimitri Sivanich <[email protected]>
Reviewed-by: Steve Wahl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
arch/x86/kernel/apic/x2apic_uv_x.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index f5a48e6..387d653 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -199,10 +199,16 @@ static void __init uv_tsc_check_sync(void)
int mmr_shift;
char *state;

- /* Different returns from different UV BIOS versions */
+ /* UV5+, sync state from bios not available, assumed valid */
+ if (!is_uv(UV2|UV3|UV4)) {
+ pr_debug("UV: TSC sync state for UV5+ assumed valid\n");
+ mark_tsc_async_resets("UV5+");
+ return;
+ }
+
+ /* UV2,3,4, UV BIOS TSC sync state available */
mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
- mmr_shift =
- is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
+ mmr_shift = is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;

/* Check if TSC is valid for all sockets */