2022-03-28 22:14:16

by Deucher, Alexander

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Subject: [PATCH V3 2/2] Documentation: x86: Clarify Intel IOMMU documentation

Based on feedback from Robin on the initial AMD IOMMU
documentation, fix up the Intel documentation to
clarify IOMMU vs device and modern DMA API.

Signed-off-by: Alex Deucher <[email protected]>
---

V2: Fix spelling error in commit message
Rework ACPI section as suggested by Dave Hansen

Documentation/x86/intel-iommu.rst | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/Documentation/x86/intel-iommu.rst b/Documentation/x86/intel-iommu.rst
index 4d3391c7bd3f..17d8497e506b 100644
--- a/Documentation/x86/intel-iommu.rst
+++ b/Documentation/x86/intel-iommu.rst
@@ -19,9 +19,8 @@ Some Keywords
Basic stuff
-----------

-ACPI enumerates and lists the different DMA engines in the platform, and
-device scope relationships between PCI devices and which DMA engine controls
-them.
+ACPI enumerates both the IOMMUs in the platform and which IOMMU
+controls a specific PCI device.

What is RMRR?
-------------
@@ -36,9 +35,9 @@ unity mappings for these regions for these devices to access these regions.
How is IOVA generated?
----------------------

-Well behaved drivers call pci_map_*() calls before sending command to device
+Well behaved drivers call dma_map_*() calls before sending command to device
that needs to perform DMA. Once DMA is completed and mapping is no longer
-required, device performs a pci_unmap_*() calls to unmap the region.
+required, device performs a dma_unmap_*() calls to unmap the region.

The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
device has its own domain (hence protection). Devices under p2p bridges
@@ -68,7 +67,7 @@ address from PCI MMIO ranges so they are not allocated for IOVA addresses.

Fault reporting
---------------
-When errors are reported, the DMA engine signals via an interrupt. The fault
+When errors are reported, the IOMMU signals via an interrupt. The fault
reason and device that caused it with fault reason is printed on console.

See below for sample.
--
2.35.1


2022-03-29 08:51:33

by Bagas Sanjaya

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Subject: Re: [PATCH V3 2/2] Documentation: x86: Clarify Intel IOMMU documentation

On 29/03/22 00.28, Alex Deucher wrote:
> Based on feedback from Robin on the initial AMD IOMMU
> documentation, fix up the Intel documentation to
> clarify IOMMU vs device and modern DMA API.
>

Maybe we can squash into [1/2]?

--
An old man doll... just what I always wanted! - Clara