Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem (cluster).
Signed-off-by: Tanmay Shah <[email protected]>
---
Changes in v4:
- Add memory-region, mboxes and mbox-names properties in example
Changes in v3:
- None
.../bindings/remoteproc/xlnx,r5f-rproc.yaml | 145 ++++++++++++++++++
include/dt-bindings/power/xlnx-zynqmp-power.h | 6 +
2 files changed, 151 insertions(+)
create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
new file mode 100644
index 000000000000..c1f99e17b4b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx R5F processor subsystem
+
+maintainers:
+ - Ben Levinsky <[email protected]>
+ - Tanmay Shah <[email protected]>
+
+description: |
+ The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
+ real-time processing based on the Cortex-R5F processor core from ARM.
+ The Cortex-R5F processor implements the Arm v7-R architecture and includes a
+ floating-point unit that implements the Arm VFPv3 instruction set.
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-r5fss
+
+ xlnx,cluster-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The RPU MPCore can operate in split mode(Dual-processor performance), Safety
+ lock-step mode(Both RPU cores execute the same code in lock-step,
+ clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
+ core 1 runs normally). The processor does not support dynamic configuration.
+ Switching between modes is only permitted immediately after a processor reset.
+ If set to 1 then lockstep mode and if 0 then split mode.
+ If set to 2 then single CPU mode. When not defined, default will be lockstep mode.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ reg:
+ items:
+ - description: RPU subsystem status and control registers
+
+patternProperties:
+ "^r5f-[a-f0-9]+$":
+ type: object
+ description: |
+ The RPU is located in the Low Power Domain of the Processor Subsystem.
+ Each processor includes separate L1 instruction and data caches and
+ tightly coupled memories (TCM). System memory is cacheable, but the TCM
+ memory space is non-cacheable.
+
+ Each RPU contains one 64KB memory and two 32KB memories that
+ are accessed via the TCM A and B port interfaces, for a total of 128KB
+ per processor. In lock-step mode, the processor has access to 256KB of
+ TCM memory.
+
+ properties:
+ compatible:
+ const: xlnx,zynqmp-r5f
+
+ power-domains:
+ description: |
+ phandle to a PM domain provider node and an args specifier containing
+ the r5f0 and r5f1 node id value.
+
+ reg:
+ items:
+ - description: RPU0 and RPU1 control and status registers
+
+ mboxes:
+ items:
+ - description: |
+ Bi-directional channel to send data to RPU and receive ack from RPU.
+ Request and response message buffers are available and each buffer is 32 bytes.
+ - description: |
+ Bi-directional channel to receive data from RPU and send ack from RPU.
+ Request and response message buffers are available and each buffer is 32 bytes.
+ minItems: 1
+
+ mbox-names:
+ items:
+ - const: tx
+ - const: rx
+ minItems: 1
+
+ sram:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ description: |
+ phandles to one or more reserved on-chip SRAM regions. Other than TCM,
+ the RPU can execute instructions and access data from, the OCM memory,
+ the main DDR memory, and other system memories.
+
+ The regions should be defined as child nodes of the respective SRAM
+ node, and should be defined as per the generic bindings in,
+ Documentation/devicetree/bindings/sram/sram.yaml
+
+ memory-region:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandles to the reserved memory regions associated with the
+ remoteproc device. This is variable and describes the memories shared with
+ the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
+ vrings, ...). This reserved memory region will be allocated on DDR memory.
+ See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+
+ required:
+ - compatible
+ - power-domains
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ r5fss: r5fss@ff9a0000 {
+ compatible = "xlnx,zynqmp-r5fss";
+ xlnx,cluster-mode = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xff9a0000 0x228>;
+
+ r5f-0 {
+ compatible = "xlnx,zynqmp-r5f";
+ power-domains = <&zynqmp_firmware 0x7>;
+ memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
+ mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
+ mbox-names = "tx", "rx";
+ };
+
+ r5f-1 {
+ compatible = "xlnx,zynqmp-r5f";
+ power-domains = <&zynqmp_firmware 0x8>;
+ memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
+ mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+...
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
index 0d9a412fd5e0..618024cbb20d 100644
--- a/include/dt-bindings/power/xlnx-zynqmp-power.h
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -6,6 +6,12 @@
#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
#define _DT_BINDINGS_ZYNQMP_POWER_H
+#define PD_RPU_0 7
+#define PD_RPU_1 8
+#define PD_R5_0_ATCM 15
+#define PD_R5_0_BTCM 16
+#define PD_R5_1_ATCM 17
+#define PD_R5_1_BTCM 18
#define PD_USB_0 22
#define PD_USB_1 23
#define PD_TTC_0 24
--
2.25.1
On Wed, Apr 20, 2022 at 12:44:47AM -0700, Tanmay Shah wrote:
> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem (cluster).
>
> Signed-off-by: Tanmay Shah <[email protected]>
> ---
>
> Changes in v4:
> - Add memory-region, mboxes and mbox-names properties in example
>
> Changes in v3:
> - None
>
> .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 145 ++++++++++++++++++
> include/dt-bindings/power/xlnx-zynqmp-power.h | 6 +
> 2 files changed, 151 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> new file mode 100644
> index 000000000000..c1f99e17b4b2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> @@ -0,0 +1,145 @@
> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx R5F processor subsystem
> +
> +maintainers:
> + - Ben Levinsky <[email protected]>
> + - Tanmay Shah <[email protected]>
> +
> +description: |
> + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
> + real-time processing based on the Cortex-R5F processor core from ARM.
> + The Cortex-R5F processor implements the Arm v7-R architecture and includes a
> + floating-point unit that implements the Arm VFPv3 instruction set.
> +
> +properties:
> + compatible:
> + const: xlnx,zynqmp-r5fss
> +
> + xlnx,cluster-mode:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + The RPU MPCore can operate in split mode(Dual-processor performance), Safety
> + lock-step mode(Both RPU cores execute the same code in lock-step,
> + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
> + core 1 runs normally). The processor does not support dynamic configuration.
> + Switching between modes is only permitted immediately after a processor reset.
> + If set to 1 then lockstep mode and if 0 then split mode.
> + If set to 2 then single CPU mode. When not defined, default will be lockstep mode.
Constraints of the possible values?
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + reg:
> + items:
> + - description: RPU subsystem status and control registers
> +
> +patternProperties:
> + "^r5f-[a-f0-9]+$":
> + type: object
> + description: |
> + The RPU is located in the Low Power Domain of the Processor Subsystem.
> + Each processor includes separate L1 instruction and data caches and
> + tightly coupled memories (TCM). System memory is cacheable, but the TCM
> + memory space is non-cacheable.
> +
> + Each RPU contains one 64KB memory and two 32KB memories that
> + are accessed via the TCM A and B port interfaces, for a total of 128KB
> + per processor. In lock-step mode, the processor has access to 256KB of
> + TCM memory.
> +
> + properties:
> + compatible:
> + const: xlnx,zynqmp-r5f
> +
> + power-domains:
> + description: |
> + phandle to a PM domain provider node and an args specifier containing
> + the r5f0 and r5f1 node id value.
You don't need to redefine what this is, but you need to define how many
entries and what they are. It sounds like 2 how this is worded, but the
example shows 1 entry.
> +
> + reg:
> + items:
> + - description: RPU0 and RPU1 control and status registers
1 or 2 entries?
> +
> + mboxes:
> + items:
> + - description: |
> + Bi-directional channel to send data to RPU and receive ack from RPU.
> + Request and response message buffers are available and each buffer is 32 bytes.
> + - description: |
> + Bi-directional channel to receive data from RPU and send ack from RPU.
> + Request and response message buffers are available and each buffer is 32 bytes.
I don't think I'd call this bi-directional. Aren't mboxes one direction
of data flow and the ack is just a detail of the protocol?
> + minItems: 1
> +
> + mbox-names:
> + items:
> + - const: tx
> + - const: rx
> + minItems: 1
> +
> + sram:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + minItems: 1
> + description: |
> + phandles to one or more reserved on-chip SRAM regions. Other than TCM,
> + the RPU can execute instructions and access data from, the OCM memory,
> + the main DDR memory, and other system memories.
> +
> + The regions should be defined as child nodes of the respective SRAM
> + node, and should be defined as per the generic bindings in,
> + Documentation/devicetree/bindings/sram/sram.yaml
> +
> + memory-region:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Already has a type.
This needs how many and what each one is.
> + description: |
> + List of phandles to the reserved memory regions associated with the
> + remoteproc device. This is variable and describes the memories shared with
> + the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
> + vrings, ...). This reserved memory region will be allocated on DDR memory.
> + See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
Don't link to old text bindings.
> +
> + required:
> + - compatible
> + - power-domains
reg should be required or dropped altogether.
> +
> + unevaluatedProperties: false
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + r5fss: r5fss@ff9a0000 {
> + compatible = "xlnx,zynqmp-r5fss";
> + xlnx,cluster-mode = <1>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xff9a0000 0x228>;
> +
> + r5f-0 {
> + compatible = "xlnx,zynqmp-r5f";
> + power-domains = <&zynqmp_firmware 0x7>;
> + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
> + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
> + mbox-names = "tx", "rx";
> + };
> +
> + r5f-1 {
> + compatible = "xlnx,zynqmp-r5f";
> + power-domains = <&zynqmp_firmware 0x8>;
> + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
> + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
> + mbox-names = "tx", "rx";
> + };
> + };
> +...
> diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
> index 0d9a412fd5e0..618024cbb20d 100644
> --- a/include/dt-bindings/power/xlnx-zynqmp-power.h
> +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
> @@ -6,6 +6,12 @@
> #ifndef _DT_BINDINGS_ZYNQMP_POWER_H
> #define _DT_BINDINGS_ZYNQMP_POWER_H
>
> +#define PD_RPU_0 7
> +#define PD_RPU_1 8
> +#define PD_R5_0_ATCM 15
> +#define PD_R5_0_BTCM 16
> +#define PD_R5_1_ATCM 17
> +#define PD_R5_1_BTCM 18
> #define PD_USB_0 22
> #define PD_USB_1 23
> #define PD_TTC_0 24
> --
> 2.25.1
>
>