Hi,
This series add support for the USB Host controllers available on
RZN1 (r9a06g032) SOC.
These USB Host controllers are PCI OHCI/EHCI controllers located
behind a bridge.
Regards,
Herve
Changes v2:
- Convert bindings to json-schema
- Update clocks description
- Remove unneeded '.compatible = "renesas,pci-r9a06g032"'
Changes v3:
- Remove the unneeded patch that calls clk_bulk_prepare_enable()
- Rework the device tree binding (conversion from .txt and RZ/N1 support)
- Use the RZ/N1 SOCs family only in the driver match compatible string.
- Enable PM and PM_GENERIC_DOMAIN for RZ/N1 and add the missing
'#power-domain-cells' in sysctrl node.
Herve Codina (8):
dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for
r9a06g032
PCI: rcar-gen2: Add RZ/N1 SOCs support
soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs
ARM: dts: r9a06g032: Add missing '#power-domain-cells'
ARM: dts: r9a06g032: Add internal PCI bridge node
ARM: dts: r9a06g032: Add USB PHY DT support
ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
.../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 --------
.../bindings/pci/renesas,pci-rcar-gen2.yaml | 187 ++++++++++++++++++
arch/arm/boot/dts/r9a06g032.dtsi | 48 +++++
drivers/pci/controller/pci-rcar-gen2.c | 1 +
drivers/soc/renesas/Kconfig | 2 +
5 files changed, 238 insertions(+), 84 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
--
2.35.1
Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of
one.
Signed-off-by: Herve Codina <[email protected]>
---
.../bindings/pci/renesas,pci-rcar-gen2.yaml | 43 ++++++++++++++++---
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
index 494eb975c146..c29c46533e1b 100644
--- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
@@ -32,6 +32,10 @@ properties:
- renesas,pci-r8a7793 # R-Car M2-N
- renesas,pci-r8a7794 # R-Car E2
- const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+ - items:
+ - enum:
+ - renesas,pci-r9a06g032 # RZ/N1D
+ - const: renesas,pci-rzn1 # RZ/N1
reg:
items:
@@ -41,13 +45,9 @@ properties:
interrupts:
maxItems: 1
- clocks:
- items:
- - description: Device clock
+ clocks: true
- clock-names:
- items:
- - const: pclk
+ clock-names: true
resets:
maxItems: 1
@@ -113,6 +113,37 @@ required:
- "#size-cells"
- "#interrupt-cells"
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,pci-rzn1
+
+then:
+ properties:
+ clocks:
+ items:
+ - description: Internal bus clock (AHB) for HOST
+ - description: Internal bus clock (AHB) Power Management
+ - description: PCI clock for USB subsystem
+ clock-names:
+ items:
+ - const: hclk_usbh
+ - const: hclk_usbpm
+ - const: clk_pci_usb
+ required:
+ - clock-names
+
+else:
+ properties:
+ clocks:
+ items:
+ - description: Device clock
+ clock-names:
+ items:
+ - const: pclk
+
unevaluatedProperties: false
examples:
--
2.35.1
Add Renesas RZ/N1 SOCs family support to the Renesas R-Car
gen2 PCI bridge driver.
The Renesas RZ/N1 SOCs internal PCI bridge is comptible with
the one available in the R-Car Gen2 family.
Tested with the RZ/N1D (R9A06G032) SOC.
Signed-off-by: Herve Codina <[email protected]>
---
drivers/pci/controller/pci-rcar-gen2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
index 35804ea394fd..839695791757 100644
--- a/drivers/pci/controller/pci-rcar-gen2.c
+++ b/drivers/pci/controller/pci-rcar-gen2.c
@@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = {
{ .compatible = "renesas,pci-r8a7791", },
{ .compatible = "renesas,pci-r8a7794", },
{ .compatible = "renesas,pci-rcar-gen2", },
+ { .compatible = "renesas,pci-rzn1", },
{ },
};
--
2.35.1
Add the device node for the r9a06g032 internal PCI bridge device.
Signed-off-by: Herve Codina <[email protected]>
---
arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 20286433d3c6..33581f0c55c4 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ pci_usb: pci@40030000 {
+ compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
+ device_type = "pci";
+ clocks = <&sysctrl R9A06G032_HCLK_USBH>,
+ <&sysctrl R9A06G032_HCLK_USBPM>,
+ <&sysctrl R9A06G032_CLK_PCI_USB>;
+ clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
+ power-domains = <&sysctrl>;
+ reg = <0x40030000 0xc00>,
+ <0x40020000 0x1100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
+ /* Should map all possible DDR as inbound ranges, but
+ * the IP only supports a 256MB, 512MB, or 1GB window.
+ * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
+ */
+ dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
timer {
--
2.35.1
On Fri, Apr 22, 2022 at 02:08:45PM +0200, Herve Codina wrote:
> Add Renesas RZ/N1 SOCs family support to the Renesas R-Car
> gen2 PCI bridge driver.
> The Renesas RZ/N1 SOCs internal PCI bridge is comptible with
> the one available in the R-Car Gen2 family.
> Tested with the RZ/N1D (R9A06G032) SOC.
Nits (only address if you have some other reason to repost this
series):
- Subject claims this adds "support," which suggests that this adds
some piece of new functionality. But it adds no new
functionality, it merely adds a new compatible string. I would
say "Add RZ/N1 SOC compatible string"
- Add blank lines between paragraphs
- Rewrap paragraphs to fill 75 characters
- s/comptible/compatible/
- s/R-Car gen2/R-Car Gen2/ to write this consistently instead of
capitalizing "Gen2" sometimes but not others
> Signed-off-by: Herve Codina <[email protected]>
> ---
> drivers/pci/controller/pci-rcar-gen2.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
> index 35804ea394fd..839695791757 100644
> --- a/drivers/pci/controller/pci-rcar-gen2.c
> +++ b/drivers/pci/controller/pci-rcar-gen2.c
> @@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = {
> { .compatible = "renesas,pci-r8a7791", },
> { .compatible = "renesas,pci-r8a7794", },
> { .compatible = "renesas,pci-rcar-gen2", },
> + { .compatible = "renesas,pci-rzn1", },
> { },
> };
>
> --
> 2.35.1
>
Describe the PCI USB devices that are behind the PCI bridge, adding
necessary links to the USB PHY device.
Signed-off-by: Herve Codina <[email protected]>
---
arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 58af07eb75c9..8dc50c09ac65 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -246,6 +246,18 @@ pci_usb: pci@40030000 {
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usbphy>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usbphy>;
+ phy-names = "usb";
+ };
};
};
--
2.35.1
On Fri, 22 Apr 2022 14:08:44 +0200, Herve Codina wrote:
> Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
> RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
> present in the R-Car Gen2 family.
> Compared to the R-Car Gen2 family, it needs three clocks instead of
> one.
>
> Signed-off-by: Herve Codina <[email protected]>
> ---
> .../bindings/pci/renesas,pci-rcar-gen2.yaml | 43 ++++++++++++++++---
> 1 file changed, 37 insertions(+), 6 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
Hi Hervé,
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <[email protected]> wrote:
> Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
> RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
> present in the R-Car Gen2 family.
> Compared to the R-Car Gen2 family, it needs three clocks instead of
> one.
>
> Signed-off-by: Herve Codina <[email protected]>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> @@ -113,6 +113,37 @@ required:
> - "#size-cells"
> - "#interrupt-cells"
>
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,pci-rzn1
> +
> +then:
> + properties:
> + clocks:
> + items:
> + - description: Internal bus clock (AHB) for HOST
> + - description: Internal bus clock (AHB) Power Management
> + - description: PCI clock for USB subsystem
> + clock-names:
> + items:
> + - const: hclk_usbh
> + - const: hclk_usbpm
> + - const: clk_pci_usb
These are the provider names.
I think they should use the consumer names: usb_hclkh, usb_hclkpm,
and usb_pciclk.
The rest looks good to me.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Hervé
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <[email protected]> wrote:
> Add the device node for the r9a06g032 internal PCI bridge device.
>
> Signed-off-by: Herve Codina <[email protected]>
Thanks for your patch!
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
> interrupts =
> <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> };
> +
> + pci_usb: pci@40030000 {
> + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
> + device_type = "pci";
> + clocks = <&sysctrl R9A06G032_HCLK_USBH>,
> + <&sysctrl R9A06G032_HCLK_USBPM>,
> + <&sysctrl R9A06G032_CLK_PCI_USB>;
> + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
The clock names need an update, cfr. my comment on the bindings.
The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Bjorn,
On Fri, 22 Apr 2022 11:47:44 -0500
Bjorn Helgaas <[email protected]> wrote:
> On Fri, Apr 22, 2022 at 02:08:45PM +0200, Herve Codina wrote:
> > Add Renesas RZ/N1 SOCs family support to the Renesas R-Car
> > gen2 PCI bridge driver.
> > The Renesas RZ/N1 SOCs internal PCI bridge is comptible with
> > the one available in the R-Car Gen2 family.
> > Tested with the RZ/N1D (R9A06G032) SOC.
>
> Nits (only address if you have some other reason to repost this
> series):
>
> - Subject claims this adds "support," which suggests that this adds
> some piece of new functionality. But it adds no new
> functionality, it merely adds a new compatible string. I would
> say "Add RZ/N1 SOC compatible string"
>
> - Add blank lines between paragraphs
>
> - Rewrap paragraphs to fill 75 characters
>
> - s/comptible/compatible/
>
> - s/R-Car gen2/R-Car Gen2/ to write this consistently instead of
> capitalizing "Gen2" sometimes but not others
I plan a v4 and so, I will take these points into account.
Thanks for the review.
Regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Hi Hervé,
On Thu, Apr 28, 2022 at 11:49 AM Geert Uytterhoeven
<[email protected]> wrote:
> > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
> > interrupts =
> > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> > };
> > +
> > + pci_usb: pci@40030000 {
Please preserve sort order (by unit address).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <[email protected]> wrote:
> Describe the PCI USB devices that are behind the PCI bridge, adding
> necessary links to the USB PHY device.
>
> Signed-off-by: Herve Codina <[email protected]>
LGTM, so
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Thu, 28 Apr 2022 11:50:21 +0200
Geert Uytterhoeven <[email protected]> wrote:
> Hi Hervé,
>
> On Thu, Apr 28, 2022 at 11:49 AM Geert Uytterhoeven
> <[email protected]> wrote:
> > > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
> > > interrupts =
> > > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> > > };
> > > +
> > > + pci_usb: pci@40030000 {
>
> Please preserve sort order (by unit address).
Ok, will be done in v4.
Thanks,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Hi Geert,
On Thu, 28 Apr 2022 11:49:28 +0200
Geert Uytterhoeven <[email protected]> wrote:
> Hi Hervé
>
> On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <[email protected]> wrote:
> > Add the device node for the r9a06g032 internal PCI bridge device.
> >
> > Signed-off-by: Herve Codina <[email protected]>
>
> Thanks for your patch!
>
> > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
> > interrupts =
> > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> > };
> > +
> > + pci_usb: pci@40030000 {
> > + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
> > + device_type = "pci";
> > + clocks = <&sysctrl R9A06G032_HCLK_USBH>,
> > + <&sysctrl R9A06G032_HCLK_USBPM>,
> > + <&sysctrl R9A06G032_CLK_PCI_USB>;
> > + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
>
> The clock names need an update, cfr. my comment on the bindings.
Sure.
>
> The rest LGTM, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <[email protected]>
>
Thanks for the review.
Regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Hi Geert,
On Wed, 27 Apr 2022 17:15:15 +0200
Geert Uytterhoeven <[email protected]> wrote:
> Hi Hervé,
>
> On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <[email protected]> wrote:
> > Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
> > RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
> > present in the R-Car Gen2 family.
> > Compared to the R-Car Gen2 family, it needs three clocks instead of
> > one.
> >
> > Signed-off-by: Herve Codina <[email protected]>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> > +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> > @@ -113,6 +113,37 @@ required:
> > - "#size-cells"
> > - "#interrupt-cells"
> >
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - renesas,pci-rzn1
> > +
> > +then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: Internal bus clock (AHB) for HOST
> > + - description: Internal bus clock (AHB) Power Management
> > + - description: PCI clock for USB subsystem
> > + clock-names:
> > + items:
> > + - const: hclk_usbh
> > + - const: hclk_usbpm
> > + - const: clk_pci_usb
>
> These are the provider names.
> I think they should use the consumer names: usb_hclkh, usb_hclkpm,
> and usb_pciclk.
Yes, it makes sense.
I will changed in v4.
>
> The rest looks good to me.
Perfect.
Thanks for the review,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com