2022-04-27 10:59:42

by Fabien Parent

Subject: [PATCH 4/7] arm64: dts: mediatek: mt8195-evb: enable ethernet

From: Biao Huang <[email protected]>

Add ethernet support for MT8195 EVB.

Signed-off-by: Biao Huang <[email protected]>
Signed-off-by: Fabien Parent <[email protected]>
---
This patch comes from https://lore.kernel.org/all/[email protected]/

The differences between that patch and this patch is that:
* The EVB dts modification has been split into its own commit
* The patch was rebased to fix merge conflict with the upstream mt8195-evb.dts file
* Re-ordered the node to be correctly sorted based on phandle name
* Re-ordered the pins for the pinctrl to be sorted by node name
* Fixed dtbs_check: use - instead of _ in node names + prefix pins node with pins-

arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 90 +++++++++++++++++++++
1 file changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
index d49ae8605e67..0b04421942ac 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8195.dtsi"
+#include <dt-bindings/gpio/gpio.h>

/ {
model = "MediaTek MT8195 evaluation board";
@@ -28,6 +29,29 @@ &auxadc {
status = "okay";
};

+&eth {
+ phy-mode ="rgmii-rxid";
+ phy-handle = <&eth_phy0>;
+ snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
+ snps,reset-delays-us = <0 10000 10000>;
+ mediatek,tx-delay-ps = <2030>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&eth_default_pins>;
+ pinctrl-1 = <&eth_sleep_pins>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ eth_phy0: eth_phy0@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ #phy-cells = <0>;
+ reg = <0x1>;
+ };
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pin>;
@@ -69,6 +93,72 @@ flash@0 {
};

&pio {
+ eth_default_pins: eth-default-pins {
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+ <PINMUX_GPIO88__FUNC_GBE_TXEN>,
+ <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+ <PINMUX_GPIO86__FUNC_GBE_RXC>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+ <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+ input-enable;
+ };
+ pins-power {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ output-high;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+ <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+ <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+ <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+ };
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+ <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+ <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+ <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ };
+
+ eth_sleep_pins: eth-sleep-pins {
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+ <PINMUX_GPIO88__FUNC_GPIO88>,
+ <PINMUX_GPIO87__FUNC_GPIO87>,
+ <PINMUX_GPIO86__FUNC_GPIO86>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+ <PINMUX_GPIO90__FUNC_GPIO90>;
+ input-disable;
+ bias-disable;
+ };
+ pins-power {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ input-disable;
+ bias-disable;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+ <PINMUX_GPIO82__FUNC_GPIO82>,
+ <PINMUX_GPIO83__FUNC_GPIO83>,
+ <PINMUX_GPIO84__FUNC_GPIO84>;
+ };
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+ <PINMUX_GPIO78__FUNC_GPIO78>,
+ <PINMUX_GPIO79__FUNC_GPIO79>,
+ <PINMUX_GPIO80__FUNC_GPIO80>;
+ };
+ };
+
i2c0_pin: i2c0-pins {
pins {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
--
2.36.0