2022-04-30 13:52:01

by Robert Foss

Subject: [PATCH v1 9/9] arm64: dts: qcom: sm8350: Add DISPCC node

Add the dispcc clock-controller DT node for sm8350.

Signed-off-by: Robert Foss <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index c49735d1b458..252fdef927cb 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,7 +3,9 @@
* Copyright (c) 2020, Linaro Limited
*/

+#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
@@ -2533,6 +2535,29 @@ usb_2_dwc3: usb@a800000 {
};
};

+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8350-dispcc";
+ reg = <0 0x0af00000 0 0x10000>;
+ mmcx-supply = <&mmcx_reg>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
adsp: remoteproc@17300000 {
compatible = "qcom,sm8350-adsp-pas";
reg = <0 0x17300000 0 0x100>;
--
2.32.0

2022-05-02 11:13:22

by Dmitry Baryshkov

Subject: Re: [PATCH v1 9/9] arm64: dts: qcom: sm8350: Add DISPCC node

On 29/04/2022 18:12, Robert Foss wrote:
> Add the dispcc clock-controller DT node for sm8350.
>
> Signed-off-by: Robert Foss <[email protected]>

With mmcx-supply removed:

Reviewed-by: Dmitry Baryshkov <[email protected]>


> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index c49735d1b458..252fdef927cb 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -3,7 +3,9 @@
> * Copyright (c) 2020, Linaro Limited
> */
>
> +#include <dt-bindings/interconnect/qcom,sm8350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> @@ -2533,6 +2535,29 @@ usb_2_dwc3: usb@a800000 {
> };
> };
>
> + dispcc: clock-controller@af00000 {
> + compatible = "qcom,sm8350-dispcc";
> + reg = <0 0x0af00000 0 0x10000>;
> + mmcx-supply = <&mmcx_reg>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + clock-names = "bi_tcxo",
> + "dsi0_phy_pll_out_byteclk",
> + "dsi0_phy_pll_out_dsiclk",
> + "dsi1_phy_pll_out_byteclk",
> + "dsi1_phy_pll_out_dsiclk",
> + "dp_phy_pll_link_clk",
> + "dp_phy_pll_vco_div_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> adsp: remoteproc@17300000 {
> compatible = "qcom,sm8350-adsp-pas";
> reg = <0 0x17300000 0 0x100>;


--
With best wishes
Dmitry