2022-05-10 15:58:19

by Nick Forrington

[permalink] [raw]
Subject: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

Add Performance Monitoring Unit event data for the Arm CPUs listed
below.

Changesets are dependent due to incremental updates to the common events
file and mapfile.csv.

Data is sourced from https://github.com/ARM-software/data

Nick Forrington (20):
perf vendors events arm64: Arm Cortex-A5
perf vendors events arm64: Arm Cortex-A7
perf vendors events arm64: Arm Cortex-A8
perf vendors events arm64: Arm Cortex-A9
perf vendors events arm64: Arm Cortex-A15
perf vendors events arm64: Arm Cortex-A17
perf vendors events arm64: Arm Cortex-A32
perf vendors events arm64: Arm Cortex-A34
perf vendors events arm64: Arm Cortex-A35
perf vendors events arm64: Arm Cortex-A55
perf vendors events arm64: Arm Cortex-A510
perf vendors events arm64: Arm Cortex-A65
perf vendors events arm64: Arm Cortex-A73
perf vendors events arm64: Arm Cortex-A75
perf vendors events arm64: Arm Cortex-A77
perf vendors events arm64: Arm Cortex-A78
perf vendors events arm64: Arm Cortex-A710
perf vendors events arm64: Arm Cortex-X1
perf vendors events arm64: Arm Cortex-X2
perf vendors events arm64: Arm Neoverse E1

.../arch/arm64/arm/cortex-a15/branch.json | 17 ++
.../arch/arm64/arm/cortex-a15/bus.json | 29 +++
.../arch/arm64/arm/cortex-a15/cache.json | 80 ++++++
.../arch/arm64/arm/cortex-a15/exception.json | 8 +
.../arm64/arm/cortex-a15/instruction.json | 59 +++++
.../arch/arm64/arm/cortex-a15/memory.json | 20 ++
.../arch/arm64/arm/cortex-a17/branch.json | 17 ++
.../arch/arm64/arm/cortex-a17/bus.json | 26 ++
.../arch/arm64/arm/cortex-a17/cache.json | 53 ++++
.../arch/arm64/arm/cortex-a17/exception.json | 11 +
.../arm64/arm/cortex-a17/instruction.json | 56 +++++
.../arch/arm64/arm/cortex-a17/memory.json | 20 ++
.../arch/arm64/arm/cortex-a32/branch.json | 11 +
.../arch/arm64/arm/cortex-a32/bus.json | 17 ++
.../arch/arm64/arm/cortex-a32/cache.json | 32 +++
.../arch/arm64/arm/cortex-a32/exception.json | 14 ++
.../arm64/arm/cortex-a32/instruction.json | 29 +++
.../arch/arm64/arm/cortex-a32/memory.json | 8 +
.../arch/arm64/arm/cortex-a34/branch.json | 11 +
.../arch/arm64/arm/cortex-a34/bus.json | 17 ++
.../arch/arm64/arm/cortex-a34/cache.json | 32 +++
.../arch/arm64/arm/cortex-a34/exception.json | 14 ++
.../arm64/arm/cortex-a34/instruction.json | 29 +++
.../arch/arm64/arm/cortex-a34/memory.json | 8 +
.../arch/arm64/arm/cortex-a35/branch.json | 11 +
.../arch/arm64/arm/cortex-a35/bus.json | 17 ++
.../arch/arm64/arm/cortex-a35/cache.json | 32 +++
.../arch/arm64/arm/cortex-a35/exception.json | 14 ++
.../arm64/arm/cortex-a35/instruction.json | 44 ++++
.../arch/arm64/arm/cortex-a35/memory.json | 8 +
.../arch/arm64/arm/cortex-a5/branch.json | 8 +
.../arch/arm64/arm/cortex-a5/cache.json | 23 ++
.../arch/arm64/arm/cortex-a5/exception.json | 11 +
.../arch/arm64/arm/cortex-a5/instruction.json | 29 +++
.../arch/arm64/arm/cortex-a5/memory.json | 8 +
.../arch/arm64/arm/cortex-a510/branch.json | 59 +++++
.../arch/arm64/arm/cortex-a510/bus.json | 17 ++
.../arch/arm64/arm/cortex-a510/cache.json | 182 ++++++++++++++
.../arch/arm64/arm/cortex-a510/exception.json | 14 ++
.../arm64/arm/cortex-a510/instruction.json | 95 +++++++
.../arch/arm64/arm/cortex-a510/memory.json | 32 +++
.../arch/arm64/arm/cortex-a510/pipeline.json | 107 ++++++++
.../arch/arm64/arm/cortex-a510/pmu.json | 8 +
.../arch/arm64/arm/cortex-a510/trace.json | 32 +++
.../arch/arm64/arm/cortex-a55/branch.json | 59 +++++
.../arch/arm64/arm/cortex-a55/bus.json | 17 ++
.../arch/arm64/arm/cortex-a55/cache.json | 188 ++++++++++++++
.../arch/arm64/arm/cortex-a55/exception.json | 20 ++
.../arm64/arm/cortex-a55/instruction.json | 65 +++++
.../arch/arm64/arm/cortex-a55/memory.json | 17 ++
.../arch/arm64/arm/cortex-a55/pipeline.json | 80 ++++++
.../arch/arm64/arm/cortex-a65/branch.json | 17 ++
.../arch/arm64/arm/cortex-a65/bus.json | 17 ++
.../arch/arm64/arm/cortex-a65/cache.json | 236 ++++++++++++++++++
.../arch/arm64/arm/cortex-a65/dpu.json | 32 +++
.../arch/arm64/arm/cortex-a65/exception.json | 14 ++
.../arch/arm64/arm/cortex-a65/ifu.json | 122 +++++++++
.../arm64/arm/cortex-a65/instruction.json | 71 ++++++
.../arch/arm64/arm/cortex-a65/memory.json | 35 +++
.../arch/arm64/arm/cortex-a65/pipeline.json | 8 +
.../arch/arm64/arm/cortex-a7/branch.json | 8 +
.../arch/arm64/arm/cortex-a7/bus.json | 17 ++
.../arch/arm64/arm/cortex-a7/cache.json | 32 +++
.../arch/arm64/arm/cortex-a7/exception.json | 11 +
.../arch/arm64/arm/cortex-a7/instruction.json | 29 +++
.../arch/arm64/arm/cortex-a7/memory.json | 8 +
.../arch/arm64/arm/cortex-a710/branch.json | 17 ++
.../arch/arm64/arm/cortex-a710/bus.json | 20 ++
.../arch/arm64/arm/cortex-a710/cache.json | 155 ++++++++++++
.../arch/arm64/arm/cortex-a710/exception.json | 47 ++++
.../arm64/arm/cortex-a710/instruction.json | 134 ++++++++++
.../arch/arm64/arm/cortex-a710/memory.json | 41 +++
.../arch/arm64/arm/cortex-a710/pipeline.json | 23 ++
.../arch/arm64/arm/cortex-a710/trace.json | 29 +++
.../arch/arm64/arm/cortex-a73/branch.json | 11 +
.../arch/arm64/arm/cortex-a73/bus.json | 23 ++
.../arch/arm64/arm/cortex-a73/cache.json | 107 ++++++++
.../arch/arm64/arm/cortex-a73/etm.json | 14 ++
.../arch/arm64/arm/cortex-a73/exception.json | 14 ++
.../arm64/arm/cortex-a73/instruction.json | 65 +++++
.../arch/arm64/arm/cortex-a73/memory.json | 14 ++
.../arch/arm64/arm/cortex-a73/mmu.json | 44 ++++
.../arch/arm64/arm/cortex-a73/pipeline.json | 38 +++
.../arch/arm64/arm/cortex-a75/branch.json | 11 +
.../arch/arm64/arm/cortex-a75/bus.json | 17 ++
.../arch/arm64/arm/cortex-a75/cache.json | 164 ++++++++++++
.../arch/arm64/arm/cortex-a75/etm.json | 14 ++
.../arch/arm64/arm/cortex-a75/exception.json | 17 ++
.../arm64/arm/cortex-a75/instruction.json | 74 ++++++
.../arch/arm64/arm/cortex-a75/memory.json | 17 ++
.../arch/arm64/arm/cortex-a75/mmu.json | 44 ++++
.../arch/arm64/arm/cortex-a75/pipeline.json | 44 ++++
.../arch/arm64/arm/cortex-a77/branch.json | 17 ++
.../arch/arm64/arm/cortex-a77/bus.json | 17 ++
.../arch/arm64/arm/cortex-a77/cache.json | 143 +++++++++++
.../arch/arm64/arm/cortex-a77/exception.json | 47 ++++
.../arm64/arm/cortex-a77/instruction.json | 77 ++++++
.../arch/arm64/arm/cortex-a77/memory.json | 23 ++
.../arch/arm64/arm/cortex-a77/pipeline.json | 8 +
.../arch/arm64/arm/cortex-a78/branch.json | 17 ++
.../arch/arm64/arm/cortex-a78/bus.json | 20 ++
.../arch/arm64/arm/cortex-a78/cache.json | 155 ++++++++++++
.../arch/arm64/arm/cortex-a78/exception.json | 47 ++++
.../arm64/arm/cortex-a78/instruction.json | 80 ++++++
.../arch/arm64/arm/cortex-a78/memory.json | 23 ++
.../arch/arm64/arm/cortex-a78/pipeline.json | 23 ++
.../arch/arm64/arm/cortex-a8/branch.json | 8 +
.../arch/arm64/arm/cortex-a8/cache.json | 77 ++++++
.../arch/arm64/arm/cortex-a8/exception.json | 5 +
.../arch/arm64/arm/cortex-a8/instruction.json | 38 +++
.../arch/arm64/arm/cortex-a8/memory.json | 5 +
.../arch/arm64/arm/cortex-a9/branch.json | 8 +
.../arch/arm64/arm/cortex-a9/cache.json | 17 ++
.../arch/arm64/arm/cortex-a9/exception.json | 5 +
.../arch/arm64/arm/cortex-a9/instruction.json | 29 +++
.../arch/arm64/arm/cortex-a9/memory.json | 5 +
.../arch/arm64/arm/cortex-x1/branch.json | 17 ++
.../arch/arm64/arm/cortex-x1/bus.json | 20 ++
.../arch/arm64/arm/cortex-x1/cache.json | 155 ++++++++++++
.../arch/arm64/arm/cortex-x1/exception.json | 47 ++++
.../arch/arm64/arm/cortex-x1/instruction.json | 80 ++++++
.../arch/arm64/arm/cortex-x1/memory.json | 23 ++
.../arch/arm64/arm/cortex-x1/pipeline.json | 23 ++
.../arch/arm64/arm/cortex-x2/branch.json | 17 ++
.../arch/arm64/arm/cortex-x2/bus.json | 20 ++
.../arch/arm64/arm/cortex-x2/cache.json | 155 ++++++++++++
.../arch/arm64/arm/cortex-x2/exception.json | 47 ++++
.../arch/arm64/arm/cortex-x2/instruction.json | 134 ++++++++++
.../arch/arm64/arm/cortex-x2/memory.json | 41 +++
.../arch/arm64/arm/cortex-x2/pipeline.json | 23 ++
.../arch/arm64/arm/cortex-x2/trace.json | 29 +++
.../arch/arm64/arm/neoverse-e1/branch.json | 17 ++
.../arch/arm64/arm/neoverse-e1/bus.json | 17 ++
.../arch/arm64/arm/neoverse-e1/cache.json | 107 ++++++++
.../arch/arm64/arm/neoverse-e1/exception.json | 14 ++
.../arm64/arm/neoverse-e1/instruction.json | 65 +++++
.../arch/arm64/arm/neoverse-e1/memory.json | 23 ++
.../arch/arm64/arm/neoverse-e1/pipeline.json | 8 +
.../arch/arm64/arm/neoverse-e1/spe.json | 14 ++
.../arch/arm64/common-and-microarch.json | 66 +++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 20 ++
141 files changed, 5746 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json

--
2.25.1



2022-05-10 18:12:15

by Nick Forrington

[permalink] [raw]
Subject: [PATCH 17/20] perf vendors events arm64: Arm Cortex-A710

Add PMU events for Arm Cortex-A710
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a710.json

which is based on PMU event descriptions from the Arm Cortex-A710 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Signed-off-by: Nick Forrington <[email protected]>
---
.../arch/arm64/arm/cortex-a710/branch.json | 17 ++
.../arch/arm64/arm/cortex-a710/bus.json | 20 +++
.../arch/arm64/arm/cortex-a710/cache.json | 155 ++++++++++++++++++
.../arch/arm64/arm/cortex-a710/exception.json | 47 ++++++
.../arm64/arm/cortex-a710/instruction.json | 134 +++++++++++++++
.../arch/arm64/arm/cortex-a710/memory.json | 41 +++++
.../arch/arm64/arm/cortex-a710/pipeline.json | 23 +++
.../arch/arm64/arm/cortex-a710/trace.json | 29 ++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
9 files changed, 467 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
new file mode 100644
index 000000000000..2f2d137f5f55
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
new file mode 100644
index 000000000000..579c1c993d17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
@@ -0,0 +1,20 @@
+[
+ {
+ "ArchStdEvent": "CPU_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS"
+ },
+ {
+ "ArchStdEvent": "BUS_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "CNT_CYCLES"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
new file mode 100644
index 000000000000..0141f749bff3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
@@ -0,0 +1,155 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB"
+ },
+ {
+ "ArchStdEvent": "DTLB_WALK"
+ },
+ {
+ "ArchStdEvent": "ITLB_WALK"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_MISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_LMISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_WR"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE_LMISS"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_LMISS_RD"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_LMISS_RD"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
new file mode 100644
index 000000000000..344a2d552ad5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
@@ -0,0 +1,47 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ },
+ {
+ "ArchStdEvent": "MEMORY_ERROR"
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF"
+ },
+ {
+ "ArchStdEvent": "EXC_SVC"
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ"
+ },
+ {
+ "ArchStdEvent": "EXC_SMC"
+ },
+ {
+ "ArchStdEvent": "EXC_HVC"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
new file mode 100644
index 000000000000..964f47c6b099
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
@@ -0,0 +1,134 @@
+[
+ {
+ "ArchStdEvent": "SW_INCR"
+ },
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "TTBR_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_MIS_PRED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "OP_RETIRED"
+ },
+ {
+ "ArchStdEvent": "OP_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC"
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC"
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC"
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC"
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_HP_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_SP_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_EMPTY_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_FULL_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_LDFF_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_LDFF_FAULT_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_SCALE_OPS_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_FIXED_OPS_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT8_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT16_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT32_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT64_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
new file mode 100644
index 000000000000..7b2b21ac150f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
@@ -0,0 +1,41 @@
+[
+ {
+ "ArchStdEvent": "MEM_ACCESS"
+ },
+ {
+ "ArchStdEvent": "REMOTE_ACCESS"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDST_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "LD_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "ST_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
new file mode 100644
index 000000000000..f9fae15f7555
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
@@ -0,0 +1,23 @@
+[
+ {
+ "ArchStdEvent": "STALL_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND"
+ },
+ {
+ "ArchStdEvent": "STALL"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT_BACKEND"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND_MEM"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
new file mode 100644
index 000000000000..3116135c59e2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
@@ -0,0 +1,29 @@
+[
+ {
+ "ArchStdEvent": "TRB_WRAP"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT0"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT1"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT2"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT3"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT4"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT5"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT6"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT7"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 31a43b5114bc..1c49480d0e44 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -35,6 +35,7 @@
0x00000000410fd400,v1,arm/neoverse-v1,core
0x00000000410fd410,v1,arm/cortex-a78,core
0x00000000410fd460,v1,arm/cortex-a510,core
+0x00000000410fd470,v1,arm/cortex-a710,core
0x00000000410fd490,v1,arm/neoverse-n2,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
--
2.25.1


2022-05-10 18:13:27

by Nick Forrington

[permalink] [raw]
Subject: [PATCH 02/20] perf vendors events arm64: Arm Cortex-A7

Add PMU events for Arm Cortex-A7
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a7.json

which is based on PMU event descriptions from the Arm Cortex-A7 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Signed-off-by: Nick Forrington <[email protected]>
---
.../arch/arm64/arm/cortex-a7/branch.json | 8 +++++
.../arch/arm64/arm/cortex-a7/bus.json | 17 ++++++++++
.../arch/arm64/arm/cortex-a7/cache.json | 32 +++++++++++++++++++
.../arch/arm64/arm/cortex-a7/exception.json | 11 +++++++
.../arch/arm64/arm/cortex-a7/instruction.json | 29 +++++++++++++++++
.../arch/arm64/arm/cortex-a7/memory.json | 8 +++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
7 files changed, 106 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
new file mode 100644
index 000000000000..79f2016c53b0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
@@ -0,0 +1,8 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
new file mode 100644
index 000000000000..75d850b781ac
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "CPU_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS"
+ },
+ {
+ "ArchStdEvent": "BUS_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
new file mode 100644
index 000000000000..8a9a95e05c32
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
@@ -0,0 +1,32 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
new file mode 100644
index 000000000000..8e6da69a1cbd
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
@@ -0,0 +1,11 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
new file mode 100644
index 000000000000..7c018f439206
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
@@ -0,0 +1,29 @@
+[
+ {
+ "ArchStdEvent": "SW_INCR"
+ },
+ {
+ "ArchStdEvent": "LD_RETIRED"
+ },
+ {
+ "ArchStdEvent": "ST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_RETIRED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json
new file mode 100644
index 000000000000..2c319f936957
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json
@@ -0,0 +1,8 @@
+[
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 154d1fc61ee4..9d8ebe3ea6d2 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -13,6 +13,7 @@
#
#Family-model,Version,Filename,EventType
0x00000000410fc050,v1,arm/cortex-a5,core
+0x00000000410fc070,v1,arm/cortex-a7,core
0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f1000,v1,arm/cortex-a53,core
0x00000000410fd070,v1,arm/cortex-a57-a72,core
--
2.25.1


2022-05-10 18:45:03

by Nick Forrington

[permalink] [raw]
Subject: [PATCH 11/20] perf vendors events arm64: Arm Cortex-A510

Add PMU events for Arm Cortex-A510
Add corresponding common events
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a510.json

which is based on PMU event descriptions from the Arm Cortex-A510 Technical
Reference Manual.

Common event data based on:
https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json

which is based on PMU event descriptions found in the Arm Architecture
Reference Manual:
https://developer.arm.com/documentation/ddi0487/

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Signed-off-by: Nick Forrington <[email protected]>
---
.../arch/arm64/arm/cortex-a510/branch.json | 59 ++++++
.../arch/arm64/arm/cortex-a510/bus.json | 17 ++
.../arch/arm64/arm/cortex-a510/cache.json | 182 ++++++++++++++++++
.../arch/arm64/arm/cortex-a510/exception.json | 14 ++
.../arm64/arm/cortex-a510/instruction.json | 95 +++++++++
.../arch/arm64/arm/cortex-a510/memory.json | 32 +++
.../arch/arm64/arm/cortex-a510/pipeline.json | 107 ++++++++++
.../arch/arm64/arm/cortex-a510/pmu.json | 8 +
.../arch/arm64/arm/cortex-a510/trace.json | 32 +++
.../arch/arm64/common-and-microarch.json | 18 ++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
11 files changed, 565 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
new file mode 100644
index 000000000000..411fcbdbd7e6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
@@ -0,0 +1,59 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC"
+ },
+ {
+ "PublicDescription": "Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off",
+ "EventCode": "0xC9",
+ "EventName": "BR_COND_PRED",
+ "BriefDescription": "Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off"
+ },
+ {
+ "PublicDescription": "Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off",
+ "EventCode": "0xCA",
+ "EventName": "BR_INDIRECT_MIS_PRED",
+ "BriefDescription": "Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off"
+ },
+ {
+ "PublicDescription": "Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
+ "EventCode": "0xCB",
+ "EventName": "BR_INDIRECT_ADDR_MIS_PRED",
+ "BriefDescription": "Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
+ },
+ {
+ "PublicDescription": "Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count",
+ "EventCode": "0xCC",
+ "EventName": "BR_COND_MIS_PRED",
+ "BriefDescription": "Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count"
+ },
+ {
+ "PublicDescription": "Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
+ "EventCode": "0xCD",
+ "EventName": "BR_INDIRECT_ADDR_PRED",
+ "BriefDescription": "Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
+ },
+ {
+ "PublicDescription": "Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
+ "EventCode": "0xCE",
+ "EventName": "BR_RETURN_ADDR_PRED",
+ "BriefDescription": "Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
+ },
+ {
+ "PublicDescription": "Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
+ "EventCode": "0xCF",
+ "EventName": "BR_RETURN_ADDR_MIS_PRED",
+ "BriefDescription": "Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
new file mode 100644
index 000000000000..75d850b781ac
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "CPU_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS"
+ },
+ {
+ "ArchStdEvent": "BUS_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
new file mode 100644
index 000000000000..27cd913e186b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
@@ -0,0 +1,182 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB"
+ },
+ {
+ "ArchStdEvent": "DTLB_WALK"
+ },
+ {
+ "ArchStdEvent": "ITLB_WALK"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_MISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_LMISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_REFILL_RD"
+ },
+ {
+ "PublicDescription": "L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented",
+ "EventCode": "0xC1",
+ "EventName": "L2D_CACHE_REFILL_PREFETCH",
+ "BriefDescription": "L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented"
+ },
+ {
+ "PublicDescription": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache",
+ "EventCode": "0xC2",
+ "EventName": "L1D_CACHE_REFILL_PREFETCH",
+ "BriefDescription": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache"
+ },
+ {
+ "PublicDescription": "L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache",
+ "EventCode": "0xC3",
+ "EventName": "L2D_WS_MODE",
+ "BriefDescription": "L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache"
+ },
+ {
+ "PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode",
+ "EventCode": "0xC4",
+ "EventName": "L1D_WS_MODE_ENTRY",
+ "BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode"
+ },
+ {
+ "PublicDescription": "L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache",
+ "EventCode": "0xC5",
+ "EventName": "L1D_WS_MODE",
+ "BriefDescription": "L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache"
+ },
+ {
+ "PublicDescription": "L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache",
+ "EventCode": "0xC7",
+ "EventName": "L3D_WS_MODE",
+ "BriefDescription": "L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache"
+ },
+ {
+ "PublicDescription": "Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache",
+ "EventCode": "0xC8",
+ "EventName": "LL_WS_MODE",
+ "BriefDescription": "Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache"
+ },
+ {
+ "PublicDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled",
+ "EventCode": "0xD0",
+ "EventName": "L2D_WALK_TLB",
+ "BriefDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled"
+ },
+ {
+ "PublicDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled",
+ "EventCode": "0xD1",
+ "EventName": "L2D_WALK_TLB_REFILL",
+ "BriefDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled"
+ },
+ {
+ "PublicDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count",
+ "EventCode": "0xD4",
+ "EventName": "L2D_S2_TLB",
+ "BriefDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count"
+ },
+ {
+ "PublicDescription": "L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count",
+ "EventCode": "0xD5",
+ "EventName": "L2D_S2_TLB_REFILL",
+ "BriefDescription": "L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count"
+ },
+ {
+ "PublicDescription": "L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request",
+ "EventCode": "0xD6",
+ "EventName": "L2D_CACHE_STASH_DROPPED",
+ "BriefDescription": "L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE_LMISS"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_LMISS_RD"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_LMISS_RD"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
new file mode 100644
index 000000000000..27c3fe9c831a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
@@ -0,0 +1,14 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ },
+ {
+ "ArchStdEvent": "MEMORY_ERROR"
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
new file mode 100644
index 000000000000..3039d03412df
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
@@ -0,0 +1,95 @@
+[
+ {
+ "ArchStdEvent": "LD_RETIRED"
+ },
+ {
+ "ArchStdEvent": "ST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "TTBR_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_MIS_PRED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "OP_RETIRED"
+ },
+ {
+ "ArchStdEvent": "OP_SPEC"
+ },
+ {
+ "ArchStdEvent": "LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC"
+ },
+ {
+ "ArchStdEvent": "DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC"
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC"
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "SVE_INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_HP_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_SP_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT8_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT16_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT32_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT64_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
new file mode 100644
index 000000000000..38f459502514
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
@@ -0,0 +1,32 @@
+[
+ {
+ "ArchStdEvent": "MEM_ACCESS"
+ },
+ {
+ "ArchStdEvent": "REMOTE_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "LDST_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "LD_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "ST_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
new file mode 100644
index 000000000000..325daaa7b809
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
@@ -0,0 +1,107 @@
+[
+ {
+ "ArchStdEvent": "STALL_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND"
+ },
+ {
+ "ArchStdEvent": "STALL"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT_BACKEND"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT"
+ },
+ {
+ "PublicDescription": "No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed",
+ "EventCode": "0xE1",
+ "EventName": "STALL_FRONTEND_CACHE",
+ "BriefDescription": "No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed"
+ },
+ {
+ "PublicDescription": "No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed",
+ "EventCode": "0xE2",
+ "EventName": "STALL_FRONTEND_TLB",
+ "BriefDescription": "No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed"
+ },
+ {
+ "PublicDescription": "No operation issued due to the frontend, pre-decode error",
+ "EventCode": "0xE3",
+ "EventName": "STALL_FRONTEND_PDERR",
+ "BriefDescription": "No operation issued due to the frontend, pre-decode error"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded",
+ "EventCode": "0xE4",
+ "EventName": "STALL_BACKEND_ILOCK",
+ "BriefDescription": "No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded",
+ "EventCode": "0xE5",
+ "EventName": "STALL_BACKEND_ILOCK_ADDR",
+ "BriefDescription": "No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded",
+ "EventCode": "0xE6",
+ "EventName": "STALL_BACKEND_ILOCK_VPU",
+ "BriefDescription": "No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load",
+ "EventCode": "0xE7",
+ "EventName": "STALL_BACKEND_LD",
+ "BriefDescription": "No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store",
+ "EventCode": "0xE8",
+ "EventName": "STALL_BACKEND_ST",
+ "BriefDescription": "No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable",
+ "EventCode": "0xE9",
+ "EventName": "STALL_BACKEND_LD_CACHE",
+ "BriefDescription": "No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage due to a load that misses in the L1 TLB",
+ "EventCode": "0xEA",
+ "EventName": "STALL_BACKEND_LD_TLB",
+ "BriefDescription": "No operation issued due to the backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage due to a load that misses in the L1 TLB"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, store, Store Buffer (STB) full. This event counts every cycle where there is a stall in the Wr stage because of a store operation that is waiting due to the STB being full",
+ "EventCode": "0xEB",
+ "EventName": "STALL_BACKEND_ST_STB",
+ "BriefDescription": "No operation issued due to the backend, store, Store Buffer (STB) full. This event counts every cycle where there is a stall in the Wr stage because of a store operation that is waiting due to the STB being full"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of a store operation that has missed in the L1 TLB",
+ "EventCode": "0xEC",
+ "EventName": "STALL_BACKEND_ST_TLB",
+ "BriefDescription": "No operation issued due to the backend, store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of a store operation that has missed in the L1 TLB"
+ },
+ {
+ "PublicDescription": "No operation issued due to the backend, VPU hazard. This event counts every cycle where the core stalls due to contention for the VPU with the other core",
+ "EventCode": "0xED",
+ "EventName": "STALL_BACKEND_VPU_HAZARD",
+ "BriefDescription": "No operation issued due to the backend, VPU hazard. This event counts every cycle where the core stalls due to contention for the VPU with the other core"
+ },
+ {
+ "PublicDescription": "Issue slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does not issue due to an interlock",
+ "EventCode": "0xEE",
+ "EventName": "STALL_SLOT_BACKEND_ILOCK",
+ "BriefDescription": "Issue slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does not issue due to an interlock"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND_MEM"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
new file mode 100644
index 000000000000..d8b7b9f9e5fa
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
@@ -0,0 +1,8 @@
+[
+ {
+ "ArchStdEvent": "PMU_OVFS"
+ },
+ {
+ "ArchStdEvent": "PMU_HOVFS"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
new file mode 100644
index 000000000000..33672a8711d4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
@@ -0,0 +1,32 @@
+[
+ {
+ "ArchStdEvent": "TRB_WRAP"
+ },
+ {
+ "ArchStdEvent": "TRB_TRIG"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT0"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT1"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT2"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT3"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT4"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT5"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT6"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT7"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json
index c50b231ce03b..876b51dae92e 100644
--- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json
+++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json
@@ -401,6 +401,24 @@
"EventName": "TRB_WRAP",
"BriefDescription": "Trace buffer current write pointer wrapped"
},
+ {
+ "PublicDescription": "PMU overflow, counters accessible to EL1 and EL0",
+ "EventCode": "0x400D",
+ "EventName": "PMU_OVFS",
+ "BriefDescription": "PMU overflow, counters accessible to EL1 and EL0"
+ },
+ {
+ "PublicDescription": "Trace buffer Trigger Event",
+ "EventCode": "0x400E",
+ "EventName": "TRB_TRIG",
+ "BriefDescription": "Trace buffer Trigger Event"
+ },
+ {
+ "PublicDescription": "PMU overflow, counters reserved for use by EL2",
+ "EventCode": "0x400F",
+ "EventName": "PMU_HOVFS",
+ "BriefDescription": "PMU overflow, counters reserved for use by EL2"
+ },
{
"PublicDescription": "PE Trace Unit external output 0",
"EventCode": "0x4010",
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index b8f0a299d204..c464469c4d51 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -29,6 +29,7 @@
0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
0x00000000410fd400,v1,arm/neoverse-v1,core
+0x00000000410fd460,v1,arm/cortex-a510,core
0x00000000410fd490,v1,arm/neoverse-n2,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
--
2.25.1


2022-05-10 19:20:17

by Nick Forrington

[permalink] [raw]
Subject: [PATCH 20/20] perf vendors events arm64: Arm Neoverse E1

Add PMU events for Arm Neoverse E1
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/neoverse-e1.json

which is based on PMU event descriptions from the Arm Neoverse E1 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Signed-off-by: Nick Forrington <[email protected]>
---
.../arch/arm64/arm/neoverse-e1/branch.json | 17 +++
.../arch/arm64/arm/neoverse-e1/bus.json | 17 +++
.../arch/arm64/arm/neoverse-e1/cache.json | 107 ++++++++++++++++++
.../arch/arm64/arm/neoverse-e1/exception.json | 14 +++
.../arm64/arm/neoverse-e1/instruction.json | 65 +++++++++++
.../arch/arm64/arm/neoverse-e1/memory.json | 23 ++++
.../arch/arm64/arm/neoverse-e1/pipeline.json | 8 ++
.../arch/arm64/arm/neoverse-e1/spe.json | 14 +++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
9 files changed, 266 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
new file mode 100644
index 000000000000..2f2d137f5f55
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
new file mode 100644
index 000000000000..75d850b781ac
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "CPU_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS"
+ },
+ {
+ "ArchStdEvent": "BUS_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
new file mode 100644
index 000000000000..3ad15e3a93a9
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
@@ -0,0 +1,107 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB"
+ },
+ {
+ "ArchStdEvent": "DTLB_WALK"
+ },
+ {
+ "ArchStdEvent": "ITLB_WALK"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_MISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_REFILL_RD"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
new file mode 100644
index 000000000000..27c3fe9c831a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
@@ -0,0 +1,14 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ },
+ {
+ "ArchStdEvent": "MEMORY_ERROR"
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
new file mode 100644
index 000000000000..6c3b8f772e7f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
@@ -0,0 +1,65 @@
+[
+ {
+ "ArchStdEvent": "SW_INCR"
+ },
+ {
+ "ArchStdEvent": "LD_RETIRED"
+ },
+ {
+ "ArchStdEvent": "ST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "TTBR_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_MIS_PRED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC"
+ },
+ {
+ "ArchStdEvent": "DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC"
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC"
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC"
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
new file mode 100644
index 000000000000..78ed6dfcedc1
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
@@ -0,0 +1,23 @@
+[
+ {
+ "ArchStdEvent": "MEM_ACCESS"
+ },
+ {
+ "ArchStdEvent": "REMOTE_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
new file mode 100644
index 000000000000..eeac798d403a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
@@ -0,0 +1,8 @@
+[
+ {
+ "ArchStdEvent": "STALL_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json
new file mode 100644
index 000000000000..20f2165c85fe
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json
@@ -0,0 +1,14 @@
+[
+ {
+ "ArchStdEvent": "SAMPLE_POP"
+ },
+ {
+ "ArchStdEvent": "SAMPLE_FEED"
+ },
+ {
+ "ArchStdEvent": "SAMPLE_FILTRATE"
+ },
+ {
+ "ArchStdEvent": "SAMPLE_COLLISION"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index eeed048e407b..9ff3b8065370 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -39,6 +39,7 @@
0x00000000410fd470,v1,arm/cortex-a710,core
0x00000000410fd480,v1,arm/cortex-x2,core
0x00000000410fd490,v1,arm/neoverse-n2,core
+0x00000000410fd4a0,v1,arm/neoverse-e1,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000460f0010,v1,fujitsu/a64fx,core
--
2.25.1


2022-05-10 20:46:19

by Arnaldo Carvalho de Melo

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
> Add Performance Monitoring Unit event data for the Arm CPUs listed
> below.
>
> Changesets are dependent due to incremental updates to the common events
> file and mapfile.csv.
>
> Data is sourced from https://github.com/ARM-software/data

Waiting for reviews to merge this.

- Arnaldo

> Nick Forrington (20):
> perf vendors events arm64: Arm Cortex-A5
> perf vendors events arm64: Arm Cortex-A7
> perf vendors events arm64: Arm Cortex-A8
> perf vendors events arm64: Arm Cortex-A9
> perf vendors events arm64: Arm Cortex-A15
> perf vendors events arm64: Arm Cortex-A17
> perf vendors events arm64: Arm Cortex-A32
> perf vendors events arm64: Arm Cortex-A34
> perf vendors events arm64: Arm Cortex-A35
> perf vendors events arm64: Arm Cortex-A55
> perf vendors events arm64: Arm Cortex-A510
> perf vendors events arm64: Arm Cortex-A65
> perf vendors events arm64: Arm Cortex-A73
> perf vendors events arm64: Arm Cortex-A75
> perf vendors events arm64: Arm Cortex-A77
> perf vendors events arm64: Arm Cortex-A78
> perf vendors events arm64: Arm Cortex-A710
> perf vendors events arm64: Arm Cortex-X1
> perf vendors events arm64: Arm Cortex-X2
> perf vendors events arm64: Arm Neoverse E1
>
> .../arch/arm64/arm/cortex-a15/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a15/bus.json | 29 +++
> .../arch/arm64/arm/cortex-a15/cache.json | 80 ++++++
> .../arch/arm64/arm/cortex-a15/exception.json | 8 +
> .../arm64/arm/cortex-a15/instruction.json | 59 +++++
> .../arch/arm64/arm/cortex-a15/memory.json | 20 ++
> .../arch/arm64/arm/cortex-a17/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a17/bus.json | 26 ++
> .../arch/arm64/arm/cortex-a17/cache.json | 53 ++++
> .../arch/arm64/arm/cortex-a17/exception.json | 11 +
> .../arm64/arm/cortex-a17/instruction.json | 56 +++++
> .../arch/arm64/arm/cortex-a17/memory.json | 20 ++
> .../arch/arm64/arm/cortex-a32/branch.json | 11 +
> .../arch/arm64/arm/cortex-a32/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a32/cache.json | 32 +++
> .../arch/arm64/arm/cortex-a32/exception.json | 14 ++
> .../arm64/arm/cortex-a32/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a32/memory.json | 8 +
> .../arch/arm64/arm/cortex-a34/branch.json | 11 +
> .../arch/arm64/arm/cortex-a34/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a34/cache.json | 32 +++
> .../arch/arm64/arm/cortex-a34/exception.json | 14 ++
> .../arm64/arm/cortex-a34/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a34/memory.json | 8 +
> .../arch/arm64/arm/cortex-a35/branch.json | 11 +
> .../arch/arm64/arm/cortex-a35/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a35/cache.json | 32 +++
> .../arch/arm64/arm/cortex-a35/exception.json | 14 ++
> .../arm64/arm/cortex-a35/instruction.json | 44 ++++
> .../arch/arm64/arm/cortex-a35/memory.json | 8 +
> .../arch/arm64/arm/cortex-a5/branch.json | 8 +
> .../arch/arm64/arm/cortex-a5/cache.json | 23 ++
> .../arch/arm64/arm/cortex-a5/exception.json | 11 +
> .../arch/arm64/arm/cortex-a5/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a5/memory.json | 8 +
> .../arch/arm64/arm/cortex-a510/branch.json | 59 +++++
> .../arch/arm64/arm/cortex-a510/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a510/cache.json | 182 ++++++++++++++
> .../arch/arm64/arm/cortex-a510/exception.json | 14 ++
> .../arm64/arm/cortex-a510/instruction.json | 95 +++++++
> .../arch/arm64/arm/cortex-a510/memory.json | 32 +++
> .../arch/arm64/arm/cortex-a510/pipeline.json | 107 ++++++++
> .../arch/arm64/arm/cortex-a510/pmu.json | 8 +
> .../arch/arm64/arm/cortex-a510/trace.json | 32 +++
> .../arch/arm64/arm/cortex-a55/branch.json | 59 +++++
> .../arch/arm64/arm/cortex-a55/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a55/cache.json | 188 ++++++++++++++
> .../arch/arm64/arm/cortex-a55/exception.json | 20 ++
> .../arm64/arm/cortex-a55/instruction.json | 65 +++++
> .../arch/arm64/arm/cortex-a55/memory.json | 17 ++
> .../arch/arm64/arm/cortex-a55/pipeline.json | 80 ++++++
> .../arch/arm64/arm/cortex-a65/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a65/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a65/cache.json | 236 ++++++++++++++++++
> .../arch/arm64/arm/cortex-a65/dpu.json | 32 +++
> .../arch/arm64/arm/cortex-a65/exception.json | 14 ++
> .../arch/arm64/arm/cortex-a65/ifu.json | 122 +++++++++
> .../arm64/arm/cortex-a65/instruction.json | 71 ++++++
> .../arch/arm64/arm/cortex-a65/memory.json | 35 +++
> .../arch/arm64/arm/cortex-a65/pipeline.json | 8 +
> .../arch/arm64/arm/cortex-a7/branch.json | 8 +
> .../arch/arm64/arm/cortex-a7/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a7/cache.json | 32 +++
> .../arch/arm64/arm/cortex-a7/exception.json | 11 +
> .../arch/arm64/arm/cortex-a7/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a7/memory.json | 8 +
> .../arch/arm64/arm/cortex-a710/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a710/bus.json | 20 ++
> .../arch/arm64/arm/cortex-a710/cache.json | 155 ++++++++++++
> .../arch/arm64/arm/cortex-a710/exception.json | 47 ++++
> .../arm64/arm/cortex-a710/instruction.json | 134 ++++++++++
> .../arch/arm64/arm/cortex-a710/memory.json | 41 +++
> .../arch/arm64/arm/cortex-a710/pipeline.json | 23 ++
> .../arch/arm64/arm/cortex-a710/trace.json | 29 +++
> .../arch/arm64/arm/cortex-a73/branch.json | 11 +
> .../arch/arm64/arm/cortex-a73/bus.json | 23 ++
> .../arch/arm64/arm/cortex-a73/cache.json | 107 ++++++++
> .../arch/arm64/arm/cortex-a73/etm.json | 14 ++
> .../arch/arm64/arm/cortex-a73/exception.json | 14 ++
> .../arm64/arm/cortex-a73/instruction.json | 65 +++++
> .../arch/arm64/arm/cortex-a73/memory.json | 14 ++
> .../arch/arm64/arm/cortex-a73/mmu.json | 44 ++++
> .../arch/arm64/arm/cortex-a73/pipeline.json | 38 +++
> .../arch/arm64/arm/cortex-a75/branch.json | 11 +
> .../arch/arm64/arm/cortex-a75/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a75/cache.json | 164 ++++++++++++
> .../arch/arm64/arm/cortex-a75/etm.json | 14 ++
> .../arch/arm64/arm/cortex-a75/exception.json | 17 ++
> .../arm64/arm/cortex-a75/instruction.json | 74 ++++++
> .../arch/arm64/arm/cortex-a75/memory.json | 17 ++
> .../arch/arm64/arm/cortex-a75/mmu.json | 44 ++++
> .../arch/arm64/arm/cortex-a75/pipeline.json | 44 ++++
> .../arch/arm64/arm/cortex-a77/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a77/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a77/cache.json | 143 +++++++++++
> .../arch/arm64/arm/cortex-a77/exception.json | 47 ++++
> .../arm64/arm/cortex-a77/instruction.json | 77 ++++++
> .../arch/arm64/arm/cortex-a77/memory.json | 23 ++
> .../arch/arm64/arm/cortex-a77/pipeline.json | 8 +
> .../arch/arm64/arm/cortex-a78/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a78/bus.json | 20 ++
> .../arch/arm64/arm/cortex-a78/cache.json | 155 ++++++++++++
> .../arch/arm64/arm/cortex-a78/exception.json | 47 ++++
> .../arm64/arm/cortex-a78/instruction.json | 80 ++++++
> .../arch/arm64/arm/cortex-a78/memory.json | 23 ++
> .../arch/arm64/arm/cortex-a78/pipeline.json | 23 ++
> .../arch/arm64/arm/cortex-a8/branch.json | 8 +
> .../arch/arm64/arm/cortex-a8/cache.json | 77 ++++++
> .../arch/arm64/arm/cortex-a8/exception.json | 5 +
> .../arch/arm64/arm/cortex-a8/instruction.json | 38 +++
> .../arch/arm64/arm/cortex-a8/memory.json | 5 +
> .../arch/arm64/arm/cortex-a9/branch.json | 8 +
> .../arch/arm64/arm/cortex-a9/cache.json | 17 ++
> .../arch/arm64/arm/cortex-a9/exception.json | 5 +
> .../arch/arm64/arm/cortex-a9/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a9/memory.json | 5 +
> .../arch/arm64/arm/cortex-x1/branch.json | 17 ++
> .../arch/arm64/arm/cortex-x1/bus.json | 20 ++
> .../arch/arm64/arm/cortex-x1/cache.json | 155 ++++++++++++
> .../arch/arm64/arm/cortex-x1/exception.json | 47 ++++
> .../arch/arm64/arm/cortex-x1/instruction.json | 80 ++++++
> .../arch/arm64/arm/cortex-x1/memory.json | 23 ++
> .../arch/arm64/arm/cortex-x1/pipeline.json | 23 ++
> .../arch/arm64/arm/cortex-x2/branch.json | 17 ++
> .../arch/arm64/arm/cortex-x2/bus.json | 20 ++
> .../arch/arm64/arm/cortex-x2/cache.json | 155 ++++++++++++
> .../arch/arm64/arm/cortex-x2/exception.json | 47 ++++
> .../arch/arm64/arm/cortex-x2/instruction.json | 134 ++++++++++
> .../arch/arm64/arm/cortex-x2/memory.json | 41 +++
> .../arch/arm64/arm/cortex-x2/pipeline.json | 23 ++
> .../arch/arm64/arm/cortex-x2/trace.json | 29 +++
> .../arch/arm64/arm/neoverse-e1/branch.json | 17 ++
> .../arch/arm64/arm/neoverse-e1/bus.json | 17 ++
> .../arch/arm64/arm/neoverse-e1/cache.json | 107 ++++++++
> .../arch/arm64/arm/neoverse-e1/exception.json | 14 ++
> .../arm64/arm/neoverse-e1/instruction.json | 65 +++++
> .../arch/arm64/arm/neoverse-e1/memory.json | 23 ++
> .../arch/arm64/arm/neoverse-e1/pipeline.json | 8 +
> .../arch/arm64/arm/neoverse-e1/spe.json | 14 ++
> .../arch/arm64/common-and-microarch.json | 66 +++++
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 20 ++
> 141 files changed, 5746 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json
>
> --
> 2.25.1

--

- Arnaldo

2022-05-10 21:05:59

by John Garry

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On 10/05/2022 16:50, Arnaldo Carvalho de Melo wrote:
> Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>> below.
>>
>> Changesets are dependent due to incremental updates to the common events
>> file and mapfile.csv.
>>
>> Data is sourced fromhttps://github.com/ARM-software/data
> Waiting for reviews to merge this.
>

I'll have a closer look this week.

@Nick, Just curious, do you have some tool/script to convert from the
JSON format @ https://github.com/ARM-software/data/blob/master/pmu/ to
the "linux" format?

Thanks,
John


2022-05-10 21:44:49

by Nick Forrington

[permalink] [raw]
Subject: [PATCH 16/20] perf vendors events arm64: Arm Cortex-A78

Add PMU events for Arm Cortex-A78
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a78.json

which is based on PMU event descriptions from the Arm Cortex-A78 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Signed-off-by: Nick Forrington <[email protected]>
---
.../arch/arm64/arm/cortex-a78/branch.json | 17 ++
.../arch/arm64/arm/cortex-a78/bus.json | 20 +++
.../arch/arm64/arm/cortex-a78/cache.json | 155 ++++++++++++++++++
.../arch/arm64/arm/cortex-a78/exception.json | 47 ++++++
.../arm64/arm/cortex-a78/instruction.json | 80 +++++++++
.../arch/arm64/arm/cortex-a78/memory.json | 23 +++
.../arch/arm64/arm/cortex-a78/pipeline.json | 23 +++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
8 files changed, 366 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
new file mode 100644
index 000000000000..2f2d137f5f55
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
new file mode 100644
index 000000000000..579c1c993d17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
@@ -0,0 +1,20 @@
+[
+ {
+ "ArchStdEvent": "CPU_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS"
+ },
+ {
+ "ArchStdEvent": "BUS_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "CNT_CYCLES"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
new file mode 100644
index 000000000000..0141f749bff3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
@@ -0,0 +1,155 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB"
+ },
+ {
+ "ArchStdEvent": "DTLB_WALK"
+ },
+ {
+ "ArchStdEvent": "ITLB_WALK"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_MISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_LMISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_WR"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE_LMISS"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_LMISS_RD"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_LMISS_RD"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
new file mode 100644
index 000000000000..344a2d552ad5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
@@ -0,0 +1,47 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ },
+ {
+ "ArchStdEvent": "MEMORY_ERROR"
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF"
+ },
+ {
+ "ArchStdEvent": "EXC_SVC"
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ"
+ },
+ {
+ "ArchStdEvent": "EXC_SMC"
+ },
+ {
+ "ArchStdEvent": "EXC_HVC"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
new file mode 100644
index 000000000000..a9edd52843a1
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
@@ -0,0 +1,80 @@
+[
+ {
+ "ArchStdEvent": "SW_INCR"
+ },
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "TTBR_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_MIS_PRED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "OP_RETIRED"
+ },
+ {
+ "ArchStdEvent": "OP_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC"
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC"
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC"
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC"
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
new file mode 100644
index 000000000000..5aff6e93c1ad
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
@@ -0,0 +1,23 @@
+[
+ {
+ "ArchStdEvent": "MEM_ACCESS"
+ },
+ {
+ "ArchStdEvent": "REMOTE_ACCESS"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
new file mode 100644
index 000000000000..f9fae15f7555
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
@@ -0,0 +1,23 @@
+[
+ {
+ "ArchStdEvent": "STALL_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND"
+ },
+ {
+ "ArchStdEvent": "STALL"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT_BACKEND"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND_MEM"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 1fa58d247132..31a43b5114bc 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -33,6 +33,7 @@
0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
0x00000000410fd0d0,v1,arm/cortex-a77,core
0x00000000410fd400,v1,arm/neoverse-v1,core
+0x00000000410fd410,v1,arm/cortex-a78,core
0x00000000410fd460,v1,arm/cortex-a510,core
0x00000000410fd490,v1,arm/neoverse-n2,core
0x00000000420f5160,v1,cavium/thunderx2,core
--
2.25.1


2022-05-14 04:23:36

by Nick Forrington

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On 10/05/2022 16:55, John Garry wrote:
> On 10/05/2022 16:50, Arnaldo Carvalho de Melo wrote:
>> Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>>> below.
>>>
>>> Changesets are dependent due to incremental updates to the common
>>> events
>>> file and mapfile.csv.
>>>
>>> Data is sourced fromhttps://github.com/ARM-software/data
>> Waiting for reviews to merge this.
>>
>
> I'll have a closer look this week.
>
> @Nick, Just curious, do you have some tool/script to convert from the
> JSON format @ https://github.com/ARM-software/data/blob/master/pmu/ to
> the "linux" format?

Thanks John.

We do have a conversion script, although it isn't publically available
anywhere at the moment.

Thanks,
Nick


2022-05-16 10:26:12

by Ian Rogers

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On Thu, May 12, 2022 at 8:53 AM John Garry <[email protected]> wrote:
>
> On 12/05/2022 14:01, Nick Forrington wrote:
> > On 10/05/2022 16:55, John Garry wrote:
> >> On 10/05/2022 16:50, Arnaldo Carvalho de Melo wrote:
> >>> Em Tue, May 10, 2022 at 11:47:38AM +0100, Nick Forrington escreveu:
> >>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
> >>>> below.
> >>>>
> >>>> Changesets are dependent due to incremental updates to the common
> >>>> events
> >>>> file and mapfile.csv.
> >>>>
> >>>> Data is sourced fromhttps://github.com/ARM-software/data
> >>> Waiting for reviews to merge this.
> >>>
> >>
> >> I'll have a closer look this week
>
> Generally this looks ok:
>
> Reviewed-by: John Garry <[email protected]>
>
> If you are feeling particularly helpful then you can add support for any
> events missing to pre-existing core support, like a57-a72.
>
> Thanks,
> john

I'll raise John's "ok" and say this looks great! :-D Some thoughts:

The mapfile.csv cpuid values don't directly align with:
https://github.com/ARM-software/data/blob/master/cpus.json
but this definitely looks deliberate.

The new events lack the PMU "Unit" value. The current perf json is
pretty free form and leads to problems if two PMUs are present.
Context is here:
https://lore.kernel.org/lkml/CAP-5=fWRRZsyJZ-gky-FOFz79zW_3r78d_0APpj5sf66HqTpLw@mail.gmail.com/

My idea to rationalize this is to mirror what is already done in
sysfs, that is the event data is specific to a PMU. As a lot of "Unit"
values are missing from events on x86 a reasonable guess if the "Unit"
is missing is to use "cpu". Poking a Google Pixel 4a, I see that all
PMU data is in "armv8_pmuv3". So for ARM I could guess this is always
the case, ie all events should belong to armv8_pmuv3. This may not be
right and could lead to confusion like an event BR_COND_MIS_PRED
having an alias of "armv8_pmuv3/BR_COND_MIS_PRED/" but it really
should have some other PMU name in there. I just raise this in case
there is a fix for this we could incorporate into this patch series,
maybe "armv8_pmuv3" is always the PMU and my life is easy.

Thanks,
Ian

2022-05-16 14:58:09

by Nick Forrington

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On 12/05/2022 16:52, John Garry wrote:
> Generally this looks ok:
>
> Reviewed-by: John Garry <[email protected]>
>
> If you are feeling particularly helpful then you can add support for
> any events missing to pre-existing core support, like a57-a72.

Thanks John.

I'll submit a separate patch for A57/A72.

Nick


2022-05-17 00:46:42

by Ian Rogers

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On Mon, May 16, 2022 at 4:10 AM John Garry <[email protected]> wrote:
>
> On 15/05/2022 23:03, Ian Rogers wrote:
> > I'll raise John's "ok" and say this looks great!:-D Some thoughts:
> >
> > The mapfile.csv cpuid values don't directly align with:
> > https://github.com/ARM-software/data/blob/master/cpus.json
> > but this definitely looks deliberate.
> >
>
> Hi Ian,
>
> > The new events lack the PMU "Unit" value.
>
> For arm support we work on the basis that no "Unit" means CPU PMU. I
> assume the same for other archs, but maybe this hybrid PMU support
> changes that.
>
> > The current perf json is
> > pretty free form and leads to problems if two PMUs are present.
>
> Can you clarify - for my benefit - exactly what you mean by "two PMUs
> are present"?

On Alderlake there is a cpu_core and cpu_atom. The event codes, etc.
vary between them - there is no notion of architecture standard
events.

> > Context is here:
> > https://lore.kernel.org/lkml/CAP-5=fWRRZsyJZ-gky-FOFz79zW_3r78d_0APpj5sf66HqTpLw@mail.gmail.com/
> >
>
> We have another problem but I am not sure if exactly the same.
>
> The issue is that if we have an event alias "cycles" for an uncore PMU,
> then if we use "stat" command then perf tool matches "cycles" to CPU
> cycles and not the uncore PMU, which we would not want.
>
> We have ways to work around it, though.

Ack.

> > My idea to rationalize this is to mirror what is already done in
> > sysfs, that is the event data is specific to a PMU. As a lot of "Unit"
> > values are missing from events on x86 a reasonable guess if the "Unit"
> > is missing is to use "cpu".
>
> This sounds like what I mentioned in the reply to 1/20:
>
> "I had a patch series which makes perf read the armv8 pmu
> sysfs event file to learn all the events which the core supports and
> create the aliases from that. So, in this, we don't require the JSONs to
> list these events explicitly. "
>
> Is this like what Andi was talking about in terms of runtime loading?

I think Andi is talking about loading the json style events at
runtime. The existing jevents.c code could be linked into the perf
tool whereas the jevents.py rewrite would be harder.

Thanks,
Ian

> > Poking a Google Pixel 4a, I see that all
> > PMU data is in "armv8_pmuv3". So for ARM I could guess this is always
> > the case, ie all events should belong to armv8_pmuv3. This may not be
> > right and could lead to confusion like an event BR_COND_MIS_PRED
> > having an alias of "armv8_pmuv3/BR_COND_MIS_PRED/" but it really
> > should have some other PMU name in there. I just raise this in case
> > there is a fix for this we could incorporate into this patch series,
> > maybe "armv8_pmuv3" is always the PMU and my life is easy.
>
> Thanks,
> John

2022-05-17 01:08:33

by Nick Forrington

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On 15/05/2022 23:03, Ian Rogers wrote:
> On Thu, May 12, 2022 at 8:53 AM John Garry <[email protected]> wrote:
>
> Generally this looks ok:
>
> Reviewed-by: John Garry <[email protected]>
>
> If you are feeling particularly helpful then you can add support for any
> events missing to pre-existing core support, like a57-a72.
>
> I'll raise John's "ok" and say this looks great! :-D Some thoughts:

Thanks Ian!

> The mapfile.csv cpuid values don't directly align with:
> https://github.com/ARM-software/data/blob/master/cpus.json
> but this definitely looks deliberate.

Correct - they use different formats.

mapfile.csv uses the MIDR format

https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/midr-el1--main-id-register--el1

The cpus.json "cpuid" is the implementer and part number from the MIDR
(the other fields are always fixed in mapfile.csv)
> The new events lack the PMU "Unit" value. The current perf json is
> pretty free form and leads to problems if two PMUs are present.
> Context is here:
> https://lore.kernel.org/lkml/CAP-5=fWRRZsyJZ-gky-FOFz79zW_3r78d_0APpj5sf66HqTpLw@mail.gmail.com/
>
> My idea to rationalize this is to mirror what is already done in
> sysfs, that is the event data is specific to a PMU. As a lot of "Unit"
> values are missing from events on x86 a reasonable guess if the "Unit"
> is missing is to use "cpu". Poking a Google Pixel 4a, I see that all
> PMU data is in "armv8_pmuv3". So for ARM I could guess this is always
> the case, ie all events should belong to armv8_pmuv3. This may not be
> right and could lead to confusion like an event BR_COND_MIS_PRED
> having an alias of "armv8_pmuv3/BR_COND_MIS_PRED/" but it really
> should have some other PMU name in there. I just raise this in case
> there is a fix for this we could incorporate into this patch series,
> maybe "armv8_pmuv3" is always the PMU and my life is easy.

My understanding is that all JSON events under arm64/arm apply to the
CPU PMU, although there could be 2 (or more) armv8_pmuv3 devices in a
herterogeneous system (armv8_pmuv3_0, armv8_pmuv3_1, ...) - each with
different events.

So I don't think static "Unit" data would be helpful, but it should be
possible to map JSON events to appropriate CPUs with existing data.

e.g. /sys/bus/event_source/devices/armv8_pmuv3_0/cpus shows the CPUs
associated with a PMU device, and each CPU can be mapped to JSON events
via the MIDR (as is done already)

Thanks,
Nick


2022-05-17 01:25:14

by John Garry

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On 15/05/2022 23:03, Ian Rogers wrote:
> I'll raise John's "ok" and say this looks great!:-D Some thoughts:
>
> The mapfile.csv cpuid values don't directly align with:
> https://github.com/ARM-software/data/blob/master/cpus.json
> but this definitely looks deliberate.
>

Hi Ian,

> The new events lack the PMU "Unit" value.

For arm support we work on the basis that no "Unit" means CPU PMU. I
assume the same for other archs, but maybe this hybrid PMU support
changes that.

> The current perf json is
> pretty free form and leads to problems if two PMUs are present.

Can you clarify - for my benefit - exactly what you mean by "two PMUs
are present"?

> Context is here:
> https://lore.kernel.org/lkml/CAP-5=fWRRZsyJZ-gky-FOFz79zW_3r78d_0APpj5sf66HqTpLw@mail.gmail.com/
>

We have another problem but I am not sure if exactly the same.

The issue is that if we have an event alias "cycles" for an uncore PMU,
then if we use "stat" command then perf tool matches "cycles" to CPU
cycles and not the uncore PMU, which we would not want.

We have ways to work around it, though.

> My idea to rationalize this is to mirror what is already done in
> sysfs, that is the event data is specific to a PMU. As a lot of "Unit"
> values are missing from events on x86 a reasonable guess if the "Unit"
> is missing is to use "cpu".

This sounds like what I mentioned in the reply to 1/20:

"I had a patch series which makes perf read the armv8 pmu
sysfs event file to learn all the events which the core supports and
create the aliases from that. So, in this, we don't require the JSONs to
list these events explicitly. "

Is this like what Andi was talking about in terms of runtime loading?

> Poking a Google Pixel 4a, I see that all
> PMU data is in "armv8_pmuv3". So for ARM I could guess this is always
> the case, ie all events should belong to armv8_pmuv3. This may not be
> right and could lead to confusion like an event BR_COND_MIS_PRED
> having an alias of "armv8_pmuv3/BR_COND_MIS_PRED/" but it really
> should have some other PMU name in there. I just raise this in case
> there is a fix for this we could incorporate into this patch series,
> maybe "armv8_pmuv3" is always the PMU and my life is easy.

Thanks,
John

2022-05-18 04:51:37

by Robin Murphy

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

Hi Nick,

On 2022-05-10 11:47, Nick Forrington wrote:
> Add Performance Monitoring Unit event data for the Arm CPUs listed
> below.
>
> Changesets are dependent due to incremental updates to the common events
> file and mapfile.csv.
>
> Data is sourced from https://github.com/ARM-software/data
>
> Nick Forrington (20):
> perf vendors events arm64: Arm Cortex-A5
> perf vendors events arm64: Arm Cortex-A7
> perf vendors events arm64: Arm Cortex-A8
> perf vendors events arm64: Arm Cortex-A9
> perf vendors events arm64: Arm Cortex-A15
> perf vendors events arm64: Arm Cortex-A17
> perf vendors events arm64: Arm Cortex-A32

Obligatory question over anything relating to the above CPUs being in an
"arch/arm64" directory... ;)

Cheers,
Robin.

> perf vendors events arm64: Arm Cortex-A34
> perf vendors events arm64: Arm Cortex-A35
> perf vendors events arm64: Arm Cortex-A55
> perf vendors events arm64: Arm Cortex-A510
> perf vendors events arm64: Arm Cortex-A65
> perf vendors events arm64: Arm Cortex-A73
> perf vendors events arm64: Arm Cortex-A75
> perf vendors events arm64: Arm Cortex-A77
> perf vendors events arm64: Arm Cortex-A78
> perf vendors events arm64: Arm Cortex-A710
> perf vendors events arm64: Arm Cortex-X1
> perf vendors events arm64: Arm Cortex-X2
> perf vendors events arm64: Arm Neoverse E1
>
> .../arch/arm64/arm/cortex-a15/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a15/bus.json | 29 +++
> .../arch/arm64/arm/cortex-a15/cache.json | 80 ++++++
> .../arch/arm64/arm/cortex-a15/exception.json | 8 +
> .../arm64/arm/cortex-a15/instruction.json | 59 +++++
> .../arch/arm64/arm/cortex-a15/memory.json | 20 ++
> .../arch/arm64/arm/cortex-a17/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a17/bus.json | 26 ++
> .../arch/arm64/arm/cortex-a17/cache.json | 53 ++++
> .../arch/arm64/arm/cortex-a17/exception.json | 11 +
> .../arm64/arm/cortex-a17/instruction.json | 56 +++++
> .../arch/arm64/arm/cortex-a17/memory.json | 20 ++
> .../arch/arm64/arm/cortex-a32/branch.json | 11 +
> .../arch/arm64/arm/cortex-a32/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a32/cache.json | 32 +++
> .../arch/arm64/arm/cortex-a32/exception.json | 14 ++
> .../arm64/arm/cortex-a32/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a32/memory.json | 8 +
> .../arch/arm64/arm/cortex-a34/branch.json | 11 +
> .../arch/arm64/arm/cortex-a34/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a34/cache.json | 32 +++
> .../arch/arm64/arm/cortex-a34/exception.json | 14 ++
> .../arm64/arm/cortex-a34/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a34/memory.json | 8 +
> .../arch/arm64/arm/cortex-a35/branch.json | 11 +
> .../arch/arm64/arm/cortex-a35/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a35/cache.json | 32 +++
> .../arch/arm64/arm/cortex-a35/exception.json | 14 ++
> .../arm64/arm/cortex-a35/instruction.json | 44 ++++
> .../arch/arm64/arm/cortex-a35/memory.json | 8 +
> .../arch/arm64/arm/cortex-a5/branch.json | 8 +
> .../arch/arm64/arm/cortex-a5/cache.json | 23 ++
> .../arch/arm64/arm/cortex-a5/exception.json | 11 +
> .../arch/arm64/arm/cortex-a5/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a5/memory.json | 8 +
> .../arch/arm64/arm/cortex-a510/branch.json | 59 +++++
> .../arch/arm64/arm/cortex-a510/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a510/cache.json | 182 ++++++++++++++
> .../arch/arm64/arm/cortex-a510/exception.json | 14 ++
> .../arm64/arm/cortex-a510/instruction.json | 95 +++++++
> .../arch/arm64/arm/cortex-a510/memory.json | 32 +++
> .../arch/arm64/arm/cortex-a510/pipeline.json | 107 ++++++++
> .../arch/arm64/arm/cortex-a510/pmu.json | 8 +
> .../arch/arm64/arm/cortex-a510/trace.json | 32 +++
> .../arch/arm64/arm/cortex-a55/branch.json | 59 +++++
> .../arch/arm64/arm/cortex-a55/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a55/cache.json | 188 ++++++++++++++
> .../arch/arm64/arm/cortex-a55/exception.json | 20 ++
> .../arm64/arm/cortex-a55/instruction.json | 65 +++++
> .../arch/arm64/arm/cortex-a55/memory.json | 17 ++
> .../arch/arm64/arm/cortex-a55/pipeline.json | 80 ++++++
> .../arch/arm64/arm/cortex-a65/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a65/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a65/cache.json | 236 ++++++++++++++++++
> .../arch/arm64/arm/cortex-a65/dpu.json | 32 +++
> .../arch/arm64/arm/cortex-a65/exception.json | 14 ++
> .../arch/arm64/arm/cortex-a65/ifu.json | 122 +++++++++
> .../arm64/arm/cortex-a65/instruction.json | 71 ++++++
> .../arch/arm64/arm/cortex-a65/memory.json | 35 +++
> .../arch/arm64/arm/cortex-a65/pipeline.json | 8 +
> .../arch/arm64/arm/cortex-a7/branch.json | 8 +
> .../arch/arm64/arm/cortex-a7/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a7/cache.json | 32 +++
> .../arch/arm64/arm/cortex-a7/exception.json | 11 +
> .../arch/arm64/arm/cortex-a7/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a7/memory.json | 8 +
> .../arch/arm64/arm/cortex-a710/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a710/bus.json | 20 ++
> .../arch/arm64/arm/cortex-a710/cache.json | 155 ++++++++++++
> .../arch/arm64/arm/cortex-a710/exception.json | 47 ++++
> .../arm64/arm/cortex-a710/instruction.json | 134 ++++++++++
> .../arch/arm64/arm/cortex-a710/memory.json | 41 +++
> .../arch/arm64/arm/cortex-a710/pipeline.json | 23 ++
> .../arch/arm64/arm/cortex-a710/trace.json | 29 +++
> .../arch/arm64/arm/cortex-a73/branch.json | 11 +
> .../arch/arm64/arm/cortex-a73/bus.json | 23 ++
> .../arch/arm64/arm/cortex-a73/cache.json | 107 ++++++++
> .../arch/arm64/arm/cortex-a73/etm.json | 14 ++
> .../arch/arm64/arm/cortex-a73/exception.json | 14 ++
> .../arm64/arm/cortex-a73/instruction.json | 65 +++++
> .../arch/arm64/arm/cortex-a73/memory.json | 14 ++
> .../arch/arm64/arm/cortex-a73/mmu.json | 44 ++++
> .../arch/arm64/arm/cortex-a73/pipeline.json | 38 +++
> .../arch/arm64/arm/cortex-a75/branch.json | 11 +
> .../arch/arm64/arm/cortex-a75/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a75/cache.json | 164 ++++++++++++
> .../arch/arm64/arm/cortex-a75/etm.json | 14 ++
> .../arch/arm64/arm/cortex-a75/exception.json | 17 ++
> .../arm64/arm/cortex-a75/instruction.json | 74 ++++++
> .../arch/arm64/arm/cortex-a75/memory.json | 17 ++
> .../arch/arm64/arm/cortex-a75/mmu.json | 44 ++++
> .../arch/arm64/arm/cortex-a75/pipeline.json | 44 ++++
> .../arch/arm64/arm/cortex-a77/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a77/bus.json | 17 ++
> .../arch/arm64/arm/cortex-a77/cache.json | 143 +++++++++++
> .../arch/arm64/arm/cortex-a77/exception.json | 47 ++++
> .../arm64/arm/cortex-a77/instruction.json | 77 ++++++
> .../arch/arm64/arm/cortex-a77/memory.json | 23 ++
> .../arch/arm64/arm/cortex-a77/pipeline.json | 8 +
> .../arch/arm64/arm/cortex-a78/branch.json | 17 ++
> .../arch/arm64/arm/cortex-a78/bus.json | 20 ++
> .../arch/arm64/arm/cortex-a78/cache.json | 155 ++++++++++++
> .../arch/arm64/arm/cortex-a78/exception.json | 47 ++++
> .../arm64/arm/cortex-a78/instruction.json | 80 ++++++
> .../arch/arm64/arm/cortex-a78/memory.json | 23 ++
> .../arch/arm64/arm/cortex-a78/pipeline.json | 23 ++
> .../arch/arm64/arm/cortex-a8/branch.json | 8 +
> .../arch/arm64/arm/cortex-a8/cache.json | 77 ++++++
> .../arch/arm64/arm/cortex-a8/exception.json | 5 +
> .../arch/arm64/arm/cortex-a8/instruction.json | 38 +++
> .../arch/arm64/arm/cortex-a8/memory.json | 5 +
> .../arch/arm64/arm/cortex-a9/branch.json | 8 +
> .../arch/arm64/arm/cortex-a9/cache.json | 17 ++
> .../arch/arm64/arm/cortex-a9/exception.json | 5 +
> .../arch/arm64/arm/cortex-a9/instruction.json | 29 +++
> .../arch/arm64/arm/cortex-a9/memory.json | 5 +
> .../arch/arm64/arm/cortex-x1/branch.json | 17 ++
> .../arch/arm64/arm/cortex-x1/bus.json | 20 ++
> .../arch/arm64/arm/cortex-x1/cache.json | 155 ++++++++++++
> .../arch/arm64/arm/cortex-x1/exception.json | 47 ++++
> .../arch/arm64/arm/cortex-x1/instruction.json | 80 ++++++
> .../arch/arm64/arm/cortex-x1/memory.json | 23 ++
> .../arch/arm64/arm/cortex-x1/pipeline.json | 23 ++
> .../arch/arm64/arm/cortex-x2/branch.json | 17 ++
> .../arch/arm64/arm/cortex-x2/bus.json | 20 ++
> .../arch/arm64/arm/cortex-x2/cache.json | 155 ++++++++++++
> .../arch/arm64/arm/cortex-x2/exception.json | 47 ++++
> .../arch/arm64/arm/cortex-x2/instruction.json | 134 ++++++++++
> .../arch/arm64/arm/cortex-x2/memory.json | 41 +++
> .../arch/arm64/arm/cortex-x2/pipeline.json | 23 ++
> .../arch/arm64/arm/cortex-x2/trace.json | 29 +++
> .../arch/arm64/arm/neoverse-e1/branch.json | 17 ++
> .../arch/arm64/arm/neoverse-e1/bus.json | 17 ++
> .../arch/arm64/arm/neoverse-e1/cache.json | 107 ++++++++
> .../arch/arm64/arm/neoverse-e1/exception.json | 14 ++
> .../arm64/arm/neoverse-e1/instruction.json | 65 +++++
> .../arch/arm64/arm/neoverse-e1/memory.json | 23 ++
> .../arch/arm64/arm/neoverse-e1/pipeline.json | 8 +
> .../arch/arm64/arm/neoverse-e1/spe.json | 14 ++
> .../arch/arm64/common-and-microarch.json | 66 +++++
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 20 ++
> 141 files changed, 5746 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a15/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a17/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a32/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a5/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a7/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a8/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a9/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json
>

2022-05-18 12:48:01

by Robin Murphy

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On 2022-05-18 09:15, John Garry wrote:
> On 17/05/2022 15:32, Robin Murphy wrote:
>>
>> On 2022-05-10 11:47, Nick Forrington wrote:
>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>>> below.
>>>
>>> Changesets are dependent due to incremental updates to the common events
>>> file and mapfile.csv.
>>>
>>> Data is sourced from https://github.com/ARM-software/data
>>>
>>> Nick Forrington (20):
>>>    perf vendors events arm64: Arm Cortex-A5
>>>    perf vendors events arm64: Arm Cortex-A7
>>>    perf vendors events arm64: Arm Cortex-A8
>>>    perf vendors events arm64: Arm Cortex-A9
>>>    perf vendors events arm64: Arm Cortex-A15
>>>    perf vendors events arm64: Arm Cortex-A17
>>>    perf vendors events arm64: Arm Cortex-A32
>>
>> Obligatory question over anything relating to the above CPUs being in
>> an "arch/arm64" directory... ;)
>
> If we were to add to arm32/arm then the common event numbers and maybe
> other JSONs in future would need to be duplicated.
>
> Would there be any reason to add to arm32/arm apart to from being
> strictly proper? Maybe if lots of other 32b support for other vendors
> came along then it could make sense (to separate them out).

That's the heart of the question, really. At best it seems unnecessarily
confusing as-is. AFAICS either the naming isn't functional, wherein it
would potentially make the most sense to rename the whole thing
"pmu-events/arch/arm" if it's merely for categorising Arm architectures
in general, or it is actually tied to the host triplet, in which case
the above patches are most likely useless.

I'd agree that there doesn't seem much point in trying to separate
things along relatively arbitrary lines if it *isn't* functionally
necessary - the PMUv2 common events look to be a straightforward subset
of the PMUv3 ones, but then there's Cortex-A32 anyway, plus most of the
already-supported CPUs could equally run an AArch32 perf tool as well.

Thanks,
Robin.

2022-05-18 14:18:41

by Robin Murphy

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On 2022-05-18 14:48, John Garry wrote:
> On 18/05/2022 13:32, Robin Murphy wrote:
>>> If we were to add to arm32/arm then the common event numbers and
>>> maybe other JSONs in future would need to be duplicated.
>>>
>>> Would there be any reason to add to arm32/arm apart to from being
>>> strictly proper? Maybe if lots of other 32b support for other vendors
>>> came along then it could make sense (to separate them out).
>>
>> That's the heart of the question, really. At best it seems
>> unnecessarily confusing as-is.
>
> I think it comes down to the first core supported was TX2 and the build
> system relies on the target arch to decide which arch from
> pmu-events/arch to compile.
>
>> AFAICS either the naming isn't functional, wherein it would
>> potentially make the most sense to rename the whole thing
>> "pmu-events/arch/arm" if it's merely for categorising Arm
>> architectures in general, or it is actually tied to the host triplet,
>> in which case the above patches are most likely useless.
>
> Today ARCH=arm has no pmu-events support. I think that it should be easy
> to add plumbing for that. It becomes more tricky with supporting a
> single "arm" folder.
>
> But then do people really care enough about pmu-events for these 32b
> cores? Until now, it seems not.
>
>>
>> I'd agree that there doesn't seem much point in trying to separate
>> things along relatively arbitrary lines if it *isn't* functionally
>> necessary - the PMUv2 common events look to be a straightforward
>> subset of the PMUv3 ones, but then there's Cortex-A32 anyway, plus
>> most of the already-supported CPUs could equally run an AArch32 perf
>> tool as well.
>
> Sure, we should have these 32b cores supported for ARCH=arm if they are
> supported for ARCH=arm64. But then does it even make sense to have A7
> support in arch/arm64?

That's what I'm getting at. If it is tied to the build target as you've
said above, then there is no point in an AArch64 perf tool including
data for CPUs on which that tool cannot possibly run; it's simply a
waste of space.

If there is interest in plumbing in support on AArch32 builds as well,
then I'd still be inclined to have a single arch/arm events directory,
and either do some build-time path munging or just symlink an arch/arm64
sibling back to it. Yes, technically there are AArch64-only CPUs whose
data would then be redundant when building for AArch32, but those are
such a minority that it seems like an entirely reasonable compromise.

Thanks,
Robin.

2022-05-19 23:58:17

by John Garry

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On 18/05/2022 15:14, Robin Murphy wrote:
>> Sure, we should have these 32b cores supported for ARCH=arm if they
>> are supported for ARCH=arm64. But then does it even make sense to have
>> A7 support in arch/arm64?
>
> That's what I'm getting at. If it is tied to the build target as you've
> said above, then there is no point in an AArch64 perf tool including
> data for CPUs on which that tool cannot possibly run; it's simply a
> waste of space.
>
> If there is interest in plumbing in support on AArch32 builds as well,
> then I'd still be inclined to have a single arch/arm events directory,
> and either do some build-time path munging or just symlink an arch/arm64
> sibling back to it. Yes, technically there are AArch64-only CPUs whose
> data would then be redundant when building for AArch32,

If size is an issue then we have ways to cut this down, like doing the
arch standard events fixup dynamically when running perf tool, or even
not describing those events in the JSONs and rely on reading the CPU PMU
events folder to learn which of those events are supported.

> but those are
> such a minority that it seems like an entirely reasonable compromise.

@Nick, Can you drop the 32b core support for arm64? Or, if you really
want them, look into ARCH=arm pmu-events support?

thanks,
John

2022-05-20 08:40:08

by Nick Forrington

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs


On 19/05/2022 08:59, John Garry wrote:
> On 18/05/2022 15:14, Robin Murphy wrote:
>>> Sure, we should have these 32b cores supported for ARCH=arm if they
>>> are supported for ARCH=arm64. But then does it even make sense to
>>> have A7 support in arch/arm64?
>>
>> That's what I'm getting at. If it is tied to the build target as
>> you've said above, then there is no point in an AArch64 perf tool
>> including data for CPUs on which that tool cannot possibly run; it's
>> simply a waste of space.
>>
>> If there is interest in plumbing in support on AArch32 builds as
>> well, then I'd still be inclined to have a single arch/arm events
>> directory, and either do some build-time path munging or just symlink
>> an arch/arm64 sibling back to it. Yes, technically there are
>> AArch64-only CPUs whose data would then be redundant when building
>> for AArch32,
>
> If size is an issue then we have ways to cut this down, like doing the
> arch standard events fixup dynamically when running perf tool, or even
> not describing those events in the JSONs and rely on reading the CPU
> PMU events folder to learn which of those events are supported.
>
> > but those are
> > such a minority that it seems like an entirely reasonable compromise.
>
> @Nick, Can you drop the 32b core support for arm64? Or, if you really
> want them, look into ARCH=arm pmu-events support?

No problem - I'll resubmit without the 32b-only CPUs.

Thanks,
Nick


2022-05-20 11:29:34

by Nick Forrington

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs


On 18/05/2022 09:15, John Garry wrote:
> On 17/05/2022 15:32, Robin Murphy wrote:
>>
>> On 2022-05-10 11:47, Nick Forrington wrote:
>>> Add Performance Monitoring Unit event data for the Arm CPUs listed
>>> below.
>>>
>>> Changesets are dependent due to incremental updates to the common
>>> events
>>> file and mapfile.csv.
>>>
>>> Data is sourced from https://github.com/ARM-software/data
>>>
>>> Nick Forrington (20):
>>>    perf vendors events arm64: Arm Cortex-A5
>>>    perf vendors events arm64: Arm Cortex-A7
>>>    perf vendors events arm64: Arm Cortex-A8
>>>    perf vendors events arm64: Arm Cortex-A9
>>>    perf vendors events arm64: Arm Cortex-A15
>>>    perf vendors events arm64: Arm Cortex-A17
>>>    perf vendors events arm64: Arm Cortex-A32
>>
>> Obligatory question over anything relating to the above CPUs being in
>> an "arch/arm64" directory... ;)
>
> If we were to add to arm32/arm then the common event numbers and maybe
> other JSONs in future would need to be duplicated.
>
> Would there be any reason to add to arm32/arm apart to from being
> strictly proper? Maybe if lots of other 32b support for other vendors
> came along then it could make sense (to separate them out).

Not that I'm aware of, although I don't have these available to test.

I'm happy to re-submit without these CPUs if it simplifies things.

Thanks,
Nick


2022-05-22 13:10:40

by Ian Rogers

[permalink] [raw]
Subject: Re: [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs

On Thu, May 19, 2022 at 6:53 AM Nick Forrington <[email protected]> wrote:
>
>
> On 19/05/2022 08:59, John Garry wrote:
> > On 18/05/2022 15:14, Robin Murphy wrote:
> >>> Sure, we should have these 32b cores supported for ARCH=arm if they
> >>> are supported for ARCH=arm64. But then does it even make sense to
> >>> have A7 support in arch/arm64?
> >>
> >> That's what I'm getting at. If it is tied to the build target as
> >> you've said above, then there is no point in an AArch64 perf tool
> >> including data for CPUs on which that tool cannot possibly run; it's
> >> simply a waste of space.
> >>
> >> If there is interest in plumbing in support on AArch32 builds as
> >> well, then I'd still be inclined to have a single arch/arm events
> >> directory, and either do some build-time path munging or just symlink
> >> an arch/arm64 sibling back to it. Yes, technically there are
> >> AArch64-only CPUs whose data would then be redundant when building
> >> for AArch32,
> >
> > If size is an issue then we have ways to cut this down, like doing the
> > arch standard events fixup dynamically when running perf tool, or even
> > not describing those events in the JSONs and rely on reading the CPU
> > PMU events folder to learn which of those events are supported.
> >
> > > but those are
> > > such a minority that it seems like an entirely reasonable compromise.
> >
> > @Nick, Can you drop the 32b core support for arm64? Or, if you really
> > want them, look into ARCH=arm pmu-events support?
>
> No problem - I'll resubmit without the 32b-only CPUs.
>
> Thanks,
> Nick
>

I'm hoping with jevents.py [1] then we can do a few things on the size front:

1) relocations - the current pattern of generating '.foo = "foo_Bar"'
means that when perf starts the .foo pointer needs to be updated for
the relocation. If we concatenate the strings together then we can
have 1 relocation, but we'll need an offset and length to get .foo's
value and some kind of iteration abstraction. If we do this then we
could also look to compress the string at compile time.
2) sorting events - not really a compiler size improvement but should
lower some runtime memory usage. We shouldn't need to linearly search
event names, sorting at compile time means we can locate faster, less
paging, etc.
3) we've spoken in the past of the problems of cross-architecture
testing of events, metrics, etc. For metrics, we may want to record
events on one architecture and compute metrics on another. One idea is
to have a fuller jevents mode where everything is built into one
binary, which would make size improvements more valuable.

Another thing with jevents.py is trying to make the pmu-events.c
presentation more consistent with sysfs', which may regress things on
size.

Anyway, I think it is good to have more events and I'm excited to see
this merged in a way that's suitable for John. I'm happy to do more
optionality stuff with jevents.py or the build if that can mean having
more events on ARM32.

Thanks,
Ian

[1] https://lore.kernel.org/linux-perf-users/[email protected]/
- show your love with Acked-bys :-D