RGMII mode can be enable from dp83822 straps, and also writing bit 9
of register 0x17 - RMII and Status Register (RCSR).
When phy_interface_is_rgmii rgmii mode must be enabled, same for
contrary, this prevents malconfigurations of hw straps
References:
- https://www.ti.com/lit/gpn/dp83822i p66
Signed-off-by: Tommaso Merciai <[email protected]>
Co-developed-by: Michael Trimarchi <[email protected]>
Suggested-by: Alberto Bianchi <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>
---
Changes since v1:
- Improve commit msg
- Add definition of bit 9 reg rcsr (rgmii mode en)
- Handle case: phy_interface_is_rgmii is false
drivers/net/phy/dp83822.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index ce17b2af3218..7cb9d084707b 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -94,6 +94,9 @@
#define DP83822_WOL_INDICATION_SEL BIT(8)
#define DP83822_WOL_CLR_INDICATION BIT(11)
+/* RCSR bits */
+#define DP83822_RGMII_MODE_EN BIT(9)
+
/* RSCR bits */
#define DP83822_RX_CLK_SHIFT BIT(12)
#define DP83822_TX_CLK_SHIFT BIT(11)
@@ -408,6 +411,12 @@ static int dp83822_config_init(struct phy_device *phydev)
if (err)
return err;
}
+
+ phy_set_bits_mmd(phydev, DP83822_DEVADDR,
+ MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
+ } else {
+ phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
+ MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
}
if (dp83822->fx_enabled) {
--
2.25.1
On Thu, May 19, 2022 at 08:50:56PM +0200, Tommaso Merciai wrote:
> RGMII mode can be enable from dp83822 straps, and also writing bit 9
> of register 0x17 - RMII and Status Register (RCSR).
> When phy_interface_is_rgmii rgmii mode must be enabled, same for
> contrary, this prevents malconfigurations of hw straps
>
> References:
> - https://www.ti.com/lit/gpn/dp83822i p66
>
> Signed-off-by: Tommaso Merciai <[email protected]>
> Co-developed-by: Michael Trimarchi <[email protected]>
> Suggested-by: Alberto Bianchi <[email protected]>
> Tested-by: Tommaso Merciai <[email protected]>
> ---
> Changes since v1:
> - Improve commit msg
> - Add definition of bit 9 reg rcsr (rgmii mode en)
> - Handle case: phy_interface_is_rgmii is false
Please don't post a new version for at least 24 hours. Give people
time to review the code and make comments.
Andrew
Hi Tommaso
On Thu, May 19, 2022 at 8:50 PM Tommaso Merciai
<[email protected]> wrote:
>
> RGMII mode can be enable from dp83822 straps, and also writing bit 9
> of register 0x17 - RMII and Status Register (RCSR).
> When phy_interface_is_rgmii rgmii mode must be enabled, same for
> contrary, this prevents malconfigurations of hw straps
>
> References:
> - https://www.ti.com/lit/gpn/dp83822i p66
>
> Signed-off-by: Tommaso Merciai <[email protected]>
> Co-developed-by: Michael Trimarchi <[email protected]>
> Suggested-by: Alberto Bianchi <[email protected]>
> Tested-by: Tommaso Merciai <[email protected]>
> ---
> Changes since v1:
> - Improve commit msg
> - Add definition of bit 9 reg rcsr (rgmii mode en)
> - Handle case: phy_interface_is_rgmii is false
>
> drivers/net/phy/dp83822.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
> index ce17b2af3218..7cb9d084707b 100644
> --- a/drivers/net/phy/dp83822.c
> +++ b/drivers/net/phy/dp83822.c
> @@ -94,6 +94,9 @@
> #define DP83822_WOL_INDICATION_SEL BIT(8)
> #define DP83822_WOL_CLR_INDICATION BIT(11)
>
> +/* RCSR bits */
> +#define DP83822_RGMII_MODE_EN BIT(9)
> +
> /* RSCR bits */
> #define DP83822_RX_CLK_SHIFT BIT(12)
> #define DP83822_TX_CLK_SHIFT BIT(11)
BIT(9) should go here
#define DP83822_RGMII_MODE_EN BIT(9)
#define DP83822_RX_CLK_SHIFT BIT(12)
#define DP83822_TX_CLK_SHIFT BIT(11)
You duplicate the comments up.
> @@ -408,6 +411,12 @@ static int dp83822_config_init(struct phy_device *phydev)
> if (err)
> return err;
> }
> +
> + phy_set_bits_mmd(phydev, DP83822_DEVADDR,
> + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
> + } else {
> + phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
> + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
> }
>
> if (dp83822->fx_enabled) {
> --
> 2.25.1
>
Michael
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
[email protected]
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