Hello
2 sunxi board still does not have ethernet working, orangepi 1+ and
orangepi 3.
This is due to the fact thoses boards have a PHY which need 2 regulators.
A first attempt by Ondřej Jirman was made to support them was made by adding support in
stmmac driver:
https://lore.kernel.org/lkml/[email protected]/
Proposal rejected, since regulators need to be handled by the PHY core.
My first tentative was to just add handling of phy and phy-io in
phy-core:
https://lore.kernel.org/netdev/[email protected]/T/
But having hard-coded phy names was rejected.
Second tentative tryed the same path than clocks and clock-names for
regulators.
https://lore.kernel.org/netdev/[email protected]/t/
But using this was rejected by DT maintainers.
So v3 use a new regulator_bulk_get_all() which grab all supplies
properties in a DT node.
But this way could have some problem, a netdev driver could handle
already its PHY (like dwmac-sun8i already do) and so both phy-core and
the netdev will use both.
It is why phy-supply was renamed in ephy-supply in patch #3.
This serie was tested on whole range of board and PHY architecture:
- internal PHY
* sun8i-h3-orangepi-pc
- external PHY
* sun50i-h6-pine-h64
* sun8i-r40-bananapi-m2-ultra
* sun8i-a83t-bananapi-m3
* sun50i-a64-bananapi-m64
* sun50i-h6-orangepi-3
* sun50i-h5-nanopi-neo-plus2
The resume/suspend of PHY was tested.
Regards
changes since v1:
- Add regulator_bulk_get_all for ease handling of PHY regulators
- Removed all convertion patchs to keep DT compatibility.
Changes since v2:
- removed use of regulator-names and regulators list.
Corentin Labbe (2):
regulator: Add regulator_bulk_get_all
phy: handle optional regulator for PHY
Ondřej Jirman (1):
arm64: dts: allwinner: orange-pi-3: Enable ethernet
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 38 ++++++++
drivers/net/mdio/Kconfig | 1 +
drivers/net/mdio/fwnode_mdio.c | 36 +++++++-
drivers/net/phy/phy_device.c | 10 ++
drivers/regulator/core.c | 92 +++++++++++++++++++
include/linux/phy.h | 3 +
include/linux/regulator/consumer.h | 2 +
7 files changed, 178 insertions(+), 4 deletions(-)
--
2.35.1
From: Ondřej Jirman <[email protected]>
Orange Pi 3 has two regulators that power the Realtek RTL8211E
PHY. According to the datasheet, both regulators need to be enabled
at the same time, or that "phy-io" should be enabled slightly earlier
than "phy" regulator.
RTL8211E/RTL8211EG datasheet says:
Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously
or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power
later than 3.3V power may lead to errors.
The timing is set in DT via startup-delay-us.
Signed-off-by: Ondrej Jirman <[email protected]>
Signed-off-by: Corentin Labbe <[email protected]>
---
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index c45d7b7fb39a..2760a0bf76d5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -13,6 +13,7 @@ / {
compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -55,6 +56,15 @@ led-1 {
};
};
+ reg_gmac_2v5: gmac-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the DC jack */
compatible = "regulator-fixed";
@@ -113,6 +123,33 @@ &ehci3 {
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ /*
+ * The board uses 2.5V RGMII signalling. Power sequence to enable
+ * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
+ * at the same time and to wait 100ms. The driver enables phy-io
+ * first. Delay is achieved with enable-ramp-delay on reg_aldo2.
+ */
+ phy-io-supply = <®_gmac_2v5>;
+ ephy-supply = <®_aldo2>;
+
+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+ reset-assert-us = <15000>;
+ reset-deassert-us = <40000>;
+ };
+};
+
&gpu {
mali-supply = <®_dcdcc>;
status = "okay";
@@ -211,6 +248,7 @@ reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33-audio-tv-ephy-mac";
+ regulator-enable-ramp-delay = <100000>;
};
/* ALDO3 is shorted to CLDO1 */
--
2.35.1