Here is version 2 of the series adding support for job manager Valhall
(v9). CSF Valhall is not supported in this series. The core
issues/features are added for Mali-G57 "Natt" as the current target.
Natt is used in MT8192, which needs a few extra patches to follow
(currently blocked on MediaTek integration issues.)
In terms of userspace, Mesa has almost all the required code for GLES3.1
conformance and is just missing a few patches to merge for remaining
features.
v2 addresses minor issues found in v1, but no major changes.
Alyssa Rosenzweig (9):
dt-bindings: Add compatibles for Mali Valhall GPU
drm/panfrost: Handle HW_ISSUE_TTRX_2968_TTRX_3162
drm/panfrost: Constify argument to has_hw_issue
drm/panfrost: Handle HW_ISSUE_TTRX_3076
drm/panfrost: Add HW_ISSUE_TTRX_3485 quirk
drm/panfrost: Add "clean only safe" feature bit
drm/panfrost: Don't set L2_MMU_CONFIG quirks
drm/panfrost: Add Mali-G57 "Natt" support
drm/panfrost: Add arm,mali-valhall-jm compatible
.../bindings/gpu/arm,mali-bifrost.yaml | 53 +++++++++++++++----
drivers/gpu/drm/panfrost/panfrost_device.c | 9 +++-
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
drivers/gpu/drm/panfrost/panfrost_features.h | 13 +++++
drivers/gpu/drm/panfrost/panfrost_gpu.c | 18 +++----
drivers/gpu/drm/panfrost/panfrost_issues.h | 21 +++++++-
drivers/gpu/drm/panfrost/panfrost_regs.h | 1 +
7 files changed, 91 insertions(+), 25 deletions(-)
--
2.35.1
L2_MMU_CONFIG is an implementation-defined register. Different Mali GPUs
define slightly different MAX_READS and MAX_WRITES fields, which
throttle outstanding reads and writes when set to non-zero values. When
left as zero, reads and writes are not throttled.
Both kbase and panfrost always zero these registers. Per discussion with
Steven Price, there are two reasons these quirks may be used:
1. Simulating slower memory subsystems. This use case is only of
interest to system-on-chip designers; it is not relevant to mainline.
2. Working around broken memory subsystems. Hopefully we never see this
case in mainline. If we do, we'll need to set this register based on
an SoC-compatible, rather than generally matching on the GPU model.
To the best of our knowledge, these fields are zero at reset, so the
write is not necessary. Let's remove the write to aid porting to new
Mali GPUs, which have different layouts for the L2_MMU_CONFIG register.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Suggested-by: Steven Price <[email protected]>
Reviewed-by: Steven Price <[email protected]>
---
drivers/gpu/drm/panfrost/panfrost_gpu.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c
index 295bef27fb55..e1a6e763d0dc 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
+++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
@@ -127,18 +127,6 @@ static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
gpu_write(pfdev, GPU_TILER_CONFIG, quirks);
- quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG);
-
- /* Limit read & write ID width for AXI */
- if (panfrost_has_hw_feature(pfdev, HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG))
- quirks &= ~(L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS |
- L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES);
- else
- quirks &= ~(L2_MMU_CONFIG_LIMIT_EXTERNAL_READS |
- L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES);
-
- gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks);
-
quirks = 0;
if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) &&
pfdev->features.revision >= 0x2000)
--
2.35.1
The most important Valhall-specific quirks have been handled, so add the
Valhall compatible and probe.
v2: Use arm,mali-valhall-jm compatible.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Steven Price <[email protected]>
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 7fcbc2a5b6cd..b48b6f2af029 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -664,6 +664,7 @@ static const struct of_device_id dt_match[] = {
{ .compatible = "arm,mali-t860", .data = &default_data, },
{ .compatible = "arm,mali-t880", .data = &default_data, },
{ .compatible = "arm,mali-bifrost", .data = &default_data, },
+ { .compatible = "arm,mali-valhall-jm", .data = &default_data, },
{ .compatible = "mediatek,mt8183-mali", .data = &mediatek_mt8183_data },
{}
};
--
2.35.1
Add the HW_FEATURE_CLEAN_ONLY_SAFE bit based on kbase. When I actually
tried to port the logic from kbase, trivial jobs raised Data Invalid
Faults, so this may depend on other coherency details. It's still useful
to have the bit to record the feature bit when adding new models.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Steven Price <[email protected]>
---
drivers/gpu/drm/panfrost/panfrost_features.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_features.h b/drivers/gpu/drm/panfrost/panfrost_features.h
index 36fadcf9634e..1a8bdebc86a3 100644
--- a/drivers/gpu/drm/panfrost/panfrost_features.h
+++ b/drivers/gpu/drm/panfrost/panfrost_features.h
@@ -21,6 +21,7 @@ enum panfrost_hw_feature {
HW_FEATURE_TLS_HASHING,
HW_FEATURE_THREAD_GROUP_SPLIT,
HW_FEATURE_IDVS_GROUP_SIZE,
+ HW_FEATURE_CLEAN_ONLY_SAFE,
HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG,
};
--
2.35.1