IBS support has been enhanced with two new features in upcoming uarch:
1. DataSrc extension and 2. L3 miss filtering. Additional set of bits
has been introduced in IBS registers to exploit these features. Define
these new bits into arch/x86/ header.
Signed-off-by: Ravi Bangoria <[email protected]>
Acked-by: Ian Rogers <[email protected]>
---
arch/x86/include/asm/amd-ibs.h | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
index aabdbb5ab920..f3eb098d63d4 100644
--- a/arch/x86/include/asm/amd-ibs.h
+++ b/arch/x86/include/asm/amd-ibs.h
@@ -29,7 +29,10 @@ union ibs_fetch_ctl {
rand_en:1, /* 57: random tagging enable */
fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
* (needs IbsFetchComp) */
- reserved:5; /* 59-63: reserved */
+ l3_miss_only:1, /* 59: Collect L3 miss samples only */
+ fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */
+ fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */
+ reserved:2; /* 62-63: reserved */
};
};
@@ -38,14 +41,14 @@ union ibs_op_ctl {
__u64 val;
struct {
__u64 opmaxcnt:16, /* 0-15: periodic op max. count */
- reserved0:1, /* 16: reserved */
+ l3_miss_only:1, /* 16: Collect L3 miss samples only */
op_en:1, /* 17: op sampling enable */
op_val:1, /* 18: op sample valid */
cnt_ctl:1, /* 19: periodic op counter control */
opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
- reserved1:5, /* 27-31: reserved */
+ reserved0:5, /* 27-31: reserved */
opcurcnt:27, /* 32-58: periodic op counter current count */
- reserved2:5; /* 59-63: reserved */
+ reserved1:5; /* 59-63: reserved */
};
};
@@ -71,11 +74,12 @@ union ibs_op_data {
union ibs_op_data2 {
__u64 val;
struct {
- __u64 data_src:3, /* 0-2: data source */
+ __u64 data_src_lo:3, /* 0-2: data source low */
reserved0:1, /* 3: reserved */
rmt_node:1, /* 4: destination node */
cache_hit_st:1, /* 5: cache hit state */
- reserved1:57; /* 5-63: reserved */
+ data_src_hi:2, /* 6-7: data source high */
+ reserved1:56; /* 8-63: reserved */
};
};
--
2.31.1
On 03-Jun-22 3:18 AM, Namhyung Kim wrote:
> On Tue, May 31, 2022 at 8:30 PM Ravi Bangoria <[email protected]> wrote:
>>
>> IBS support has been enhanced with two new features in upcoming uarch:
>> 1. DataSrc extension and 2. L3 miss filtering. Additional set of bits
>> has been introduced in IBS registers to exploit these features. Define
>> these new bits into arch/x86/ header.
>>
>> Signed-off-by: Ravi Bangoria <[email protected]>
>> Acked-by: Ian Rogers <[email protected]>
>
> Isn't it a part of kernel changes?
Yes, that was left out because in the initial versions I did not have a
separate patch for kernel and tools. So Peter might not have consider it.
In any case, the changes into this header file are not used by kernel
atm. So I'm fine whichever way it goes in.
Thanks,
Ravi
On Tue, May 31, 2022 at 8:30 PM Ravi Bangoria <[email protected]> wrote:
>
> IBS support has been enhanced with two new features in upcoming uarch:
> 1. DataSrc extension and 2. L3 miss filtering. Additional set of bits
> has been introduced in IBS registers to exploit these features. Define
> these new bits into arch/x86/ header.
>
> Signed-off-by: Ravi Bangoria <[email protected]>
> Acked-by: Ian Rogers <[email protected]>
Isn't it a part of kernel changes?
Thanks,
Namhyung
> ---
> arch/x86/include/asm/amd-ibs.h | 16 ++++++++++------
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
> index aabdbb5ab920..f3eb098d63d4 100644
> --- a/arch/x86/include/asm/amd-ibs.h
> +++ b/arch/x86/include/asm/amd-ibs.h
> @@ -29,7 +29,10 @@ union ibs_fetch_ctl {
> rand_en:1, /* 57: random tagging enable */
> fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
> * (needs IbsFetchComp) */
> - reserved:5; /* 59-63: reserved */
> + l3_miss_only:1, /* 59: Collect L3 miss samples only */
> + fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */
> + fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */
> + reserved:2; /* 62-63: reserved */
> };
> };
>
> @@ -38,14 +41,14 @@ union ibs_op_ctl {
> __u64 val;
> struct {
> __u64 opmaxcnt:16, /* 0-15: periodic op max. count */
> - reserved0:1, /* 16: reserved */
> + l3_miss_only:1, /* 16: Collect L3 miss samples only */
> op_en:1, /* 17: op sampling enable */
> op_val:1, /* 18: op sample valid */
> cnt_ctl:1, /* 19: periodic op counter control */
> opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
> - reserved1:5, /* 27-31: reserved */
> + reserved0:5, /* 27-31: reserved */
> opcurcnt:27, /* 32-58: periodic op counter current count */
> - reserved2:5; /* 59-63: reserved */
> + reserved1:5; /* 59-63: reserved */
> };
> };
>
> @@ -71,11 +74,12 @@ union ibs_op_data {
> union ibs_op_data2 {
> __u64 val;
> struct {
> - __u64 data_src:3, /* 0-2: data source */
> + __u64 data_src_lo:3, /* 0-2: data source low */
> reserved0:1, /* 3: reserved */
> rmt_node:1, /* 4: destination node */
> cache_hit_st:1, /* 5: cache hit state */
> - reserved1:57; /* 5-63: reserved */
> + data_src_hi:2, /* 6-7: data source high */
> + reserved1:56; /* 8-63: reserved */
> };
> };
>
> --
> 2.31.1
>